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SIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SOPT1

SNVS_MISC_CTRL

GPR0

GPR1

GPR2

GPR3

MISC_CTRL0

SOPT1CFG

DGO_CTRL0

DGO_CTRL1

DGO_GP1

DGO_GP2

DGO_GP3

DGO_GP4

DGO_GP5

DGO_GP6

DGO_GP7

DGO_GP8

DGO_GP9

DGO_GP10

DGO_GP11

WKPU_WAKEUP_EN

JTAG_ID_REG

A7_TSTMR_CMP_VAL_L

A7_TSTMR_CMP_VAL_H

COMP_CELL_OVERRIDE

HSIC_CAL


SOPT1

SIM Systems Options Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOPT1 SOPT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A7_SW_RESET EN_SEC_VIO PMIC_STBY_REQ MIPI_ISO_DISABLE M4_FPU_DISABLE M4_MPU_DISABLE EN_SNVS_HARD_RST EN_WDG2_HARD_RST

A7_SW_RESET : SW reset for A7 domain.
bits : 0 - 0 (1 bit)
access : write-only

EN_SEC_VIO : Security Violation Enable.
bits : 1 - 1 (1 bit)
access : read-writeOnce

PMIC_STBY_REQ : PMIC Standby Request.
bits : 2 - 2 (1 bit)
access : read-write

MIPI_ISO_DISABLE : MIPI Isolation Disable.
bits : 3 - 3 (1 bit)
access : read-write

M4_FPU_DISABLE : Disables M4 FPU unit.
bits : 5 - 5 (1 bit)
access : read-write

M4_MPU_DISABLE : Disables M4 MPU unit.
bits : 6 - 6 (1 bit)
access : read-write

EN_SNVS_HARD_RST : SNVS_HP system reset enable (Write Once).
bits : 8 - 8 (1 bit)
access : read-writeOnce

EN_WDG2_HARD_RST : Watchdog 2 Reset Enable.
bits : 9 - 9 (1 bit)
access : read-writeOnce


SNVS_MISC_CTRL

SNVS Misc Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNVS_MISC_CTRL SNVS_MISC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC_CAP_TRIM COIN_CELL_CHARGE_EN

OSC_CAP_TRIM : Trims to control the CAP on 32K Oscillator.
bits : 0 - 3 (4 bit)
access : read-write

COIN_CELL_CHARGE_EN : Enables Signal Isolation on SNVS Software Trims and Pull controls (PUS/PUE) until the software writes "1" to this register field. This ensures trim values are held until registers get updated by software after boot up.
bits : 31 - 31 (1 bit)
access : read-write


GPR0

HW SIM General Purpose Register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR0 GPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTR_CLK_DIS OCOTP_CLK_DIS

MTR_CLK_DIS : MBIST clocks disable.
bits : 0 - 0 (1 bit)
access : read-write

OCOTP_CLK_DIS : OCOTP clocks disable.
bits : 1 - 1 (1 bit)
access : read-write


GPR1

HW SIM General Purpose Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR1 GPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_PHY_VLLS_WAKEUP_EN USB_PHY_GLOBAL_WAKEUP_EN

USB_PHY_VLLS_WAKEUP_EN : USB PHY VLLS wakeup enable.
bits : 0 - 0 (1 bit)
access : read-write

USB_PHY_GLOBAL_WAKEUP_EN : USB PHY global wakeup enable.
bits : 1 - 1 (1 bit)
access : read-write


GPR2

HW SIM General Purpose Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR2 GPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPR3

HW SIM General Purpose Register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR3 GPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MISC_CTRL0

HW SIM MISC Register 0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC_CTRL0 MISC_CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB_DELAY_OE_EXTS OBS_CLK_ENABLE M4_OBS_CLK_SRC_SEL M4_OBS_CLK_DIV_RATIO A7_OBS_CLK_SRC_SEL A7_OBS_CLK_DIV_RATIO TESTCLK_TRIM TESTCLK_OBE DISABLE_DDR_HW_AUTO_LP_MODE A7_TSTMR_COMP_EN A7_TO_M4_RST_IRQ_CTRL A7_TO_M4_RST_IRQ_EN A7_TSTMR_COMP_IRQ_CTRL

FB_DELAY_OE_EXTS : Flexbus control of fb_oe delay when exts is enabled.
bits : 0 - 0 (1 bit)
access : read-write

OBS_CLK_ENABLE : Enable that clocks can be observed at M4 CLKOUT, A7 CLKOUT and LVDS clock pads.
bits : 4 - 4 (1 bit)
access : read-write

M4_OBS_CLK_SRC_SEL : Selects the clock to be observed on M4 domain.
bits : 6 - 9 (4 bit)
access : read-write

M4_OBS_CLK_DIV_RATIO : Selection of division rate (2**n) of M4 observation clock div rate = 2**n (n=0..7).
bits : 10 - 12 (3 bit)
access : read-write

A7_OBS_CLK_SRC_SEL : Selects the clock to be observed on A7 domain.
bits : 13 - 16 (4 bit)
access : read-write

A7_OBS_CLK_DIV_RATIO : Selection of division rate (2**n) of A7 observation clock div rate = 2**n (n=0..7).
bits : 17 - 19 (3 bit)
access : read-write

TESTCLK_TRIM : Trim Delay for LVDS TESTCLK_P/TESTCLK_N pad.
bits : 20 - 22 (3 bit)
access : read-write

TESTCLK_OBE : Output Buffer Enable for LVDS TESTCLK_P/TESTCLK_N pad.
bits : 23 - 23 (1 bit)
access : read-write

DISABLE_DDR_HW_AUTO_LP_MODE : Disable control to put DDR in self-refresh mode automatically by HW during low power modes.
bits : 24 - 24 (1 bit)
access : read-write

A7_TSTMR_COMP_EN : Enables the compare of A7 TS Timer versus a programmed value.
bits : 25 - 25 (1 bit)
access : read-write

A7_TO_M4_RST_IRQ_CTRL : Controls the assertion of A7 reset as IRQ/Wake-up to M4.
bits : 26 - 26 (1 bit)
access : read-write

A7_TO_M4_RST_IRQ_EN : Enables the assertion of A7 reset as IRQ/Wake-up to M4.
bits : 27 - 27 (1 bit)
access : read-write

A7_TSTMR_COMP_IRQ_CTRL : Controls the compare of A7 reset as IRQ.
bits : 29 - 29 (1 bit)
access : read-write


SOPT1CFG

SIM SOPT1 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOPT1CFG SOPT1CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK_DPM_PANIC_OUT MASK_DPM_PANIC_IN DSI_PLL_EN DSI_CM DSI_SD QSPI_PULL_TIM_RELAX_b DSI_RST_BYTE_N DSI_RST_ESC_N DSI_RST_DPI_N

MASK_DPM_PANIC_OUT : DPM Panic Out Mask (Write Once).
bits : 0 - 0 (1 bit)
access : read-writeOnce

MASK_DPM_PANIC_IN : DPM Panic In Mask (Write Once).
bits : 1 - 1 (1 bit)
access : read-writeOnce

DSI_PLL_EN : DSI PLL Enable.
bits : 7 - 7 (1 bit)
access : read-write

DSI_CM : DSI Color Mode Control.
bits : 8 - 8 (1 bit)
access : read-write

DSI_SD : DSI Shutdown Control.
bits : 9 - 9 (1 bit)
access : read-write

QSPI_PULL_TIM_RELAX_b : QSPI OBE Assertion Control.
bits : 10 - 10 (1 bit)
access : read-write

DSI_RST_BYTE_N : DSI Reset Byte Control.
bits : 29 - 29 (1 bit)
access : read-write

DSI_RST_ESC_N : DSI Reset Escape Control.
bits : 30 - 30 (1 bit)
access : read-write

DSI_RST_DPI_N : DSI Reset DPI Control.
bits : 31 - 31 (1 bit)
access : read-write


DGO_CTRL0

SIM DGO Control Register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_CTRL0 DGO_CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDATE_DGO_GP1 UPDATE_DGO_GP2 UPDATE_DGO_GP3 UPDATE_DGO_GP4 UPDATE_DGO_GP5 UPDATE_DGO_GP6 WR_ACK_DGO_GP1 WR_ACK_DGO_GP2 WR_ACK_DGO_GP3 WR_ACK_DGO_GP4 WR_ACK_DGO_GP5 WR_ACK_DGO_GP6 INT_EN_ACK1 INT_EN_ACK2 INT_EN_ACK3 INT_EN_ACK4 INT_EN_ACK5 INT_EN_ACK6

UPDATE_DGO_GP1 : Writing HIGH to this bit field indicates corresponding DGO_GP1 register has been updated with new values.
bits : 0 - 0 (1 bit)
access : read-write

UPDATE_DGO_GP2 : Writing HIGH to this bit field indicates corresponding DGO_GP2 register has been updated with new values.
bits : 1 - 1 (1 bit)
access : read-write

UPDATE_DGO_GP3 : Writing HIGH to this bit field indicates corresponding DGO_GP3 register has been updated with new values.
bits : 2 - 2 (1 bit)
access : read-write

UPDATE_DGO_GP4 : Writing HIGH to this bit field indicates corresponding DGO_GP4 register has been updated with new values.
bits : 3 - 3 (1 bit)
access : read-write

UPDATE_DGO_GP5 : Writing HIGH to this bit field indicates corresponding DGO_GP5 register has been updated with new values.
bits : 4 - 4 (1 bit)
access : read-write

UPDATE_DGO_GP6 : Writing HIGH to this bit field indicates corresponding DGO_GP6 register has been updated with new values.
bits : 5 - 5 (1 bit)
access : read-write

WR_ACK_DGO_GP1 : This bit field is set automatically when corresponding DGO_GP1 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 13 - 13 (1 bit)
access : read-write

WR_ACK_DGO_GP2 : This bit field is set automatically when corresponding DGO_GP2 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 14 - 14 (1 bit)
access : read-write

WR_ACK_DGO_GP3 : This bit field is set automatically when corresponding DGO_GP3 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 15 - 15 (1 bit)
access : read-write

WR_ACK_DGO_GP4 : This bit field is set automatically when corresponding DGO_GP4 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 16 - 16 (1 bit)
access : read-write

WR_ACK_DGO_GP5 : This bit field is set automatically when corresponding DGO_GP5 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 17 - 17 (1 bit)
access : read-write

WR_ACK_DGO_GP6 : This bit field is set automatically when corresponding DGO_GP6 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 18 - 18 (1 bit)
access : read-write

INT_EN_ACK1 : Interrupt enable for WR_ACK_DGO_GP1 bit field.
bits : 26 - 26 (1 bit)
access : read-write

INT_EN_ACK2 : Interrupt enable for WR_ACK_DGO_GP2 bit field.
bits : 27 - 27 (1 bit)
access : read-write

INT_EN_ACK3 : Interrupt enable for WR_ACK_DGO_GP3 bit field.
bits : 28 - 28 (1 bit)
access : read-write

INT_EN_ACK4 : Interrupt enable for WR_ACK_DGO_GP4 bit field.
bits : 29 - 29 (1 bit)
access : read-write

INT_EN_ACK5 : Interrupt enable for WR_ACK_DGO_GP5 bit field.
bits : 30 - 30 (1 bit)
access : read-write

INT_EN_ACK6 : Interrupt enable for WR_ACK_DGO_GP6 bit field.
bits : 31 - 31 (1 bit)
access : read-write


DGO_CTRL1

SIM DGO Control Register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_CTRL1 DGO_CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDATE_DGO_GP7 UPDATE_DGO_GP8 UPDATE_DGO_GP9 UPDATE_DGO_GP10 UPDATE_DGO_GP11 WR_ACK_DGO_GP7 WR_ACK_DGO_GP8 WR_ACK_DGO_GP9 WR_ACK_DGO_GP10 WR_ACK_DGO_GP11 INT_EN_ACK7 INT_EN_ACK8 INT_EN_ACK9 INT_EN_ACK10 INT_EN_ACK11

UPDATE_DGO_GP7 : Writing HIGH to this bit field indicates corresponding DGO_GP7 register has been updated with new values.
bits : 0 - 0 (1 bit)
access : read-write

UPDATE_DGO_GP8 : Writing HIGH to this bit field indicates corresponding DGO_GP8 register has been updated with new values.
bits : 1 - 1 (1 bit)
access : read-write

UPDATE_DGO_GP9 : Writing HIGH to this bit field indicates corresponding DGO_GP9 register has been updated with new values.
bits : 2 - 2 (1 bit)
access : read-write

UPDATE_DGO_GP10 : Writing HIGH to this bit field indicates corresponding DGO_GP10 register has been updated with new values.
bits : 3 - 3 (1 bit)
access : read-write

UPDATE_DGO_GP11 : Writing HIGH to this bit field indicates corresponding DGO_GP11 register has been updated with new values.
bits : 4 - 4 (1 bit)
access : read-write

WR_ACK_DGO_GP7 : This bit field is set automatically when corresponding DGO_GP7 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 13 - 13 (1 bit)
access : read-write

WR_ACK_DGO_GP8 : This bit field is set automatically when corresponding DGO_GP8 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 14 - 14 (1 bit)
access : read-write

WR_ACK_DGO_GP9 : This bit field is set automatically when corresponding DGO_GP9 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 15 - 15 (1 bit)
access : read-write

WR_ACK_DGO_GP10 : This bit field is set automatically when corresponding DGO_GP10 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 16 - 16 (1 bit)
access : read-write

WR_ACK_DGO_GP11 : This bit field is set automatically when corresponding DGO_GP11 register is shadowed in DGO domain. SW needs to write "1" to clear.
bits : 17 - 17 (1 bit)
access : read-write

INT_EN_ACK7 : Interrupt enable for WR_ACK_DGO_GP7 bit field.
bits : 27 - 27 (1 bit)
access : read-write

INT_EN_ACK8 : Interrupt enable for WR_ACK_DGO_GP8 bit field.
bits : 28 - 28 (1 bit)
access : read-write

INT_EN_ACK9 : Interrupt enable for WR_ACK_DGO_GP9 bit field.
bits : 29 - 29 (1 bit)
access : read-write

INT_EN_ACK10 : Interrupt enable for WR_ACK_DGO_GP10 bit field.
bits : 30 - 30 (1 bit)
access : read-write

INT_EN_ACK11 : Interrupt enable for WR_ACK_DGO_GP11 bit field.
bits : 31 - 31 (1 bit)
access : read-write


DGO_GP1

SIM DGO General Purpose Register 1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP1 DGO_GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP1

SIM_DGO_GP1 : SIM DGO General purpose register 1. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP2

SIM DGO general Purpose Register 2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP2 DGO_GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP2

SIM_DGO_GP2 : SIM DGO General purpose register 2. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP3

SIM DGO General Purpose Register 3
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP3 DGO_GP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP3

SIM_DGO_GP3 : SIM DGO General purpose register 3. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP4

SIM DGO General Purpose Register 4
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP4 DGO_GP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP4

SIM_DGO_GP4 : SIM DGO General purpose register 4. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP5

SIM DGO General Purpose Register 5
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP5 DGO_GP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP5

SIM_DGO_GP5 : SIM DGO General purpose register 5. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP6

SIM DGO General Purpose Register 6
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP6 DGO_GP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP6

SIM_DGO_GP6 : SIM DGO General purpose register 6. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP7

SIM DGO General Purpose Register 7
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP7 DGO_GP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP7

SIM_DGO_GP7 : SIM DGO General purpose register 7. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP8

SIM DGO General Purpose Register 8
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP8 DGO_GP8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP8

SIM_DGO_GP8 : SIM DGO General purpose register 8. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP9

SIM DGO General Purpose Register 9
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP9 DGO_GP9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP9

SIM_DGO_GP9 : SIM DGO General purpose register 9. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP10

SIM DGO General Purpose Register 10
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP10 DGO_GP10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_DGO_GP10

SIM_DGO_GP10 : SIM DGO General purpose register 10. Contents are retained between power cycles
bits : 0 - 31 (32 bit)
access : read-write


DGO_GP11

SIM DGO General Purpose Register 11
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGO_GP11 DGO_GP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_SPIDEN_SPNIDEN SIM_DGO_GP11_1 PTA_RANGE_CTRL PTB_RANGE_CTRL PTC_RANGE_CTRL PTE_RANGE_CTRL PTF_RANGE_CTRL SIM_DGO_GP11_2

DBG_SPIDEN_SPNIDEN : Debug secured access enable.
bits : 0 - 0 (1 bit)
access : read-write

SIM_DGO_GP11_1 : Reserved bit field.
bits : 1 - 15 (15 bit)
access : read-write

PTA_RANGE_CTRL : PTA Range Control.
bits : 16 - 17 (2 bit)
access : read-write

PTB_RANGE_CTRL : PTB Range Control.
bits : 18 - 19 (2 bit)
access : read-write

PTC_RANGE_CTRL : PTC Range Control.
bits : 20 - 21 (2 bit)
access : read-write

PTE_RANGE_CTRL : PTE Range Control.
bits : 22 - 23 (2 bit)
access : read-write

PTF_RANGE_CTRL : PTF Range Control.
bits : 24 - 25 (2 bit)
access : read-write

SIM_DGO_GP11_2 : Reserved bit field.
bits : 26 - 29 (4 bit)
access : read-write


WKPU_WAKEUP_EN

WKPU Wake-up Enable
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKPU_WAKEUP_EN WKPU_WAKEUP_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKPU_CH_WAKEUP_EN

WKPU_CH_WAKEUP_EN : Bit used to disable wake-up events through this channel. Each channel may have one or multiple wake-up sources associated to it.
bits : 0 - 31 (32 bit)
access : read-write


JTAG_ID_REG

Mirror of JTAG ID Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JTAG_ID_REG JTAG_ID_REG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JTAG_INIT_BIT COMPANY_IDCODE PIN_PLUG DESIGN_CENTER_IDCODE PRN_PLUG

JTAG_INIT_BIT : JTAG ID initial bit.
bits : 0 - 0 (1 bit)
access : read-only

COMPANY_IDCODE : Company ID Code.
bits : 1 - 11 (11 bit)
access : read-only

PIN_PLUG : Part Identification Number.
bits : 12 - 21 (10 bit)
access : read-only

DESIGN_CENTER_IDCODE : Design Center ID Code.
bits : 22 - 27 (6 bit)
access : read-only

PRN_PLUG : Part Revision Number.
bits : 28 - 31 (4 bit)
access : read-only


A7_TSTMR_CMP_VAL_L

Lower A7 TS Timer compare value
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

A7_TSTMR_CMP_VAL_L A7_TSTMR_CMP_VAL_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A7_TSTMR_CMP_VAL_L

A7_TSTMR_CMP_VAL_L : Lower A7 TS Timer compare value.
bits : 0 - 31 (32 bit)
access : read-write


A7_TSTMR_CMP_VAL_H

Upper A7 TS Timer compare value
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

A7_TSTMR_CMP_VAL_H A7_TSTMR_CMP_VAL_H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A7_TSTMR_CMP_VAL_H

A7_TSTMR_CMP_VAL_H : Upper A7 TS Timer compare value.
bits : 0 - 31 (32 bit)
access : read-write


COMP_CELL_OVERRIDE

Override Control for Compensation Codes
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP_CELL_OVERRIDE COMP_CELL_OVERRIDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RASRCN RASRCP READ_MODE FASTFREEZE FREEZE NASRCN NASRCP COMPOK

RASRCN : 4-bit NMOS compensation codes.
bits : 0 - 3 (4 bit)
access : read-write

RASRCP : 4-bit PMOS compensation codes.
bits : 4 - 7 (4 bit)
access : read-write

READ_MODE : Read Mode.
bits : 8 - 8 (1 bit)
access : read-write

FASTFREEZE : Fast-Freeze.
bits : 9 - 9 (1 bit)
access : read-write

FREEZE : Freeze.
bits : 10 - 10 (1 bit)
access : read-write

NASRCN : 4-bit NMOS compensation measured/generated codes.
bits : 16 - 19 (4 bit)
access : read-only

NASRCP : 4-bit PMOS compensation measured/generated codes.
bits : 20 - 23 (4 bit)
access : read-only

COMPOK : Compensation OK.
bits : 24 - 24 (1 bit)
access : read-only


HSIC_CAL

HW SIM HSIC CAL Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSIC_CAL HSIC_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSIC_ZQ_VOH HSIC_ZQ_CAL_EN HSIC_ZQ_VOH_M1 HSIC_ZQ_VOL HSIC_ZQ_VOL_M1

HSIC_ZQ_VOH : HSIC ZQ pull-up resistence.
bits : 0 - 4 (5 bit)
access : read-write

HSIC_ZQ_CAL_EN : HSIC ZQ compare enable.
bits : 7 - 7 (1 bit)
access : read-write

HSIC_ZQ_VOH_M1 : HSIC ZQ pull-up resistence incremented.
bits : 8 - 12 (5 bit)
access : read-write

HSIC_ZQ_VOL : HSIC ZQ pull-down resistence.
bits : 16 - 20 (5 bit)
access : read-write

HSIC_ZQ_VOL_M1 : HSIC ZQ pull-down resistence incremented.
bits : 24 - 28 (5 bit)
access : read-write



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