\n

PCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xB8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PCC_TPIU

PCC_QSPI_OTFAD

PCC_TPM2

PCC_TPM3

PCC_SAI1

PCC_LPUART2

PCC_LPUART3

PCC_ADC1


PCC_TPIU

PCC TPIU Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPIU PCC_TPIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_QSPI_OTFAD

PCC QSPI_OTFAD Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_QSPI_OTFAD PCC_QSPI_OTFAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TPM2

PCC TPM2 Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM2 PCC_TPM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TPM3

PCC TPM3 Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM3 PCC_TPM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_SAI1

PCC SAI1 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_SAI1 PCC_SAI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 15 (16 bit)
access : read-write

FRAC : Peripheral Clock Divider Fraction
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART2

PCC LPUART2 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART2 PCC_LPUART2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART3

PCC LPUART3 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART3 PCC_LPUART3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_ADC1

PCC ADC1 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_ADC1 PCC_ADC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.