Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xD0 byte (0x0)
mem_usage : registers
protection : not protected
DMA System Address
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DS_ADDR : DS_ADDR
bits : 0 - 31 (32 bit)
access : read-write
Command Response0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRSP0 : Command Response 0
bits : 0 - 31 (32 bit)
access : read-only
Command Response1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRSP1 : Command Response 1
bits : 0 - 31 (32 bit)
access : read-only
Command Response2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRSP2 : Command Response 2
bits : 0 - 31 (32 bit)
access : read-only
Command Response3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRSP3 : Command Response 3
bits : 0 - 31 (32 bit)
access : read-only
Data Buffer Access Port
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATCONT : Data Content
bits : 0 - 31 (32 bit)
access : read-write
Present State
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIHB : Command Inhibit (CMD)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : CIHB_0
Can issue command using only CMD line
0x1 : CIHB_1
Cannot issue command
End of enumeration elements list.
CDIHB : Command Inhibit (DATA)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CDIHB_0
Can issue command which uses the DATA line
0x1 : CDIHB_1
Cannot issue command which uses the DATA line
End of enumeration elements list.
DLA : Data Line Active
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : DLA_0
DATA Line Inactive
0x1 : DLA_1
DATA Line Active
End of enumeration elements list.
SDSTB : SD Clock Stable
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SDSTB_0
Clock is changing frequency and not stable.
0x1 : SDSTB_1
Clock is stable.
End of enumeration elements list.
IPGOFF : IPG_CLK Gated Off Internally
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : IPGOFF_0
IPG_CLK is active.
0x1 : IPGOFF_1
IPG_CLK is gated off.
End of enumeration elements list.
HCKOFF : HCLK Gated Off Internally
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : HCKOFF_0
HCLK is active.
0x1 : HCKOFF_1
HCLK is gated off.
End of enumeration elements list.
PEROFF : IPG_PERCLK Gated Off Internally
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : PEROFF_0
IPG_PERCLK is active.
0x1 : PEROFF_1
IPG_PERCLK is gated off.
End of enumeration elements list.
SDOFF : SD Clock Gated Off Internally
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : SDOFF_0
SD Clock is active.
0x1 : SDOFF_1
SD Clock is gated off.
End of enumeration elements list.
WTA : Write Transfer Active
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : WTA_0
No valid data
0x1 : WTA_1
Transferring data
End of enumeration elements list.
RTA : Read Transfer Active
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : RTA_0
No valid data
0x1 : RTA_1
Transferring data
End of enumeration elements list.
BWEN : Buffer Write Enable
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : BWEN_0
Write disable
0x1 : BWEN_1
Write enable
End of enumeration elements list.
BREN : Buffer Read Enable
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : BREN_0
Read disable
0x1 : BREN_1
Read enable
End of enumeration elements list.
RTR : Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : RTR_0
Fixed or well tuned sampling clock
0x1 : RTR_1
Sampling clock needs re-tuning
End of enumeration elements list.
TSCD : Tape Select Change Done
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : TSCD_0
Delay cell select change is not finished.
0x1 : TSCD_1
Delay cell select change is finished.
End of enumeration elements list.
CINST : Card Inserted
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : CINST_0
Power on Reset or No Card
0x1 : CINST_1
Card Inserted
End of enumeration elements list.
CDPL : Card Detect Pin Level
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : CDPL_0
No card present (CD_B = 1)
0x1 : CDPL_1
Card present (CD_B = 0)
End of enumeration elements list.
WPSPL : Write Protect Switch Pin Level
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : WPSPL_0
Write protected (WP = 1)
0x1 : WPSPL_1
Write enabled (WP = 0)
End of enumeration elements list.
CLSL : CMD Line Signal Level
bits : 23 - 23 (1 bit)
access : read-only
DLSL : DATA[7:0] Line Signal Level
bits : 24 - 31 (8 bit)
access : read-only
Enumeration:
0 : DATA0
Data 0 line signal level
0x1 : DATA1
Data 1 line signal level
0x2 : DATA2
Data 2 line signal level
0x3 : DATA3
Data 3 line signal level
0x4 : DATA4
Data 4 line signal level
0x5 : DATA5
Data 5 line signal level
0x6 : DATA6
Data 6 line signal level
0x7 : DATA7
Data 7 line signal level
End of enumeration elements list.
Protocol Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCTL : LED Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LCTL_0
LED off
0x1 : LCTL_1
LED on
End of enumeration elements list.
DTW : Data Transfer Width
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : DTW_0
1-bit mode
0x1 : DTW_1
4-bit mode
0x2 : DTW_2
8-bit mode
End of enumeration elements list.
D3CD : DATA3 as Card Detection Pin
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D3CD_0
DATA3 does not monitor Card Insertion
0x1 : D3CD_1
DATA3 as Card Detection Pin
End of enumeration elements list.
EMODE : Endian Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : EMODE_0
Big Endian Mode
0x1 : EMODE_1
Half Word Big Endian Mode
0x2 : EMODE_2
Little Endian Mode
End of enumeration elements list.
CDTL : Card Detect Test Level
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CDTL_0
Card Detect Test Level is 0, no card inserted
0x1 : CDTL_1
Card Detect Test Level is 1, card inserted
End of enumeration elements list.
CDSS : Card Detect Signal Selection
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CDSS_0
Card Detection Level is selected (for normal purpose).
0x1 : CDSS_1
Card Detection Test Level is selected (for test purpose).
End of enumeration elements list.
DMASEL : DMA Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DMASEL_0
No DMA or Simple DMA is selected
0x1 : DMASEL_1
ADMA1 is selected
0x2 : DMASEL_2
ADMA2 is selected
End of enumeration elements list.
SABGREQ : Stop At Block Gap Request
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SABGREQ_0
Transfer
0x1 : SABGREQ_1
Stop
End of enumeration elements list.
CREQ : Continue Request
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CREQ_0
No effect
0x1 : CREQ_1
Restart
End of enumeration elements list.
RWCTL : Read Wait Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : RWCTL_0
Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
0x1 : RWCTL_1
Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
End of enumeration elements list.
IABG : Interrupt At Block Gap
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : IABG_0
Disabled
0x1 : IABG_1
Enabled
End of enumeration elements list.
RD_DONE_NO_8CLK : RD_DONE_NO_8CLK
bits : 20 - 20 (1 bit)
access : read-write
WECINT : Wakeup Event Enable On Card Interrupt
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : WECINT_0
Disable
0x1 : WECINT_1
Enable
End of enumeration elements list.
WECINS : Wakeup Event Enable On SD Card Insertion
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : WECINS_0
Disable
0x1 : WECINS_1
Enable
End of enumeration elements list.
WECRM : Wakeup Event Enable On SD Card Removal
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : WECRM_0
Disable
0x1 : WECRM_1
Enable
End of enumeration elements list.
BURST_LEN_EN : BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
#xx1 : BURST_LEN_EN_1
Burst length is enabled for INCR
End of enumeration elements list.
NON_EXACT_BLK_RD : NON_EXACT_BLK_RD
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NON_EXACT_BLK_RD_0
The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.
0x1 : NON_EXACT_BLK_RD_1
The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
End of enumeration elements list.
System Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVS : Divisor
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DVS_0
Divide-by-1
0x1 : DVS_1
Divide-by-2
0xE : DVS_14
Divide-by-15
0xF : DVS_15
Divide-by-16
End of enumeration elements list.
SDCLKFS : SDCLK Frequency Select
bits : 8 - 15 (8 bit)
access : read-write
DTOCV : Data Timeout Counter Value
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : DTOCV_0
no description available
0x1 : DTOCV_1
no description available
0xD : DTOCV_13
no description available
0xE : DTOCV_14
no description available
0xF : DTOCV_15
no description available
End of enumeration elements list.
IPP_RST_N : IPP_RST_N
bits : 23 - 23 (1 bit)
access : read-write
RSTA : Software Reset For ALL
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : RSTA_0
No Reset
0x1 : RSTA_1
Reset
End of enumeration elements list.
RSTC : Software Reset For CMD Line
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : RSTC_0
No Reset
0x1 : RSTC_1
Reset
End of enumeration elements list.
RSTD : Software Reset For DATA Line
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : RSTD_0
No Reset
0x1 : RSTD_1
Reset
End of enumeration elements list.
INITA : Initialization Active
bits : 27 - 27 (1 bit)
access : read-write
RSTT : Reset Tuning
bits : 28 - 28 (1 bit)
access : read-write
Interrupt Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Command Complete
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CC_0
Command not complete
0x1 : CC_1
Command complete
End of enumeration elements list.
TC : Transfer Complete
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TC_0
Transfer not complete
0x1 : TC_1
Transfer complete
End of enumeration elements list.
BGE : Block Gap Event
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : BGE_0
No block gap event
0x1 : BGE_1
Transaction stopped at block gap
End of enumeration elements list.
DINT : DMA Interrupt
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DINT_0
No DMA Interrupt
0x1 : DINT_1
DMA Interrupt is generated
End of enumeration elements list.
BWR : Buffer Write Ready
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BWR_0
Not ready to write buffer
0x1 : BWR_1
Ready to write buffer:
End of enumeration elements list.
BRR : Buffer Read Ready
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BRR_0
Not ready to read buffer
0x1 : BRR_1
Ready to read buffer
End of enumeration elements list.
CINS : Card Insertion
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CINS_0
Card state unstable or removed
0x1 : CINS_1
Card inserted
End of enumeration elements list.
CRM : Card Removal
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CRM_0
Card state unstable or inserted
0x1 : CRM_1
Card removed
End of enumeration elements list.
CINT : Card Interrupt
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CINT_0
No Card Interrupt
0x1 : CINT_1
Generate Card Interrupt
End of enumeration elements list.
RTE : Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : RTE_0
Re-Tuning is not required
0x1 : RTE_1
Re-Tuning should be performed
End of enumeration elements list.
TP : Tuning Pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
bits : 14 - 14 (1 bit)
access : read-write
CTOE : Command Timeout Error
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : CTOE_0
No Error
0x1 : CTOE_1
Time out
End of enumeration elements list.
CCE : Command CRC Error
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CCE_0
No Error
0x1 : CCE_1
CRC Error Generated.
End of enumeration elements list.
CEBE : Command End Bit Error
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : CEBE_0
No Error
0x1 : CEBE_1
End Bit Error Generated
End of enumeration elements list.
CIE : Command Index Error
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : CIE_0
No Error
0x1 : CIE_1
Error
End of enumeration elements list.
DTOE : Data Timeout Error
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DTOE_0
No Error
0x1 : DTOE_1
Time out
End of enumeration elements list.
DCE : Data CRC Error
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DCE_0
No Error
0x1 : DCE_1
Error
End of enumeration elements list.
DEBE : Data End Bit Error
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DEBE_0
No Error
0x1 : DEBE_1
Error
End of enumeration elements list.
AC12E : Auto CMD12 Error
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : AC12E_0
No Error
0x1 : AC12E_1
Error
End of enumeration elements list.
TNE : Tuning Error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
bits : 26 - 26 (1 bit)
access : read-write
DMAE : DMA Error
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DMAE_0
No Error
0x1 : DMAE_1
Error
End of enumeration elements list.
Interrupt Status Enable
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCSEN : Command Complete Status Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CCSEN_0
Masked
0x1 : CCSEN_1
Enabled
End of enumeration elements list.
TCSEN : Transfer Complete Status Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TCSEN_0
Masked
0x1 : TCSEN_1
Enabled
End of enumeration elements list.
BGESEN : Block Gap Event Status Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : BGESEN_0
Masked
0x1 : BGESEN_1
Enabled
End of enumeration elements list.
DINTSEN : DMA Interrupt Status Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DINTSEN_0
Masked
0x1 : DINTSEN_1
Enabled
End of enumeration elements list.
BWRSEN : Buffer Write Ready Status Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BWRSEN_0
Masked
0x1 : BWRSEN_1
Enabled
End of enumeration elements list.
BRRSEN : Buffer Read Ready Status Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BRRSEN_0
Masked
0x1 : BRRSEN_1
Enabled
End of enumeration elements list.
CINSSEN : Card Insertion Status Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CINSSEN_0
Masked
0x1 : CINSSEN_1
Enabled
End of enumeration elements list.
CRMSEN : Card Removal Status Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CRMSEN_0
Masked
0x1 : CRMSEN_1
Enabled
End of enumeration elements list.
CINTSEN : Card Interrupt Status Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CINTSEN_0
Masked
0x1 : CINTSEN_1
Enabled
End of enumeration elements list.
RTESEN : Re-Tuning Event Status Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : RTESEN_0
Masked
0x1 : RTESEN_1
Enabled
End of enumeration elements list.
TPSEN : Tuning Pass Status Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : TPSEN_0
Masked
0x1 : TPSEN_1
Enabled
End of enumeration elements list.
CTOESEN : Command Timeout Error Status Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : CTOESEN_0
Masked
0x1 : CTOESEN_1
Enabled
End of enumeration elements list.
CCESEN : Command CRC Error Status Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CCESEN_0
Masked
0x1 : CCESEN_1
Enabled
End of enumeration elements list.
CEBESEN : Command End Bit Error Status Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : CEBESEN_0
Masked
0x1 : CEBESEN_1
Enabled
End of enumeration elements list.
CIESEN : Command Index Error Status Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : CIESEN_0
Masked
0x1 : CIESEN_1
Enabled
End of enumeration elements list.
DTOESEN : Data Timeout Error Status Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DTOESEN_0
Masked
0x1 : DTOESEN_1
Enabled
End of enumeration elements list.
DCESEN : Data CRC Error Status Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DCESEN_0
Masked
0x1 : DCESEN_1
Enabled
End of enumeration elements list.
DEBESEN : Data End Bit Error Status Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DEBESEN_0
Masked
0x1 : DEBESEN_1
Enabled
End of enumeration elements list.
AC12ESEN : Auto CMD12 Error Status Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : AC12ESEN_0
Masked
0x1 : AC12ESEN_1
Enabled
End of enumeration elements list.
TNESEN : Tuning Error Status Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TNESEN_0
Masked
0x1 : TNESEN_1
Enabled
End of enumeration elements list.
DMAESEN : DMA Error Status Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DMAESEN_0
Masked
0x1 : DMAESEN_1
Enabled
End of enumeration elements list.
Interrupt Signal Enable
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCIEN : Command Complete Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CCIEN_0
Masked
0x1 : CCIEN_1
Enabled
End of enumeration elements list.
TCIEN : Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TCIEN_0
Masked
0x1 : TCIEN_1
Enabled
End of enumeration elements list.
BGEIEN : Block Gap Event Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : BGEIEN_0
Masked
0x1 : BGEIEN_1
Enabled
End of enumeration elements list.
DINTIEN : DMA Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DINTIEN_0
Masked
0x1 : DINTIEN_1
Enabled
End of enumeration elements list.
BWRIEN : Buffer Write Ready Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BWRIEN_0
Masked
0x1 : BWRIEN_1
Enabled
End of enumeration elements list.
BRRIEN : Buffer Read Ready Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BRRIEN_0
Masked
0x1 : BRRIEN_1
Enabled
End of enumeration elements list.
CINSIEN : Card Insertion Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CINSIEN_0
Masked
0x1 : CINSIEN_1
Enabled
End of enumeration elements list.
CRMIEN : Card Removal Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CRMIEN_0
Masked
0x1 : CRMIEN_1
Enabled
End of enumeration elements list.
CINTIEN : Card Interrupt Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CINTIEN_0
Masked
0x1 : CINTIEN_1
Enabled
End of enumeration elements list.
RTEIEN : Re-Tuning Event Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : RTEIEN_0
Masked
0x1 : RTEIEN_1
Enabled
End of enumeration elements list.
TPIEN : Tuning Pass Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : TPIEN_0
Masked
0x1 : TPIEN_1
Enabled
End of enumeration elements list.
CTOEIEN : Command Timeout Error Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : CTOEIEN_0
Masked
0x1 : CTOEIEN_1
Enabled
End of enumeration elements list.
CCEIEN : Command CRC Error Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CCEIEN_0
Masked
0x1 : CCEIEN_1
Enabled
End of enumeration elements list.
CEBEIEN : Command End Bit Error Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : CEBEIEN_0
Masked
0x1 : CEBEIEN_1
Enabled
End of enumeration elements list.
CIEIEN : Command Index Error Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : CIEIEN_0
Masked
0x1 : CIEIEN_1
Enabled
End of enumeration elements list.
DTOEIEN : Data Timeout Error Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DTOEIEN_0
Masked
0x1 : DTOEIEN_1
Enabled
End of enumeration elements list.
DCEIEN : Data CRC Error Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DCEIEN_0
Masked
0x1 : DCEIEN_1
Enabled
End of enumeration elements list.
DEBEIEN : Data End Bit Error Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DEBEIEN_0
Masked
0x1 : DEBEIEN_1
Enabled
End of enumeration elements list.
AC12EIEN : Auto CMD12 Error Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : AC12EIEN_0
Masked
0x1 : AC12EIEN_1
Enabled
End of enumeration elements list.
TNEIEN : Tuning Error Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TNEIEN_0
Masked
0x1 : TNEIEN_1
Enabled
End of enumeration elements list.
DMAEIEN : DMA Error Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DMAEIEN_0
Masked
0x1 : DMAEIEN_1
Enable
End of enumeration elements list.
Auto CMD12 Error Status
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AC12NE : Auto CMD12 Not Executed
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : AC12NE_0
Executed
0x1 : AC12NE_1
Not executed
End of enumeration elements list.
AC12TOE : Auto CMD12 / 23 Timeout Error
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : AC12TOE_0
No error
0x1 : AC12TOE_1
Time out
End of enumeration elements list.
AC12EBE : Auto CMD12 / 23 End Bit Error
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : AC12EBE_0
No error
0x1 : AC12EBE_1
End Bit Error Generated
End of enumeration elements list.
AC12CE : Auto CMD12 / 23 CRC Error
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : AC12CE_0
No CRC error
0x1 : AC12CE_1
CRC Error Met in Auto CMD12/23 Response
End of enumeration elements list.
AC12IE : Auto CMD12 / 23 Index Error
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : AC12IE_0
No error
0x1 : AC12IE_1
Error, the CMD index in response is not CMD12/23
End of enumeration elements list.
CNIBAC12E : Command Not Issued By Auto CMD12 Error
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : CNIBAC12E_0
No error
0x1 : CNIBAC12E_1
Not Issued
End of enumeration elements list.
EXECUTE_TUNING : Execute Tuning
bits : 22 - 22 (1 bit)
access : read-write
SMP_CLK_SEL : Sample Clock Select
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SMP_CLK_SEL_0
Fixed clock is used to sample data
0x1 : SMP_CLK_SEL_1
Tuned clock is used to sample data
End of enumeration elements list.
Block Attributes
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKSIZE : Block Size
bits : 0 - 12 (13 bit)
access : read-write
Enumeration:
0 : BLKSIZE_0
No data transfer
0x1 : BLKSIZE_1
1 Byte
0x2 : BLKSIZE_2
2 Bytes
0x3 : BLKSIZE_3
3 Bytes
0x4 : BLKSIZE_4
4 Bytes
0x1FF : BLKSIZE_511
511 Bytes
0x200 : BLKSIZE_512
512 Bytes
0x800 : BLKSIZE_2048
2048 Bytes
0x1000 : BLKSIZE_4096
4096 Bytes
End of enumeration elements list.
BLKCNT : Block Count
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : BLKCNT_0
Stop Count
0x1 : BLKCNT_1
1 block
0x2 : BLKCNT_2
2 blocks
0xFFFF : BLKCNT_65535
65535 blocks
End of enumeration elements list.
Host Controller Capabilities
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDR50_SUPPORT : SDR50 support
bits : 0 - 0 (1 bit)
access : read-only
SDR104_SUPPORT : SDR104 support
bits : 1 - 1 (1 bit)
access : read-only
DDR50_SUPPORT : DDR50 support
bits : 2 - 2 (1 bit)
access : read-only
TIME_COUNT_RETUNING : Time Counter for Retuning
bits : 8 - 11 (4 bit)
access : read-write
USE_TUNING_SDR50 : Use Tuning for SDR50
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : USE_TUNING_SDR50_0
SDR does not require tuning
0x1 : USE_TUNING_SDR50_1
SDR50 requires tuning
End of enumeration elements list.
RETUNING_MODE : Retuning Mode
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0 : RETUNING_MODE_0
Mode 1
0x1 : RETUNING_MODE_1
Mode 2
0x2 : RETUNING_MODE_2
Mode 3
End of enumeration elements list.
MBL : Max Block Length
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0 : MBL_0
512 bytes
0x1 : MBL_1
1024 bytes
0x2 : MBL_2
2048 bytes
0x3 : MBL_3
4096 bytes
End of enumeration elements list.
ADMAS : ADMA Support
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : ADMAS_0
Advanced DMA Not supported
0x1 : ADMAS_1
Advanced DMA Supported
End of enumeration elements list.
HSS : High Speed Support
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : HSS_0
High Speed Not Supported
0x1 : HSS_1
High Speed Supported
End of enumeration elements list.
DMAS : DMA Support
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : DMAS_0
DMA not supported
0x1 : DMAS_1
DMA Supported
End of enumeration elements list.
SRS : Suspend / Resume Support
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : SRS_0
Not supported
0x1 : SRS_1
Supported
End of enumeration elements list.
VS33 : Voltage Support 3.3V
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : VS33_0
3.3V not supported
0x1 : VS33_1
3.3V supported
End of enumeration elements list.
VS30 : Voltage Support 3.0 V
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : VS30_0
3.0V not supported
0x1 : VS30_1
3.0V supported
End of enumeration elements list.
VS18 : Voltage Support 1.8 V
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : VS18_0
1.8V not supported
0x1 : VS18_1
1.8V supported
End of enumeration elements list.
Watermark Level
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_WML : Read Watermark Level
bits : 0 - 7 (8 bit)
access : read-write
RD_BRST_LEN : Read Burst Length Due to system restriction, the actual burst length may not exceed 16.
bits : 8 - 12 (5 bit)
access : read-write
WR_WML : Write Watermark Level
bits : 16 - 23 (8 bit)
access : read-write
WR_BRST_LEN : Write Burst Length Due to system restriction, the actual burst length may not exceed 16.
bits : 24 - 28 (5 bit)
access : read-write
Mixer Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DMAEN_0
Disable
0x1 : DMAEN_1
Enable
End of enumeration elements list.
BCEN : Block Count Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : BCEN_0
Disable
0x1 : BCEN_1
Enable
End of enumeration elements list.
AC12EN : Auto CMD12 Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : AC12EN_0
Disable
0x1 : AC12EN_1
Enable
End of enumeration elements list.
DDR_EN : Dual Data Rate mode selection
bits : 3 - 3 (1 bit)
access : read-write
DTDSEL : Data Transfer Direction Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DTDSEL_0
Write (Host to Card)
0x1 : DTDSEL_1
Read (Card to Host)
End of enumeration elements list.
MSBSEL : Multi / Single Block Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MSBSEL_0
Single Block
0x1 : MSBSEL_1
Multiple Blocks
End of enumeration elements list.
NIBBLE_POS : NIBBLE_POS
bits : 6 - 6 (1 bit)
access : read-write
AC23EN : Auto CMD23 Enable
bits : 7 - 7 (1 bit)
access : read-write
EXE_TUNE : Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : EXE_TUNE_0
Not Tuned or Tuning Completed
0x1 : EXE_TUNE_1
Execute Tuning
End of enumeration elements list.
SMP_CLK_SEL : SMP_CLK_SEL
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SMP_CLK_SEL_0
Fixed clock is used to sample data / cmd
0x1 : SMP_CLK_SEL_1
Tuned clock is used to sample data / cmd
End of enumeration elements list.
AUTO_TUNE_EN : Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : AUTO_TUNE_EN_0
Disable auto tuning
0x1 : AUTO_TUNE_EN_1
Enable auto tuning
End of enumeration elements list.
FBCLK_SEL : Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : FBCLK_SEL_0
Feedback clock comes from the loopback CLK
0x1 : FBCLK_SEL_1
Feedback clock comes from the ipp_card_clk_out
End of enumeration elements list.
HS400_MODE : Enable HS400 Mode
bits : 26 - 26 (1 bit)
access : read-write
Force Event
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEVTAC12NE : Force Event Auto Command 12 Not Executed
bits : 0 - 0 (1 bit)
access : write-only
FEVTAC12TOE : Force Event Auto Command 12 Time Out Error
bits : 1 - 1 (1 bit)
access : write-only
FEVTAC12CE : Force Event Auto Command 12 CRC Error
bits : 2 - 2 (1 bit)
access : write-only
FEVTAC12EBE : Force Event Auto Command 12 End Bit Error
bits : 3 - 3 (1 bit)
access : write-only
FEVTAC12IE : Force Event Auto Command 12 Index Error
bits : 4 - 4 (1 bit)
access : write-only
FEVTCNIBAC12E : Force Event Command Not Executed By Auto Command 12 Error
bits : 7 - 7 (1 bit)
access : write-only
FEVTCTOE : Force Event Command Time Out Error
bits : 16 - 16 (1 bit)
access : write-only
FEVTCCE : Force Event Command CRC Error
bits : 17 - 17 (1 bit)
access : write-only
FEVTCEBE : Force Event Command End Bit Error
bits : 18 - 18 (1 bit)
access : write-only
FEVTCIE : Force Event Command Index Error
bits : 19 - 19 (1 bit)
access : write-only
FEVTDTOE : Force Event Data Time Out Error
bits : 20 - 20 (1 bit)
access : write-only
FEVTDCE : Force Event Data CRC Error
bits : 21 - 21 (1 bit)
access : write-only
FEVTDEBE : Force Event Data End Bit Error
bits : 22 - 22 (1 bit)
access : write-only
FEVTAC12E : Force Event Auto Command 12 Error
bits : 24 - 24 (1 bit)
access : write-only
FEVTTNE : Force Tuning Error
bits : 26 - 26 (1 bit)
access : write-only
FEVTDMAE : Force Event DMA Error
bits : 28 - 28 (1 bit)
access : write-only
FEVTCINT : Force Event Card Interrupt
bits : 31 - 31 (1 bit)
access : write-only
ADMA Error Status Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADMAES : ADMA Error State (when ADMA Error is occurred)
bits : 0 - 1 (2 bit)
access : read-only
ADMALME : ADMA Length Mismatch Error
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : ADMALME_0
No Error
0x1 : ADMALME_1
Error
End of enumeration elements list.
ADMADCE : ADMA Descriptor Error
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : ADMADCE_0
No Error
0x1 : ADMADCE_1
Error
End of enumeration elements list.
ADMA System Address
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADS_ADDR : ADMA System Address
bits : 2 - 31 (30 bit)
access : read-write
DLL (Delay Line) Control
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLL_CTRL_ENABLE : DLL_CTRL_ENABLE
bits : 0 - 0 (1 bit)
access : read-write
DLL_CTRL_RESET : DLL_CTRL_RESET
bits : 1 - 1 (1 bit)
access : read-write
DLL_CTRL_SLV_FORCE_UPD : DLL_CTRL_SLV_FORCE_UPD
bits : 2 - 2 (1 bit)
access : read-write
DLL_CTRL_SLV_DLY_TARGET0 : DLL_CTRL_SLV_DLY_TARGET0
bits : 3 - 6 (4 bit)
access : read-write
DLL_CTRL_GATE_UPDATE : DLL_CTRL_GATE_UPDATE
bits : 7 - 7 (1 bit)
access : read-write
DLL_CTRL_SLV_OVERRIDE : DLL_CTRL_SLV_OVERRIDE
bits : 8 - 8 (1 bit)
access : read-write
DLL_CTRL_SLV_OVERRIDE_VAL : DLL_CTRL_SLV_OVERRIDE_VAL
bits : 9 - 15 (7 bit)
access : read-write
DLL_CTRL_SLV_DLY_TARGET1 : DLL_CTRL_SLV_DLY_TARGET1
bits : 16 - 18 (3 bit)
access : read-write
DLL_CTRL_SLV_UPDATE_INT : DLL_CTRL_SLV_UPDATE_INT
bits : 20 - 27 (8 bit)
access : read-write
DLL_CTRL_REF_UPDATE_INT : DLL_CTRL_REF_UPDATE_INT
bits : 28 - 31 (4 bit)
access : read-write
DLL Status
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DLL_STS_SLV_LOCK : DLL_STS_SLV_LOCK
bits : 0 - 0 (1 bit)
access : read-only
DLL_STS_REF_LOCK : DLL_STS_REF_LOCK
bits : 1 - 1 (1 bit)
access : read-only
DLL_STS_SLV_SEL : DLL_STS_SLV_SEL
bits : 2 - 8 (7 bit)
access : read-only
DLL_STS_REF_SEL : DLL_STS_REF_SEL
bits : 9 - 15 (7 bit)
access : read-only
CLK Tuning Control and Status
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY_CELL_SET_POST : DLY_CELL_SET_POST
bits : 0 - 3 (4 bit)
access : read-write
DLY_CELL_SET_OUT : DLY_CELL_SET_OUT
bits : 4 - 7 (4 bit)
access : read-write
DLY_CELL_SET_PRE : DLY_CELL_SET_PRE
bits : 8 - 14 (7 bit)
access : read-write
NXT_ERR : NXT_ERR
bits : 15 - 15 (1 bit)
access : read-only
TAP_SEL_POST : TAP_SEL_POST
bits : 16 - 19 (4 bit)
access : read-only
TAP_SEL_OUT : TAP_SEL_OUT
bits : 20 - 23 (4 bit)
access : read-only
TAP_SEL_PRE : TAP_SEL_PRE
bits : 24 - 30 (7 bit)
access : read-only
PRE_ERR : PRE_ERR
bits : 31 - 31 (1 bit)
access : read-only
Strobe DLL Control
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STROBE_DLL_CTRL_ENABLE : Strobe DLL Control Enable
bits : 0 - 0 (1 bit)
access : read-write
STROBE_DLL_CTRL_RESET : Strobe DLL Control Reset
bits : 1 - 1 (1 bit)
access : read-write
STROBE_DLL_CTRL_SLV_FORCE_UPD : Strobe DLL Control Slave Force Updated
bits : 2 - 2 (1 bit)
access : read-write
STROBE_DLL_CTRL_SLV_DLY_TARGET : Strobe DLL Control Slave Delay Target
bits : 3 - 5 (3 bit)
access : read-write
STROBE_DLL_CTRL_GATE_UPDATE_0 : Strobe DLL Control Gate Update
bits : 6 - 6 (1 bit)
access : read-write
STROBE_DLL_CTRL_GATE_UPDATE_1 : Strobe DLL Control Gate Update
bits : 7 - 7 (1 bit)
access : read-write
STROBE_DLL_CTRL_SLV_OVERRIDE : Strobe DLL Control Slave Override
bits : 8 - 8 (1 bit)
access : read-write
STROBE_DLL_CTRL_SLV_OVERRIDE_VAL : Strobe DLL Control Slave Override Value
bits : 9 - 15 (7 bit)
access : read-write
STROBE_DLL_CTRL_SLV_UPDATE_INT : Strobe DLL Control Slave Update Interval
bits : 20 - 27 (8 bit)
access : read-write
STROBE_DLL_CTRL_REF_UPDATE_INT : Strobe DLL Control Reference Update Interval
bits : 28 - 31 (4 bit)
access : read-write
Strobe DLL Status
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STROBE_DLL_STS_SLV_LOCK : Strobe DLL Status Slave Lock
bits : 0 - 0 (1 bit)
access : read-only
STROBE_DLL_STS_REF_LOCK : Strobe DLL Status Reference Lock
bits : 1 - 1 (1 bit)
access : read-only
STROBE_DLL_STS_SLV_SEL : Strobe DLL Status Slave Select
bits : 2 - 8 (7 bit)
access : read-only
STROBE_DLL_STS_REF_SEL : Strobe DLL Status Reference Select
bits : 9 - 15 (7 bit)
access : read-only
Command Argument
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDARG : Command Argument
bits : 0 - 31 (32 bit)
access : read-write
Command Transfer Type
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSPTYP : Response Type Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : RSPTYP_0
No Response
0x1 : RSPTYP_1
Response Length 136
0x2 : RSPTYP_2
Response Length 48
0x3 : RSPTYP_3
Response Length 48, check Busy after response
End of enumeration elements list.
CCCEN : Command CRC Check Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : CCCEN_0
Disable
0x1 : CCCEN_1
Enable
End of enumeration elements list.
CICEN : Command Index Check Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : CICEN_0
Disable
0x1 : CICEN_1
Enable
End of enumeration elements list.
DPSEL : Data Present Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DPSEL_0
No Data Present
0x1 : DPSEL_1
Data Present
End of enumeration elements list.
CMDTYP : Command Type
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : CMDTYP_0
Normal Other commands
0x1 : CMDTYP_1
Suspend CMD52 for writing Bus Suspend in CCCR
0x2 : CMDTYP_2
Resume CMD52 for writing Function Select in CCCR
0x3 : CMDTYP_3
Abort CMD12, CMD52 for writing I/O Abort in CCCR
End of enumeration elements list.
CMDINX : Command Index
bits : 24 - 29 (6 bit)
access : read-write
Vendor Specific Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSELECT : Voltage Selection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : VSELECT_0
Change the voltage to high voltage range, around 3.0 V
0x1 : VSELECT_1
Change the voltage to low voltage range, around 1.8 V
End of enumeration elements list.
CONFLICT_CHK_EN : Conflict check enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : CONFLICT_CHK_EN_0
Conflict check disable
0x1 : CONFLICT_CHK_EN_1
Conflict check enable
End of enumeration elements list.
AC12_WR_CHKBUSY_EN : AC12_WR_CHKBUSY_EN
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : AC12_WR_CHKBUSY_EN_0
Do not check busy after auto CMD12 for write data packet
0x1 : AC12_WR_CHKBUSY_EN_1
Check busy after auto CMD12 for write data packet
End of enumeration elements list.
FRC_SDCLK_ON : FRC_SDCLK_ON
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FRC_SDCLK_ON_0
CLK active or inactive is fully controlled by the hardware.
0x1 : FRC_SDCLK_ON_1
Force CLK active.
End of enumeration elements list.
CRC_CHK_DIS : CRC Check Disable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CRC_CHK_DIS_0
Check CRC16 for every read data packet and check CRC bits for every write data packet
0x1 : CRC_CHK_DIS_1
Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
End of enumeration elements list.
CMD_BYTE_EN : CMD_BYTE_EN
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : CMD_BYTE_EN_0
Disable
0x1 : CMD_BYTE_EN_1
Enable
End of enumeration elements list.
MMC Boot Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTOCV_ACK : DTOCV_ACK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DTOCV_ACK_0
SDCLK x 2^14
0x1 : DTOCV_ACK_1
SDCLK x 2^15
0x2 : DTOCV_ACK_2
SDCLK x 2^16
0x3 : DTOCV_ACK_3
SDCLK x 2^17
0x4 : DTOCV_ACK_4
SDCLK x 2^18
0x5 : DTOCV_ACK_5
SDCLK x 2^19
0x6 : DTOCV_ACK_6
SDCLK x 2^20
0x7 : DTOCV_ACK_7
SDCLK x 2^21
0xE : DTOCV_ACK_14
SDCLK x 2^28
0xF : DTOCV_ACK_15
SDCLK x 2^29
End of enumeration elements list.
BOOT_ACK : BOOT_ACK
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BOOT_ACK_0
No ack
0x1 : BOOT_ACK_1
Ack
End of enumeration elements list.
BOOT_MODE : BOOT_MODE
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BOOT_MODE_0
Normal boot
0x1 : BOOT_MODE_1
Alternative boot
End of enumeration elements list.
BOOT_EN : BOOT_EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : BOOT_EN_0
Fast boot disable
0x1 : BOOT_EN_1
Fast boot enable
End of enumeration elements list.
AUTO_SABG_EN : AUTO_SABG_EN
bits : 7 - 7 (1 bit)
access : read-write
DISABLE_TIME_OUT : Disable Time Out
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE_TIME_OUT_0
Enable time out
0x1 : DISABLE_TIME_OUT_1
Disable time out
End of enumeration elements list.
BOOT_BLK_CNT : BOOT_BLK_CNT
bits : 16 - 31 (16 bit)
access : read-write
Vendor Specific 2 Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARD_INT_D3_TEST : Card Interrupt Detection Test
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CARD_INT_D3_TEST_0
Check the card interrupt only when DATA3 is high.
0x1 : CARD_INT_D3_TEST_1
Check the card interrupt by ignoring the status of DATA3.
End of enumeration elements list.
TUNING_8bit_EN : TUNING_8bit_EN
bits : 4 - 4 (1 bit)
access : read-write
TUNING_1bit_EN : TUNING_1bit_EN
bits : 5 - 5 (1 bit)
access : read-write
TUNING_CMD_EN : TUNING_CMD_EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TUNING_CMD_EN_0
Auto tuning circuit does not check the CMD line.
0x1 : TUNING_CMD_EN_1
Auto tuning circuit checks the CMD line.
End of enumeration elements list.
HS400_WR_CLK_STOP_EN : HS400 Write Clock Stop Enable
bits : 10 - 10 (1 bit)
access : read-write
HS400_RD_CLK_STOP_EN : HS400 Read Clock Stop Enable
bits : 11 - 11 (1 bit)
access : read-write
ACMD23_ARGU2_EN : Argument2 register enable for ACMD23
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : ACMD23_ARGU2_EN_0
Disable
0x1 : ACMD23_ARGU2_EN_1
Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable.
End of enumeration elements list.
PART_DLL_DEBUG : debug for part dll
bits : 13 - 13 (1 bit)
access : read-write
BUS_RST : BUS reset
bits : 14 - 14 (1 bit)
access : read-write
Tuning Control Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING_START_TAP : TUNING_START_TAP
bits : 0 - 7 (8 bit)
access : read-write
TUNING_COUNTER : TUNING_COUNTER
bits : 8 - 15 (8 bit)
access : read-write
TUNING_STEP : TUNING_STEP
bits : 16 - 18 (3 bit)
access : read-write
TUNING_WINDOW : TUNING_WINDOW
bits : 20 - 22 (3 bit)
access : read-write
STD_TUNING_EN : STD_TUNING_EN
bits : 24 - 24 (1 bit)
access : read-write
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