\n
address_offset : 0x0 Bytes (0x0)
size : 0x110 byte (0x0)
mem_usage : registers
protection : not protected
PCC WDOG2 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PCD_0
Divide by 1.
0x1 : PCD_1
Divide by 2.
0x2 : PCD_2
Divide by 3.
0x3 : PCD_3
Divide by 4.
0x4 : PCD_4
Divide by 5.
0x5 : PCD_5
Divide by 6.
0x6 : PCD_6
Divide by 7.
0x7 : PCD_7
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC DMA1 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC RGPIO2P1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC FLEXBUS Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC SEMA42_1 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC DMA_MUX1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC CAAM Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC TPM4 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC TPM5 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPIT1 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPSPI2 Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPSPI3 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPI2C4 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPI2C5 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPUART4 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPUART5 Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC FLEXIO1 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC USB0 Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PCD_0
Divide by 1.
0x1 : PCD_1
Divide by 2.
0x2 : PCD_2
Divide by 3.
0x3 : PCD_3
Divide by 4.
0x4 : PCD_4
Divide by 5.
0x5 : PCD_5
Divide by 6.
0x6 : PCD_6
Divide by 7.
0x7 : PCD_7
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC USB1 Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCC USB_PHY Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC USB_PL301 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCC USDHC0 Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PCD_0
Divide by 1.
0x1 : PCD_1
Divide by 2.
0x2 : PCD_2
Divide by 3.
0x3 : PCD_3
Divide by 4.
0x4 : PCD_4
Divide by 5.
0x5 : PCD_5
Divide by 6.
0x6 : PCD_6
Divide by 7.
0x7 : PCD_7
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC USDHC1 Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PCD_0
Divide by 1.
0x1 : PCD_1
Divide by 2.
0x2 : PCD_2
Divide by 3.
0x3 : PCD_3
Divide by 4.
0x4 : PCD_4
Divide by 5.
0x5 : PCD_5
Divide by 6.
0x6 : PCD_6
Divide by 7.
0x7 : PCD_7
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC WDOG1 Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PCD_0
Divide by 1.
0x1 : PCD_1
Divide by 2.
0x2 : PCD_2
Divide by 3.
0x3 : PCD_3
Divide by 4.
0x4 : PCD_4
Divide by 5.
0x5 : PCD_5
Divide by 6.
0x6 : PCD_6
Divide by 7.
0x7 : PCD_7
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
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