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PCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x110 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PCC_WDOG2

PCC_DMA1

PCC_RGPIO2P1

PCC_FLEXBUS

PCC_SEMA42_1

PCC_DMA_MUX1

PCC_CAAM

PCC_TPM4

PCC_TPM5

PCC_LPIT1

PCC_LPSPI2

PCC_LPSPI3

PCC_LPI2C4

PCC_LPI2C5

PCC_LPUART4

PCC_LPUART5

PCC_FLEXIO1

PCC_USB0

PCC_USB1

PCC_USB_PHY

PCC_USB_PL301

PCC_USDHC0

PCC_USDHC1

PCC_WDOG1


PCC_WDOG2

PCC WDOG2 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_WDOG2 PCC_WDOG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_DMA1

PCC DMA1 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_DMA1 PCC_DMA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_RGPIO2P1

PCC RGPIO2P1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_RGPIO2P1 PCC_RGPIO2P1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_FLEXBUS

PCC FLEXBUS Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_FLEXBUS PCC_FLEXBUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_SEMA42_1

PCC SEMA42_1 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_SEMA42_1 PCC_SEMA42_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_DMA_MUX1

PCC DMA_MUX1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_DMA_MUX1 PCC_DMA_MUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_CAAM

PCC CAAM Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_CAAM PCC_CAAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TPM4

PCC TPM4 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM4 PCC_TPM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TPM5

PCC TPM5 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM5 PCC_TPM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPIT1

PCC LPIT1 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPIT1 PCC_LPIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPSPI2

PCC LPSPI2 Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPSPI2 PCC_LPSPI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPSPI3

PCC LPSPI3 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPSPI3 PCC_LPSPI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPI2C4

PCC LPI2C4 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPI2C4 PCC_LPI2C4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPI2C5

PCC LPI2C5 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPI2C5 PCC_LPI2C5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART4

PCC LPUART4 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART4 PCC_LPUART4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART5

PCC LPUART5 Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART5 PCC_LPUART5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_FLEXIO1

PCC FLEXIO1 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_FLEXIO1 PCC_FLEXIO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_USB0

PCC USB0 Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_USB0 PCC_USB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_USB1

PCC USB1 Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCC_USB1 PCC_USB1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCC_USB_PHY

PCC USB_PHY Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_USB_PHY PCC_USB_PHY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_USB_PL301

PCC USB_PL301 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCC_USB_PL301 PCC_USB_PL301 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCC_USDHC0

PCC USDHC0 Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_USDHC0 PCC_USDHC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_USDHC1

PCC USDHC1 Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_USDHC1 PCC_USDHC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_WDOG1

PCC WDOG1 Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_WDOG1 PCC_WDOG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.



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