Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x254 byte (0x0)
mem_usage : registers
protection : not protected
LCDIF General Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUN : When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display
bits : 0 - 0 (1 bit)
access : read-write
DATA_FORMAT_24_BIT : Used only when WORD_LENGTH = 3, i
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ALL_24_BITS_VALID
Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
0x1 : DROP_UPPER_2_BITS_PER_BYTE
Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
End of enumeration elements list.
DATA_FORMAT_18_BIT : Used only when WORD_LENGTH = 2, i.e. 18-bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LOWER_18_BITS_VALID
Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
0x1 : UPPER_18_BITS_VALID
Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
End of enumeration elements list.
DATA_FORMAT_16_BIT : When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format
bits : 3 - 3 (1 bit)
access : read-write
MASTER : Set this bit to make the LCDIF act as a bus master.
bits : 5 - 5 (1 bit)
access : read-write
WORD_LENGTH : Input data format.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : 16_BIT
Input data is 16 bits per pixel.
0x1 : 8_BIT
Input data is 8 bits wide.
0x2 : 18_BIT
Input data is 18 bits per pixel.
0x3 : 24_BIT
Input data is 24 bits per pixel.
End of enumeration elements list.
LCD_DATABUS_WIDTH : LCD Data bus transfer width.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : 16_BIT
16-bit data bus mode.
0x1 : 8_BIT
8-bit data bus mode.
0x2 : 18_BIT
18-bit data bus mode.
0x3 : 24_BIT
24-bit data bus mode.
End of enumeration elements list.
CSC_DATA_SWIZZLE : This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : NO_SWAP
No byte swapping.(Little endian)
0x1 : BIG_ENDIAN_SWAP
Big Endian swap (swap bytes 0,3 and 1,2).
0x2 : HWD_SWAP
Swap half-words.
0x3 : HWD_BYTE_SWAP
Swap bytes within each half-word.
End of enumeration elements list.
INPUT_DATA_SWIZZLE : This field specifies how to swap the bytes fetched by the bus master interface
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NO_SWAP
No byte swapping.(Little endian)
0x1 : BIG_ENDIAN_SWAP
Big Endian swap (swap bytes 0,3 and 1,2).
0x2 : HWD_SWAP
Swap half-words.
0x3 : HWD_BYTE_SWAP
Swap bytes within each half-word.
End of enumeration elements list.
DOTCLK_MODE : Set this bit to 1 to make the hardware go into the DOTCLK mode, i
bits : 17 - 17 (1 bit)
access : read-write
BYPASS_COUNT : When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out
bits : 19 - 19 (1 bit)
access : read-write
SHIFT_NUM_BITS : The data to be transmitted is shifted left or right by this number of bits.
bits : 21 - 25 (5 bit)
access : read-write
DATA_SHIFT_DIR : Use this bit to determine the direction of shift of transmit data.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TXDATA_SHIFT_LEFT
Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
0x1 : TXDATA_SHIFT_RIGHT
Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
End of enumeration elements list.
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : This bit must be set to zero to enable normal operation of the LCDIF
bits : 31 - 31 (1 bit)
access : read-write
LCDIF General Control1 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET : Reset bit for the external LCD controller
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LCDRESET_LOW
LCD_RESET output signal is low.
0x1 : LCDRESET_HIGH
LCD_RESET output signal is high.
End of enumeration elements list.
VSYNC_EDGE_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
CUR_FRAME_DONE_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
UNDERFLOW_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
OVERFLOW_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
VSYNC_EDGE_IRQ_EN : This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode
bits : 12 - 12 (1 bit)
access : read-write
CUR_FRAME_DONE_IRQ_EN : This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state
bits : 13 - 13 (1 bit)
access : read-write
UNDERFLOW_IRQ_EN : This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.
bits : 14 - 14 (1 bit)
access : read-write
OVERFLOW_IRQ_EN : This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.
bits : 15 - 15 (1 bit)
access : read-write
BYTE_PACKING_FORMAT : This bitfield is used to show which data bytes in a 32-bit word are valid
bits : 16 - 19 (4 bit)
access : read-write
IRQ_ON_ALTERNATE_FIELDS : If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field
bits : 20 - 20 (1 bit)
access : read-write
FIFO_CLEAR : Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.
bits : 21 - 21 (1 bit)
access : read-write
START_INTERLACE_FROM_SECOND_FIELD : The default is to grab the odd lines first and then the even lines
bits : 22 - 22 (1 bit)
access : read-write
INTERLACE_FIELDS : Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field
bits : 23 - 23 (1 bit)
access : read-write
RECOVER_ON_UNDERFLOW : Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame
bits : 24 - 24 (1 bit)
access : read-write
BM_ERROR_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
BM_ERROR_IRQ_EN : This bit is set to enable bus master error interrupt in the LCDIF master mode.
bits : 26 - 26 (1 bit)
access : read-write
LCDIF General Control1 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET : Reset bit for the external LCD controller
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LCDRESET_LOW
LCD_RESET output signal is low.
0x1 : LCDRESET_HIGH
LCD_RESET output signal is high.
End of enumeration elements list.
VSYNC_EDGE_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
CUR_FRAME_DONE_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
UNDERFLOW_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
OVERFLOW_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
VSYNC_EDGE_IRQ_EN : This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode
bits : 12 - 12 (1 bit)
access : read-write
CUR_FRAME_DONE_IRQ_EN : This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state
bits : 13 - 13 (1 bit)
access : read-write
UNDERFLOW_IRQ_EN : This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.
bits : 14 - 14 (1 bit)
access : read-write
OVERFLOW_IRQ_EN : This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.
bits : 15 - 15 (1 bit)
access : read-write
BYTE_PACKING_FORMAT : This bitfield is used to show which data bytes in a 32-bit word are valid
bits : 16 - 19 (4 bit)
access : read-write
IRQ_ON_ALTERNATE_FIELDS : If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field
bits : 20 - 20 (1 bit)
access : read-write
FIFO_CLEAR : Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.
bits : 21 - 21 (1 bit)
access : read-write
START_INTERLACE_FROM_SECOND_FIELD : The default is to grab the odd lines first and then the even lines
bits : 22 - 22 (1 bit)
access : read-write
INTERLACE_FIELDS : Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field
bits : 23 - 23 (1 bit)
access : read-write
RECOVER_ON_UNDERFLOW : Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame
bits : 24 - 24 (1 bit)
access : read-write
BM_ERROR_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
BM_ERROR_IRQ_EN : This bit is set to enable bus master error interrupt in the LCDIF master mode.
bits : 26 - 26 (1 bit)
access : read-write
LCDIF General Control1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET : Reset bit for the external LCD controller
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LCDRESET_LOW
LCD_RESET output signal is low.
0x1 : LCDRESET_HIGH
LCD_RESET output signal is high.
End of enumeration elements list.
VSYNC_EDGE_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
CUR_FRAME_DONE_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
UNDERFLOW_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
OVERFLOW_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
VSYNC_EDGE_IRQ_EN : This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode
bits : 12 - 12 (1 bit)
access : read-write
CUR_FRAME_DONE_IRQ_EN : This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state
bits : 13 - 13 (1 bit)
access : read-write
UNDERFLOW_IRQ_EN : This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.
bits : 14 - 14 (1 bit)
access : read-write
OVERFLOW_IRQ_EN : This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.
bits : 15 - 15 (1 bit)
access : read-write
BYTE_PACKING_FORMAT : This bitfield is used to show which data bytes in a 32-bit word are valid
bits : 16 - 19 (4 bit)
access : read-write
IRQ_ON_ALTERNATE_FIELDS : If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field
bits : 20 - 20 (1 bit)
access : read-write
FIFO_CLEAR : Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.
bits : 21 - 21 (1 bit)
access : read-write
START_INTERLACE_FROM_SECOND_FIELD : The default is to grab the odd lines first and then the even lines
bits : 22 - 22 (1 bit)
access : read-write
INTERLACE_FIELDS : Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field
bits : 23 - 23 (1 bit)
access : read-write
RECOVER_ON_UNDERFLOW : Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame
bits : 24 - 24 (1 bit)
access : read-write
BM_ERROR_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
BM_ERROR_IRQ_EN : This bit is set to enable bus master error interrupt in the LCDIF master mode.
bits : 26 - 26 (1 bit)
access : read-write
Bus Master Error Status Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Virtual address at which bus master error occurred.
bits : 0 - 31 (32 bit)
access : read-write
CRC Status Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_VALUE : Calculated CRC value.
bits : 0 - 31 (32 bit)
access : read-write
LCD Interface Status Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LFIFO_COUNT : Read only view of the current count in Latency buffer (LFIFO).
bits : 0 - 8 (9 bit)
access : read-only
TXFIFO_EMPTY : Read only view of the signals that indicates LCD TXFIFO is empty.
bits : 26 - 26 (1 bit)
access : read-only
TXFIFO_FULL : Read only view of the signals that indicates LCD TXFIFO is full.
bits : 27 - 27 (1 bit)
access : read-only
LFIFO_EMPTY : Read only view of the signals that indicates LCD LFIFO is empty.
bits : 28 - 28 (1 bit)
access : read-only
LFIFO_FULL : Read only view of the signals that indicates LCD LFIFO is full.
bits : 29 - 29 (1 bit)
access : read-only
PRESENT : 0: LCDIF not present on this product 1: LCDIF is present.
bits : 31 - 31 (1 bit)
access : read-only
LCDIF General Control1 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET : Reset bit for the external LCD controller
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LCDRESET_LOW
LCD_RESET output signal is low.
0x1 : LCDRESET_HIGH
LCD_RESET output signal is high.
End of enumeration elements list.
VSYNC_EDGE_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
CUR_FRAME_DONE_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
UNDERFLOW_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
OVERFLOW_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
VSYNC_EDGE_IRQ_EN : This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode
bits : 12 - 12 (1 bit)
access : read-write
CUR_FRAME_DONE_IRQ_EN : This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state
bits : 13 - 13 (1 bit)
access : read-write
UNDERFLOW_IRQ_EN : This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.
bits : 14 - 14 (1 bit)
access : read-write
OVERFLOW_IRQ_EN : This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.
bits : 15 - 15 (1 bit)
access : read-write
BYTE_PACKING_FORMAT : This bitfield is used to show which data bytes in a 32-bit word are valid
bits : 16 - 19 (4 bit)
access : read-write
IRQ_ON_ALTERNATE_FIELDS : If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field
bits : 20 - 20 (1 bit)
access : read-write
FIFO_CLEAR : Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.
bits : 21 - 21 (1 bit)
access : read-write
START_INTERLACE_FROM_SECOND_FIELD : The default is to grab the odd lines first and then the even lines
bits : 22 - 22 (1 bit)
access : read-write
INTERLACE_FIELDS : Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field
bits : 23 - 23 (1 bit)
access : read-write
RECOVER_ON_UNDERFLOW : Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame
bits : 24 - 24 (1 bit)
access : read-write
BM_ERROR_IRQ : This bit is set to indicate that an interrupt is requested by the LCDIF block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No Interrupt Request Pending.
0x1 : REQUEST
Interrupt Request Pending.
End of enumeration elements list.
BM_ERROR_IRQ_EN : This bit is set to enable bus master error interrupt in the LCDIF master mode.
bits : 26 - 26 (1 bit)
access : read-write
LCDIF General Control2 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVEN_LINE_PATTERN : This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : RGB
RGB
0x1 : RBG
RBG
0x2 : GBR
GBR
0x3 : GRB
GRB
0x4 : BRG
BRG
0x5 : BGR
BGR
End of enumeration elements list.
ODD_LINE_PATTERN : This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : RGB
RGB
0x1 : RBG
RBG
0x2 : GBR
GBR
0x3 : GRB
GRB
0x4 : BRG
BRG
0x5 : BGR
BGR
End of enumeration elements list.
BURST_LEN_8 : By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)
bits : 20 - 20 (1 bit)
access : read-write
OUTSTANDING_REQS : This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : REQ_1
REQ_1
0x1 : REQ_2
REQ_2
0x2 : REQ_4
REQ_4
0x3 : REQ_8
REQ_8
0x4 : REQ_16
REQ_16
End of enumeration elements list.
LCDIF AS Buffer Control Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AS_ENABLE : When this bit is set by software, the LCDIF will start fetching AS buffer data in bus master mode and combine it with another buffer
bits : 0 - 0 (1 bit)
access : read-write
ALPHA_CTRL : Determines how the alpha value is constructed for this alpha surface
bits : 1 - 2 (2 bit)
access : read-write
ENABLE_COLORKEY : Indicates that colorkey functionality is enabled for this alpha surface
bits : 3 - 3 (1 bit)
access : read-write
FORMAT : Indicates the input buffer format for AS
bits : 4 - 7 (4 bit)
access : read-write
ALPHA : Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL]
bits : 8 - 15 (8 bit)
access : read-write
ROP : Indicates a raster operation to perform when enabled
bits : 16 - 19 (4 bit)
access : read-write
ALPHA_INVERT : Setting this bit to logic 0 will not alter the alpha value
bits : 20 - 20 (1 bit)
access : read-write
INPUT_DATA_SWIZZLE : This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF
bits : 21 - 22 (2 bit)
access : read-write
PS_DISABLE : When this bit is set by software, the LCDIF will disable PS buffer data.
bits : 23 - 23 (1 bit)
access : read-write
RVDS1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
Alpha Surface Buffer Pointer
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer for the alpha surface 0 buffer.
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of the next frame that will be transmitted by LCDIF.
bits : 0 - 31 (32 bit)
access : read-write
LCDIF General Control2 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVEN_LINE_PATTERN : This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : RGB
RGB
0x1 : RBG
RBG
0x2 : GBR
GBR
0x3 : GRB
GRB
0x4 : BRG
BRG
0x5 : BGR
BGR
End of enumeration elements list.
ODD_LINE_PATTERN : This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : RGB
RGB
0x1 : RBG
RBG
0x2 : GBR
GBR
0x3 : GRB
GRB
0x4 : BRG
BRG
0x5 : BGR
BGR
End of enumeration elements list.
BURST_LEN_8 : By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)
bits : 20 - 20 (1 bit)
access : read-write
OUTSTANDING_REQS : This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : REQ_1
REQ_1
0x1 : REQ_2
REQ_2
0x2 : REQ_4
REQ_4
0x3 : REQ_8
REQ_8
0x4 : REQ_16
REQ_16
End of enumeration elements list.
LCDIF Overlay Color Key Low
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : Low range of RGB color key applied to AS buffer
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-write
LCDIF Overlay Color Key High
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : High range of RGB color key applied to AS buffer
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-write
LCDIF General Control2 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVEN_LINE_PATTERN : This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : RGB
RGB
0x1 : RBG
RBG
0x2 : GBR
GBR
0x3 : GRB
GRB
0x4 : BRG
BRG
0x5 : BGR
BGR
End of enumeration elements list.
ODD_LINE_PATTERN : This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : RGB
RGB
0x1 : RBG
RBG
0x2 : GBR
GBR
0x3 : GRB
GRB
0x4 : BRG
BRG
0x5 : BGR
BGR
End of enumeration elements list.
BURST_LEN_8 : By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)
bits : 20 - 20 (1 bit)
access : read-write
OUTSTANDING_REQS : This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : REQ_1
REQ_1
0x1 : REQ_2
REQ_2
0x2 : REQ_4
REQ_4
0x3 : REQ_8
REQ_8
0x4 : REQ_16
REQ_16
End of enumeration elements list.
LCDIF General Control2 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVEN_LINE_PATTERN : This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : RGB
RGB
0x1 : RBG
RBG
0x2 : GBR
GBR
0x3 : GRB
GRB
0x4 : BRG
BRG
0x5 : BGR
BGR
End of enumeration elements list.
ODD_LINE_PATTERN : This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : RGB
RGB
0x1 : RBG
RBG
0x2 : GBR
GBR
0x3 : GRB
GRB
0x4 : BRG
BRG
0x5 : BGR
BGR
End of enumeration elements list.
BURST_LEN_8 : By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)
bits : 20 - 20 (1 bit)
access : read-write
OUTSTANDING_REQS : This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : REQ_1
REQ_1
0x1 : REQ_2
REQ_2
0x2 : REQ_4
REQ_4
0x3 : REQ_8
REQ_8
0x4 : REQ_16
REQ_16
End of enumeration elements list.
LCDIF Horizontal and Vertical Valid Data Count Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H_COUNT : Total valid data (pixels) in each horizontal line
bits : 0 - 15 (16 bit)
access : read-write
V_COUNT : Number of horizontal lines per frame which contain valid data
bits : 16 - 31 (16 bit)
access : read-write
LCDIF General Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUN : When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display
bits : 0 - 0 (1 bit)
access : read-write
DATA_FORMAT_24_BIT : Used only when WORD_LENGTH = 3, i
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ALL_24_BITS_VALID
Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
0x1 : DROP_UPPER_2_BITS_PER_BYTE
Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
End of enumeration elements list.
DATA_FORMAT_18_BIT : Used only when WORD_LENGTH = 2, i.e. 18-bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LOWER_18_BITS_VALID
Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
0x1 : UPPER_18_BITS_VALID
Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
End of enumeration elements list.
DATA_FORMAT_16_BIT : When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format
bits : 3 - 3 (1 bit)
access : read-write
MASTER : Set this bit to make the LCDIF act as a bus master.
bits : 5 - 5 (1 bit)
access : read-write
WORD_LENGTH : Input data format.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : 16_BIT
Input data is 16 bits per pixel.
0x1 : 8_BIT
Input data is 8 bits wide.
0x2 : 18_BIT
Input data is 18 bits per pixel.
0x3 : 24_BIT
Input data is 24 bits per pixel.
End of enumeration elements list.
LCD_DATABUS_WIDTH : LCD Data bus transfer width.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : 16_BIT
16-bit data bus mode.
0x1 : 8_BIT
8-bit data bus mode.
0x2 : 18_BIT
18-bit data bus mode.
0x3 : 24_BIT
24-bit data bus mode.
End of enumeration elements list.
CSC_DATA_SWIZZLE : This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : NO_SWAP
No byte swapping.(Little endian)
0x1 : BIG_ENDIAN_SWAP
Big Endian swap (swap bytes 0,3 and 1,2).
0x2 : HWD_SWAP
Swap half-words.
0x3 : HWD_BYTE_SWAP
Swap bytes within each half-word.
End of enumeration elements list.
INPUT_DATA_SWIZZLE : This field specifies how to swap the bytes fetched by the bus master interface
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NO_SWAP
No byte swapping.(Little endian)
0x1 : BIG_ENDIAN_SWAP
Big Endian swap (swap bytes 0,3 and 1,2).
0x2 : HWD_SWAP
Swap half-words.
0x3 : HWD_BYTE_SWAP
Swap bytes within each half-word.
End of enumeration elements list.
DOTCLK_MODE : Set this bit to 1 to make the hardware go into the DOTCLK mode, i
bits : 17 - 17 (1 bit)
access : read-write
BYPASS_COUNT : When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out
bits : 19 - 19 (1 bit)
access : read-write
SHIFT_NUM_BITS : The data to be transmitted is shifted left or right by this number of bits.
bits : 21 - 25 (5 bit)
access : read-write
DATA_SHIFT_DIR : Use this bit to determine the direction of shift of transmit data.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TXDATA_SHIFT_LEFT
Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
0x1 : TXDATA_SHIFT_RIGHT
Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
End of enumeration elements list.
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : This bit must be set to zero to enable normal operation of the LCDIF
bits : 31 - 31 (1 bit)
access : read-write
LCD Interface Current Buffer Address Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of the current frame being transmitted by LCDIF.
bits : 0 - 31 (32 bit)
access : read-write
LCD Interface Next Buffer Address Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of the next frame that will be transmitted by LCDIF.
bits : 0 - 31 (32 bit)
access : read-write
LCDIF VSYNC Mode and Dotclk Mode Control Register0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSYNC_PULSE_WIDTH : Number of units for which VSYNC signal is active
bits : 0 - 17 (18 bit)
access : read-write
HALF_LINE_MODE : When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line
bits : 18 - 18 (1 bit)
access : read-write
HALF_LINE : Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i
bits : 19 - 19 (1 bit)
access : read-write
VSYNC_PULSE_WIDTH_UNIT : Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles
bits : 20 - 20 (1 bit)
access : read-write
VSYNC_PERIOD_UNIT : Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles
bits : 21 - 21 (1 bit)
access : read-write
ENABLE_POL : Default 0 active low during valid data transfer on each horizontal line.
bits : 24 - 24 (1 bit)
access : read-write
DOTCLK_POL : Default is data launched at negative edge of DOTCLK and captured at positive edge
bits : 25 - 25 (1 bit)
access : read-write
HSYNC_POL : Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period
bits : 26 - 26 (1 bit)
access : read-write
VSYNC_POL : Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period
bits : 27 - 27 (1 bit)
access : read-write
ENABLE_PRESENT : Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK
bits : 28 - 28 (1 bit)
access : read-write
VSYNC_OEB : 0 means the VSYNC signal is an output, 1 means it is an input
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : VSYNC_OUTPUT
The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
0x1 : VSYNC_INPUT
The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
End of enumeration elements list.
LCDIF VSYNC Mode and Dotclk Mode Control Register0
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSYNC_PULSE_WIDTH : Number of units for which VSYNC signal is active
bits : 0 - 17 (18 bit)
access : read-write
HALF_LINE_MODE : When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line
bits : 18 - 18 (1 bit)
access : read-write
HALF_LINE : Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i
bits : 19 - 19 (1 bit)
access : read-write
VSYNC_PULSE_WIDTH_UNIT : Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles
bits : 20 - 20 (1 bit)
access : read-write
VSYNC_PERIOD_UNIT : Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles
bits : 21 - 21 (1 bit)
access : read-write
ENABLE_POL : Default 0 active low during valid data transfer on each horizontal line.
bits : 24 - 24 (1 bit)
access : read-write
DOTCLK_POL : Default is data launched at negative edge of DOTCLK and captured at positive edge
bits : 25 - 25 (1 bit)
access : read-write
HSYNC_POL : Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period
bits : 26 - 26 (1 bit)
access : read-write
VSYNC_POL : Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period
bits : 27 - 27 (1 bit)
access : read-write
ENABLE_PRESENT : Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK
bits : 28 - 28 (1 bit)
access : read-write
VSYNC_OEB : 0 means the VSYNC signal is an output, 1 means it is an input
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : VSYNC_OUTPUT
The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
0x1 : VSYNC_INPUT
The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
End of enumeration elements list.
LCDIF VSYNC Mode and Dotclk Mode Control Register0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSYNC_PULSE_WIDTH : Number of units for which VSYNC signal is active
bits : 0 - 17 (18 bit)
access : read-write
HALF_LINE_MODE : When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line
bits : 18 - 18 (1 bit)
access : read-write
HALF_LINE : Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i
bits : 19 - 19 (1 bit)
access : read-write
VSYNC_PULSE_WIDTH_UNIT : Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles
bits : 20 - 20 (1 bit)
access : read-write
VSYNC_PERIOD_UNIT : Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles
bits : 21 - 21 (1 bit)
access : read-write
ENABLE_POL : Default 0 active low during valid data transfer on each horizontal line.
bits : 24 - 24 (1 bit)
access : read-write
DOTCLK_POL : Default is data launched at negative edge of DOTCLK and captured at positive edge
bits : 25 - 25 (1 bit)
access : read-write
HSYNC_POL : Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period
bits : 26 - 26 (1 bit)
access : read-write
VSYNC_POL : Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period
bits : 27 - 27 (1 bit)
access : read-write
ENABLE_PRESENT : Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK
bits : 28 - 28 (1 bit)
access : read-write
VSYNC_OEB : 0 means the VSYNC signal is an output, 1 means it is an input
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : VSYNC_OUTPUT
The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
0x1 : VSYNC_INPUT
The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
End of enumeration elements list.
LCDIF VSYNC Mode and Dotclk Mode Control Register0
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSYNC_PULSE_WIDTH : Number of units for which VSYNC signal is active
bits : 0 - 17 (18 bit)
access : read-write
HALF_LINE_MODE : When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line
bits : 18 - 18 (1 bit)
access : read-write
HALF_LINE : Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i
bits : 19 - 19 (1 bit)
access : read-write
VSYNC_PULSE_WIDTH_UNIT : Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles
bits : 20 - 20 (1 bit)
access : read-write
VSYNC_PERIOD_UNIT : Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles
bits : 21 - 21 (1 bit)
access : read-write
ENABLE_POL : Default 0 active low during valid data transfer on each horizontal line.
bits : 24 - 24 (1 bit)
access : read-write
DOTCLK_POL : Default is data launched at negative edge of DOTCLK and captured at positive edge
bits : 25 - 25 (1 bit)
access : read-write
HSYNC_POL : Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period
bits : 26 - 26 (1 bit)
access : read-write
VSYNC_POL : Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period
bits : 27 - 27 (1 bit)
access : read-write
ENABLE_PRESENT : Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK
bits : 28 - 28 (1 bit)
access : read-write
VSYNC_OEB : 0 means the VSYNC signal is an output, 1 means it is an input
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : VSYNC_OUTPUT
The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
0x1 : VSYNC_INPUT
The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
End of enumeration elements list.
LCDIF General Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUN : When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display
bits : 0 - 0 (1 bit)
access : read-write
DATA_FORMAT_24_BIT : Used only when WORD_LENGTH = 3, i
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ALL_24_BITS_VALID
Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
0x1 : DROP_UPPER_2_BITS_PER_BYTE
Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
End of enumeration elements list.
DATA_FORMAT_18_BIT : Used only when WORD_LENGTH = 2, i.e. 18-bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LOWER_18_BITS_VALID
Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
0x1 : UPPER_18_BITS_VALID
Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
End of enumeration elements list.
DATA_FORMAT_16_BIT : When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format
bits : 3 - 3 (1 bit)
access : read-write
MASTER : Set this bit to make the LCDIF act as a bus master.
bits : 5 - 5 (1 bit)
access : read-write
WORD_LENGTH : Input data format.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : 16_BIT
Input data is 16 bits per pixel.
0x1 : 8_BIT
Input data is 8 bits wide.
0x2 : 18_BIT
Input data is 18 bits per pixel.
0x3 : 24_BIT
Input data is 24 bits per pixel.
End of enumeration elements list.
LCD_DATABUS_WIDTH : LCD Data bus transfer width.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : 16_BIT
16-bit data bus mode.
0x1 : 8_BIT
8-bit data bus mode.
0x2 : 18_BIT
18-bit data bus mode.
0x3 : 24_BIT
24-bit data bus mode.
End of enumeration elements list.
CSC_DATA_SWIZZLE : This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : NO_SWAP
No byte swapping.(Little endian)
0x1 : BIG_ENDIAN_SWAP
Big Endian swap (swap bytes 0,3 and 1,2).
0x2 : HWD_SWAP
Swap half-words.
0x3 : HWD_BYTE_SWAP
Swap bytes within each half-word.
End of enumeration elements list.
INPUT_DATA_SWIZZLE : This field specifies how to swap the bytes fetched by the bus master interface
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NO_SWAP
No byte swapping.(Little endian)
0x1 : BIG_ENDIAN_SWAP
Big Endian swap (swap bytes 0,3 and 1,2).
0x2 : HWD_SWAP
Swap half-words.
0x3 : HWD_BYTE_SWAP
Swap bytes within each half-word.
End of enumeration elements list.
DOTCLK_MODE : Set this bit to 1 to make the hardware go into the DOTCLK mode, i
bits : 17 - 17 (1 bit)
access : read-write
BYPASS_COUNT : When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out
bits : 19 - 19 (1 bit)
access : read-write
SHIFT_NUM_BITS : The data to be transmitted is shifted left or right by this number of bits.
bits : 21 - 25 (5 bit)
access : read-write
DATA_SHIFT_DIR : Use this bit to determine the direction of shift of transmit data.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TXDATA_SHIFT_LEFT
Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
0x1 : TXDATA_SHIFT_RIGHT
Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
End of enumeration elements list.
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : This bit must be set to zero to enable normal operation of the LCDIF
bits : 31 - 31 (1 bit)
access : read-write
LCDIF VSYNC Mode and Dotclk Mode Control Register1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSYNC_PERIOD : Total number of units between two positive or two negative edges of the VSYNC signal
bits : 0 - 31 (32 bit)
access : read-write
LCDIF VSYNC Mode and Dotclk Mode Control Register2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSYNC_PERIOD : Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal
bits : 0 - 17 (18 bit)
access : read-write
HSYNC_PULSE_WIDTH : Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active.
bits : 18 - 31 (14 bit)
access : read-write
LCDIF VSYNC Mode and Dotclk Mode Control Register3
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VERTICAL_WAIT_CNT : In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set
bits : 0 - 15 (16 bit)
access : read-write
HORIZONTAL_WAIT_CNT : In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins
bits : 16 - 27 (12 bit)
access : read-write
VSYNC_ONLY : This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation.
bits : 28 - 28 (1 bit)
access : read-write
MUX_SYNC_SIGNALS : When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins
bits : 29 - 29 (1 bit)
access : read-write
LCDIF VSYNC Mode and Dotclk Mode Control Register4
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOTCLK_H_VALID_DATA_CNT : Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode
bits : 0 - 17 (18 bit)
access : read-write
SYNC_SIGNALS_ON : Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end
bits : 18 - 18 (1 bit)
access : read-write
DOTCLK_DLY_SEL : This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin
bits : 29 - 31 (3 bit)
access : read-write
LCDIF General Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RUN : When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display
bits : 0 - 0 (1 bit)
access : read-write
DATA_FORMAT_24_BIT : Used only when WORD_LENGTH = 3, i
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ALL_24_BITS_VALID
Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
0x1 : DROP_UPPER_2_BITS_PER_BYTE
Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
End of enumeration elements list.
DATA_FORMAT_18_BIT : Used only when WORD_LENGTH = 2, i.e. 18-bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LOWER_18_BITS_VALID
Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
0x1 : UPPER_18_BITS_VALID
Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
End of enumeration elements list.
DATA_FORMAT_16_BIT : When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format
bits : 3 - 3 (1 bit)
access : read-write
MASTER : Set this bit to make the LCDIF act as a bus master.
bits : 5 - 5 (1 bit)
access : read-write
WORD_LENGTH : Input data format.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : 16_BIT
Input data is 16 bits per pixel.
0x1 : 8_BIT
Input data is 8 bits wide.
0x2 : 18_BIT
Input data is 18 bits per pixel.
0x3 : 24_BIT
Input data is 24 bits per pixel.
End of enumeration elements list.
LCD_DATABUS_WIDTH : LCD Data bus transfer width.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : 16_BIT
16-bit data bus mode.
0x1 : 8_BIT
8-bit data bus mode.
0x2 : 18_BIT
18-bit data bus mode.
0x3 : 24_BIT
24-bit data bus mode.
End of enumeration elements list.
CSC_DATA_SWIZZLE : This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : NO_SWAP
No byte swapping.(Little endian)
0x1 : BIG_ENDIAN_SWAP
Big Endian swap (swap bytes 0,3 and 1,2).
0x2 : HWD_SWAP
Swap half-words.
0x3 : HWD_BYTE_SWAP
Swap bytes within each half-word.
End of enumeration elements list.
INPUT_DATA_SWIZZLE : This field specifies how to swap the bytes fetched by the bus master interface
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NO_SWAP
No byte swapping.(Little endian)
0x1 : BIG_ENDIAN_SWAP
Big Endian swap (swap bytes 0,3 and 1,2).
0x2 : HWD_SWAP
Swap half-words.
0x3 : HWD_BYTE_SWAP
Swap bytes within each half-word.
End of enumeration elements list.
DOTCLK_MODE : Set this bit to 1 to make the hardware go into the DOTCLK mode, i
bits : 17 - 17 (1 bit)
access : read-write
BYPASS_COUNT : When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out
bits : 19 - 19 (1 bit)
access : read-write
SHIFT_NUM_BITS : The data to be transmitted is shifted left or right by this number of bits.
bits : 21 - 25 (5 bit)
access : read-write
DATA_SHIFT_DIR : Use this bit to determine the direction of shift of transmit data.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TXDATA_SHIFT_LEFT
Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
0x1 : TXDATA_SHIFT_RIGHT
Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
End of enumeration elements list.
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : This bit must be set to zero to enable normal operation of the LCDIF
bits : 31 - 31 (1 bit)
access : read-write
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