\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
Channel 0 Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
Channel 0 Configuration Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write
A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : A_ON_0
DMA Channel Always ON function is disabled
0x1 : A_ON_1
DMA Channel Always ON function is enabled
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIG_0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : TRIG_1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ENBL_0
DMA Mux channel is disabled
0x1 : ENBL_1
DMA Mux channel is enabled
End of enumeration elements list.
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