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DMA_CH_MUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CHCFG[0]

CHCFG[11]

CHCFG[12]

CHCFG[13]

CHCFG[3]

CHCFG[14]

CHCFG[15]

CHCFG[16]

CHCFG[17]

CHCFG[4]

CHCFG[18]

CHCFG[19]

CHCFG[20]

CHCFG[21]

CHCFG[5]

CHCFG[22]

CHCFG[1]

CHCFG[23]

CHCFG[24]

CHCFG[25]

CHCFG[6]

CHCFG[26]

CHCFG[27]

CHCFG[28]

CHCFG[29]

CHCFG[7]

CHCFG[30]

CHCFG[31]

CHCFG[8]

CHCFG[9]

CHCFG[2]

CHCFG[10]


CHCFG[0]

Channel 0 Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[0] CHCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[11]

Channel 0 Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[11] CHCFG[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[12]

Channel 0 Configuration Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[12] CHCFG[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[13]

Channel 0 Configuration Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[13] CHCFG[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[3]

Channel 0 Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[3] CHCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[14]

Channel 0 Configuration Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[14] CHCFG[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[15]

Channel 0 Configuration Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[15] CHCFG[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[16]

Channel 0 Configuration Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[16] CHCFG[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[17]

Channel 0 Configuration Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[17] CHCFG[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[4]

Channel 0 Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[4] CHCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[18]

Channel 0 Configuration Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[18] CHCFG[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[19]

Channel 0 Configuration Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[19] CHCFG[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[20]

Channel 0 Configuration Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[20] CHCFG[20] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[21]

Channel 0 Configuration Register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[21] CHCFG[21] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[5]

Channel 0 Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[5] CHCFG[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[22]

Channel 0 Configuration Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[22] CHCFG[22] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[1]

Channel 0 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[1] CHCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[23]

Channel 0 Configuration Register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[23] CHCFG[23] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[24]

Channel 0 Configuration Register
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[24] CHCFG[24] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[25]

Channel 0 Configuration Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[25] CHCFG[25] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[6]

Channel 0 Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[6] CHCFG[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[26]

Channel 0 Configuration Register
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[26] CHCFG[26] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[27]

Channel 0 Configuration Register
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[27] CHCFG[27] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[28]

Channel 0 Configuration Register
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[28] CHCFG[28] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[29]

Channel 0 Configuration Register
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[29] CHCFG[29] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[7]

Channel 0 Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[7] CHCFG[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[30]

Channel 0 Configuration Register
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[30] CHCFG[30] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[31]

Channel 0 Configuration Register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[31] CHCFG[31] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[8]

Channel 0 Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[8] CHCFG[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[9]

Channel 0 Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[9] CHCFG[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[2]

Channel 0 Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[2] CHCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[10]

Channel 0 Configuration Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[10] CHCFG[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 6 (7 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.



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