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SCG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x6FC byte (0x0)
mem_usage : registers
protection : not protected

Registers

VERID

CSR

SOSCCSR

SOSCDIV

SOSCCFG

RCCR

VCCR

HCCR

CLKOUTCNFG

SIRCCSR

SIRCDIV

SIRCCFG

FIRCCSR

FIRCDIV

FIRCCFG

FIRCTCFG

FIRCSTAT

PARAM

ROSCCSR

APLLCSR

APLLDIV

APLLCFG

APLLPFD

APLLNUM

APLLDENOM

APLLSS

APLLLOCK_CNFG

SPLLCSR

SPLLDIV

SPLLCFG

SPLLPFD

SPLLLOCK_CNFG


VERID

Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERID VERID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION

VERSION : SCG Version Number
bits : 0 - 31 (32 bit)
access : read-only


CSR

Clock Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVSLOW DIVBUS DIVPLAT DIVCORE SCS

DIVSLOW : Slow Clock Divide Ratio
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0 : DIVSLOW_0

no description available

0x1 : DIVSLOW_1

Divide-by-2

0x2 : DIVSLOW_2

Divide-by-3

0x3 : DIVSLOW_3

Divide-by-4

0x4 : DIVSLOW_4

Divide-by-5

0x5 : DIVSLOW_5

Divide-by-6

0x6 : DIVSLOW_6

Divide-by-7

0x7 : DIVSLOW_7

Divide-by-8

0x8 : DIVSLOW_8

no description available

0x9 : DIVSLOW_9

no description available

0xA : DIVSLOW_10

no description available

0xB : DIVSLOW_11

no description available

0xC : DIVSLOW_12

no description available

0xD : DIVSLOW_13

no description available

0xE : DIVSLOW_14

no description available

0xF : DIVSLOW_15

no description available

End of enumeration elements list.

DIVBUS : Bus Clock Divide Ratio
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

0 : DIVBUS_0

Divide-by-1

0x1 : DIVBUS_1

Divide-by-2

0x2 : DIVBUS_2

Divide-by-3

0x3 : DIVBUS_3

Divide-by-4

0x4 : DIVBUS_4

Divide-by-5

0x5 : DIVBUS_5

Divide-by-6

0x6 : DIVBUS_6

Divide-by-7

0x7 : DIVBUS_7

Divide-by-8

0x8 : DIVBUS_8

Divide-by-9

0x9 : DIVBUS_9

Divide-by-10

0xA : DIVBUS_10

Divide-by-11

0xB : DIVBUS_11

Divide-by-12

0xC : DIVBUS_12

Divide-by-13

0xD : DIVBUS_13

Divide-by-14

0xE : DIVBUS_14

Divide-by-15

0xF : DIVBUS_15

Divide-by-16

End of enumeration elements list.

DIVPLAT : Platform Clock Divide Ratio
bits : 12 - 15 (4 bit)
access : read-only

Enumeration:

0 : DIVPLAT_0

Divide-by-1

End of enumeration elements list.

DIVCORE : Core Clock Divide Ratio
bits : 16 - 19 (4 bit)
access : read-only

Enumeration:

0 : DIVCORE_0

Divide-by-1

0x1 : DIVCORE_1

Divide-by-2

0x2 : DIVCORE_2

Divide-by-3

0x3 : DIVCORE_3

Divide-by-4

0x4 : DIVCORE_4

Divide-by-5

0x5 : DIVCORE_5

Divide-by-6

0x6 : DIVCORE_6

Divide-by-7

0x7 : DIVCORE_7

Divide-by-8

0x8 : DIVCORE_8

Divide-by-9

0x9 : DIVCORE_9

Divide-by-10

0xA : DIVCORE_10

Divide-by-11

0xB : DIVCORE_11

Divide-by-12

0xC : DIVCORE_12

Divide-by-13

0xD : DIVCORE_13

Divide-by-14

0xE : DIVCORE_14

Divide-by-15

0xF : DIVCORE_15

Divide-by-16

End of enumeration elements list.

SCS : System Clock Source
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

0x1 : SCS_1

no description available

0x2 : SCS_2

no description available

0x3 : SCS_3

no description available

0x4 : SCS_4

no description available

0x5 : SCS_5

no description available

0x6 : SCS_6

no description available

End of enumeration elements list.


SOSCCSR

System OSC Control Status Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOSCCSR SOSCCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOSCEN SOSCSTEN SOSCLPEN SOSCCM SOSCCMRE LK SOSCVLD SOSCSEL SOSCERR

SOSCEN : System OSC Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SOSCEN_0

System OSC is disabled

0x1 : SOSCEN_1

System OSC is enabled

End of enumeration elements list.

SOSCSTEN : System OSC Stop Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SOSCSTEN_0

System OSC is disabled in Stop modes

0x1 : SOSCSTEN_1

no description available

End of enumeration elements list.

SOSCLPEN : System OSC Low Power Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SOSCLPEN_0

System OSC is disabled in VLP modes

0x1 : SOSCLPEN_1

System OSC is enabled in VLP modes

End of enumeration elements list.

SOSCCM : System OSC Clock Monitor
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SOSCCM_0

System OSC Clock Monitor is disabled

0x1 : SOSCCM_1

System OSC Clock Monitor is enabled

End of enumeration elements list.

SOSCCMRE : System OSC Clock Monitor Reset Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SOSCCMRE_0

Clock Monitor generates interrupt when error detected

0x1 : SOSCCMRE_1

Clock Monitor generates reset when error detected

End of enumeration elements list.

LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : LK_0

This Control Status Register can be written.

0x1 : LK_1

This Control Status Register cannot be written.

End of enumeration elements list.

SOSCVLD : System OSC Valid
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0 : SOSCVLD_0

System OSC is not enabled or clock is not valid

0x1 : SOSCVLD_1

System OSC is enabled and output clock is valid

End of enumeration elements list.

SOSCSEL : System OSC Selected
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

0 : SOSCSEL_0

System OSC is not the system clock source

0x1 : SOSCSEL_1

System OSC is the system clock source

End of enumeration elements list.

SOSCERR : System OSC Clock Error
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SOSCERR_0

System OSC Clock Monitor is disabled or has not detected an error

0x1 : SOSCERR_1

System OSC Clock Monitor is enabled and detected an error

End of enumeration elements list.


SOSCDIV

System OSC Divide Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOSCDIV SOSCDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOSCDIV1 SOSCDIV2 SOSCDIV3

SOSCDIV1 : System OSC Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : SOSCDIV1_0

Output disabled

0x1 : SOSCDIV1_1

Divide by 1

0x2 : SOSCDIV1_2

Divide by 2

0x3 : SOSCDIV1_3

Divide by 4

0x4 : SOSCDIV1_4

Divide by 8

0x5 : SOSCDIV1_5

Divide by 16

0x6 : SOSCDIV1_6

Divide by 32

0x7 : SOSCDIV1_7

Divide by 64

End of enumeration elements list.

SOSCDIV2 : System OSC Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : SOSCDIV2_0

Output disabled

0x1 : SOSCDIV2_1

Divide by 1

0x2 : SOSCDIV2_2

Divide by 2

0x3 : SOSCDIV2_3

Divide by 4

0x4 : SOSCDIV2_4

Divide by 8

0x5 : SOSCDIV2_5

Divide by 16

0x6 : SOSCDIV2_6

Divide by 32

0x7 : SOSCDIV2_7

Divide by 64

End of enumeration elements list.

SOSCDIV3 : System OSC Clock Divide 3
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : SOSCDIV3_0

Output disabled

0x1 : SOSCDIV3_1

Divide by 1

0x2 : SOSCDIV3_2

Divide by 2

0x3 : SOSCDIV3_3

Divide by 4

0x4 : SOSCDIV3_4

Divide by 8

0x5 : SOSCDIV3_5

Divide by 16

0x6 : SOSCDIV3_6

Divide by 32

0x7 : SOSCDIV3_7

Divide by 64

End of enumeration elements list.


SOSCCFG

System Oscillator Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOSCCFG SOSCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EREFS HGO

EREFS : External Reference Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : EREFS_0

no description available

0x1 : EREFS_1

no description available

End of enumeration elements list.

HGO : High Gain Oscillator Select
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : HGO_0

Configure crystal oscillator for low-power operation

0x1 : HGO_1

Configure crystal oscillator for high-gain operation

End of enumeration elements list.


RCCR

Run Clock Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCCR RCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVSLOW DIVBUS DIVPLAT DIVCORE SCS

DIVSLOW : Slow Clock Divide Ratio
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : DIVSLOW_0

no description available

0x1 : DIVSLOW_1

Divide-by-2

0x2 : DIVSLOW_2

Divide-by-3

0x3 : DIVSLOW_3

Divide-by-4

0x4 : DIVSLOW_4

Divide-by-5

0x5 : DIVSLOW_5

Divide-by-6

0x6 : DIVSLOW_6

Divide-by-7

0x7 : DIVSLOW_7

Divide-by-8

0x8 : DIVSLOW_8

no description available

0x9 : DIVSLOW_9

no description available

0xA : DIVSLOW_10

no description available

0xB : DIVSLOW_11

no description available

0xC : DIVSLOW_12

no description available

0xD : DIVSLOW_13

no description available

0xE : DIVSLOW_14

no description available

0xF : DIVSLOW_15

no description available

End of enumeration elements list.

DIVBUS : Bus Clock Divide Ratio
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : DIVBUS_0

Divide-by-1

0x1 : DIVBUS_1

Divide-by-2

0x2 : DIVBUS_2

Divide-by-3

0x3 : DIVBUS_3

Divide-by-4

0x4 : DIVBUS_4

Divide-by-5

0x5 : DIVBUS_5

Divide-by-6

0x6 : DIVBUS_6

Divide-by-7

0x7 : DIVBUS_7

Divide-by-8

0x8 : DIVBUS_8

Divide-by-9

0x9 : DIVBUS_9

Divide-by-10

0xA : DIVBUS_10

Divide-by-11

0xB : DIVBUS_11

Divide-by-12

0xC : DIVBUS_12

Divide-by-13

0xD : DIVBUS_13

Divide-by-14

0xE : DIVBUS_14

Divide-by-15

0xF : DIVBUS_15

Divide-by-16

End of enumeration elements list.

DIVPLAT : Platform Clock Divide Ratio
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0 : DIVPLAT_0

Divide-by-1

End of enumeration elements list.

DIVCORE : Core Clock Divide Ratio
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : DIVCORE_0

Divide-by-1

0x1 : DIVCORE_1

Divide-by-2

0x2 : DIVCORE_2

Divide-by-3

0x3 : DIVCORE_3

Divide-by-4

0x4 : DIVCORE_4

Divide-by-5

0x5 : DIVCORE_5

Divide-by-6

0x6 : DIVCORE_6

Divide-by-7

0x7 : DIVCORE_7

Divide-by-8

0x8 : DIVCORE_8

Divide-by-9

0x9 : DIVCORE_9

Divide-by-10

0xA : DIVCORE_10

Divide-by-11

0xB : DIVCORE_11

Divide-by-12

0xC : DIVCORE_12

Divide-by-13

0xD : DIVCORE_13

Divide-by-14

0xE : DIVCORE_14

Divide-by-15

0xF : DIVCORE_15

Divide-by-16

End of enumeration elements list.

SCS : System Clock Source
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x1 : SCS_1

no description available

0x2 : SCS_2

no description available

0x3 : SCS_3

no description available

0x4 : SCS_4

no description available

0x5 : SCS_5

no description available

0x6 : SCS_6

no description available

End of enumeration elements list.


VCCR

VLPR Clock Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCCR VCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVSLOW DIVBUS DIVPLAT DIVCORE SCS

DIVSLOW : Slow Clock Divide Ratio
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : DIVSLOW_0

no description available

0x1 : DIVSLOW_1

Divide-by-2

0x2 : DIVSLOW_2

Divide-by-3

0x3 : DIVSLOW_3

Divide-by-4

0x4 : DIVSLOW_4

Divide-by-5

0x5 : DIVSLOW_5

Divide-by-6

0x6 : DIVSLOW_6

Divide-by-7

0x7 : DIVSLOW_7

Divide-by-8

0x8 : DIVSLOW_8

no description available

0x9 : DIVSLOW_9

no description available

0xA : DIVSLOW_10

no description available

0xB : DIVSLOW_11

no description available

0xC : DIVSLOW_12

no description available

0xD : DIVSLOW_13

no description available

0xE : DIVSLOW_14

no description available

0xF : DIVSLOW_15

no description available

End of enumeration elements list.

DIVBUS : Bus Clock Divide Ratio
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : DIVBUS_0

Divide-by-1

0x1 : DIVBUS_1

Divide-by-2

0x2 : DIVBUS_2

Divide-by-3

0x3 : DIVBUS_3

Divide-by-4

0x4 : DIVBUS_4

Divide-by-5

0x5 : DIVBUS_5

Divide-by-6

0x6 : DIVBUS_6

Divide-by-7

0x7 : DIVBUS_7

Divide-by-8

0x8 : DIVBUS_8

Divide-by-9

0x9 : DIVBUS_9

Divide-by-10

0xA : DIVBUS_10

Divide-by-11

0xB : DIVBUS_11

Divide-by-12

0xC : DIVBUS_12

Divide-by-13

0xD : DIVBUS_13

Divide-by-14

0xE : DIVBUS_14

Divide-by-15

0xF : DIVBUS_15

Divide-by-16

End of enumeration elements list.

DIVPLAT : Platform Clock Divide Ratio
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0 : DIVPLAT_0

Divide-by-1

End of enumeration elements list.

DIVCORE : Core Clock Divide Ratio
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : DIVCORE_0

Divide-by-1

0x1 : DIVCORE_1

Divide-by-2

0x2 : DIVCORE_2

Divide-by-3

0x3 : DIVCORE_3

Divide-by-4

0x4 : DIVCORE_4

Divide-by-5

0x5 : DIVCORE_5

Divide-by-6

0x6 : DIVCORE_6

Divide-by-7

0x7 : DIVCORE_7

Divide-by-8

0x8 : DIVCORE_8

Divide-by-9

0x9 : DIVCORE_9

Divide-by-10

0xA : DIVCORE_10

Divide-by-11

0xB : DIVCORE_11

Divide-by-12

0xC : DIVCORE_12

Divide-by-13

0xD : DIVCORE_13

Divide-by-14

0xE : DIVCORE_14

Divide-by-15

0xF : DIVCORE_15

Divide-by-16

End of enumeration elements list.

SCS : System Clock Source
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x1 : SCS_1

no description available

0x2 : SCS_2

no description available

0x3 : SCS_3

no description available

0x4 : SCS_4

no description available

End of enumeration elements list.


HCCR

HSRUN Clock Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCR HCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVSLOW DIVBUS DIVPLAT DIVCORE SCS

DIVSLOW : Slow Clock Divide Ratio
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : DIVSLOW_0

no description available

0x1 : DIVSLOW_1

Divide-by-2

0x2 : DIVSLOW_2

Divide-by-3

0x3 : DIVSLOW_3

Divide-by-4

0x4 : DIVSLOW_4

Divide-by-5

0x5 : DIVSLOW_5

Divide-by-6

0x6 : DIVSLOW_6

Divide-by-7

0x7 : DIVSLOW_7

Divide-by-8

0x8 : DIVSLOW_8

no description available

0x9 : DIVSLOW_9

no description available

0xA : DIVSLOW_10

no description available

0xB : DIVSLOW_11

no description available

0xC : DIVSLOW_12

no description available

0xD : DIVSLOW_13

no description available

0xE : DIVSLOW_14

no description available

0xF : DIVSLOW_15

no description available

End of enumeration elements list.

DIVBUS : Bus Clock Divide Ratio
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : DIVBUS_0

Divide-by-1

0x1 : DIVBUS_1

Divide-by-2

0x2 : DIVBUS_2

Divide-by-3

0x3 : DIVBUS_3

Divide-by-4

0x4 : DIVBUS_4

Divide-by-5

0x5 : DIVBUS_5

Divide-by-6

0x6 : DIVBUS_6

Divide-by-7

0x7 : DIVBUS_7

Divide-by-8

0x8 : DIVBUS_8

Divide-by-9

0x9 : DIVBUS_9

Divide-by-10

0xA : DIVBUS_10

Divide-by-11

0xB : DIVBUS_11

Divide-by-12

0xC : DIVBUS_12

Divide-by-13

0xD : DIVBUS_13

Divide-by-14

0xE : DIVBUS_14

Divide-by-15

0xF : DIVBUS_15

Divide-by-16

End of enumeration elements list.

DIVPLAT : Platform Clock Divide Ratio
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0 : DIVPLAT_0

Divide-by-1

End of enumeration elements list.

DIVCORE : Core Clock Divide Ratio
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : DIVCORE_0

Divide-by-1

0x1 : DIVCORE_1

Divide-by-2

0x2 : DIVCORE_2

Divide-by-3

0x3 : DIVCORE_3

Divide-by-4

0x4 : DIVCORE_4

Divide-by-5

0x5 : DIVCORE_5

Divide-by-6

0x6 : DIVCORE_6

Divide-by-7

0x7 : DIVCORE_7

Divide-by-8

0x8 : DIVCORE_8

Divide-by-9

0x9 : DIVCORE_9

Divide-by-10

0xA : DIVCORE_10

Divide-by-11

0xB : DIVCORE_11

Divide-by-12

0xC : DIVCORE_12

Divide-by-13

0xD : DIVCORE_13

Divide-by-14

0xE : DIVCORE_14

Divide-by-15

0xF : DIVCORE_15

Divide-by-16

End of enumeration elements list.

SCS : System Clock Source
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x1 : SCS_1

no description available

0x2 : SCS_2

no description available

0x3 : SCS_3

no description available

0x4 : SCS_4

no description available

0x5 : SCS_5

no description available

0x6 : SCS_6

no description available

End of enumeration elements list.


CLKOUTCNFG

SCG CLKOUT Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKOUTCNFG CLKOUTCNFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOUTSEL

CLKOUTSEL : SCG Clkout Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : CLKOUTSEL_0

no description available

0x1 : CLKOUTSEL_1

no description available

0x2 : CLKOUTSEL_2

no description available

0x3 : CLKOUTSEL_3

no description available

0x4 : CLKOUTSEL_4

no description available

0x5 : CLKOUTSEL_5

no description available

0x6 : CLKOUTSEL_6

no description available

End of enumeration elements list.


SIRCCSR

Slow IRC Control Status Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIRCCSR SIRCCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIRCEN SIRCSTEN SIRCLPEN LPOPO LK SIRCVLD SIRCSEL

SIRCEN : Slow IRC Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SIRCEN_0

Slow IRC is disabled

0x1 : SIRCEN_1

Slow IRC is enabled

End of enumeration elements list.

SIRCSTEN : Slow IRC Stop Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SIRCSTEN_0

Slow IRC is disabled in Stop modes

0x1 : SIRCSTEN_1

Slow IRC is enabled in Stop modes

End of enumeration elements list.

SIRCLPEN : Slow IRC Low Power Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SIRCLPEN_0

Slow IRC is disabled in VLP modes

0x1 : SIRCLPEN_1

Slow IRC is enabled in VLP modes

End of enumeration elements list.

LPOPO : LPO Power Option
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : LPOPO_0

LPO clock is enabled in LLS/VLLSx

0x1 : LPOPO_1

LPO clock is disabled in LLS/VLLSx

End of enumeration elements list.

LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Control Status Register can be written.

0x1 : LK_1

Control Status Register cannot be written.

End of enumeration elements list.

SIRCVLD : Slow IRC Valid
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0 : SIRCVLD_0

Slow IRC is not enabled or clock is not valid

0x1 : SIRCVLD_1

Slow IRC is enabled and output clock is valid

End of enumeration elements list.

SIRCSEL : Slow IRC Selected
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

0 : SIRCSEL_0

Slow IRC is not the system clock source

0x1 : SIRCSEL_1

Slow IRC is the system clock source

End of enumeration elements list.


SIRCDIV

Slow IRC Divide Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIRCDIV SIRCDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIRCDIV1 SIRCDIV2 SIRCDIV3

SIRCDIV1 : Slow IRC Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : SIRCDIV1_0

Output disabled

0x1 : SIRCDIV1_1

Divide by 1

0x2 : SIRCDIV1_2

Divide by 2

0x3 : SIRCDIV1_3

Divide by 4

0x4 : SIRCDIV1_4

Divide by 8

0x5 : SIRCDIV1_5

Divide by 16

0x6 : SIRCDIV1_6

Divide by 32

0x7 : SIRCDIV1_7

Divide by 64

End of enumeration elements list.

SIRCDIV2 : Slow IRC Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : SIRCDIV2_0

Output disabled

0x1 : SIRCDIV2_1

Divide by 1

0x2 : SIRCDIV2_2

Divide by 2

0x3 : SIRCDIV2_3

Divide by 4

0x4 : SIRCDIV2_4

Divide by 8

0x5 : SIRCDIV2_5

Divide by 16

0x6 : SIRCDIV2_6

Divide by 32

0x7 : SIRCDIV2_7

Divide by 64

End of enumeration elements list.

SIRCDIV3 : Slow IRC Clock Divider 3
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : SIRCDIV3_0

Output disabled

0x1 : SIRCDIV3_1

Divide by 1

0x2 : SIRCDIV3_2

Divide by 2

0x3 : SIRCDIV3_3

Divide by 4

0x4 : SIRCDIV3_4

Divide by 8

0x5 : SIRCDIV3_5

Divide by 16

0x6 : SIRCDIV3_6

Divide by 32

0x7 : SIRCDIV3_7

Divide by 64

End of enumeration elements list.


SIRCCFG

Slow IRC Configuration Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIRCCFG SIRCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RANGE

RANGE : Frequency Range
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : RANGE_0

no description available

0x1 : RANGE_1

no description available

End of enumeration elements list.


FIRCCSR

Fast IRC Control Status Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIRCCSR FIRCCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIRCEN FIRCSTEN FIRCLPEN FIRCTREN FIRCTRUP LK FIRCVLD FIRCSEL FIRCERR

FIRCEN : Fast IRC Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : FIRCEN_0

Fast IRC is disabled

0x1 : FIRCEN_1

Fast IRC is enabled

End of enumeration elements list.

FIRCSTEN : Fast IRC Stop Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : FIRCSTEN_0

Fast IRC is disabled in Stop modes.

0x1 : FIRCSTEN_1

Fast IRC is enabled in Stop modes

End of enumeration elements list.

FIRCLPEN : Fast IRC Low Power Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : FIRCLPEN_0

Fast IRC is disabled in VLP modes

0x1 : FIRCLPEN_1

Fast IRC is enabled in VLP modes

End of enumeration elements list.

FIRCTREN : Fast IRC Trim Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : FIRCTREN_0

Disable trimming Fast IRC to an external clock source

0x1 : FIRCTREN_1

Enable trimming Fast IRC to an external clock source

End of enumeration elements list.

FIRCTRUP : Fast IRC Trim Update
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : FIRCTRUP_0

Disable Fast IRC trimming updates

0x1 : FIRCTRUP_1

Enable Fast IRC trimming updates

End of enumeration elements list.

LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Control Status Register can be written.

0x1 : LK_1

Control Status Register cannot be written.

End of enumeration elements list.

FIRCVLD : Fast IRC Valid status
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0 : FIRCVLD_0

Fast IRC is not enabled or clock is not valid.

0x1 : FIRCVLD_1

Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog.

End of enumeration elements list.

FIRCSEL : Fast IRC Selected status
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

0 : FIRCSEL_0

Fast IRC is not the system clock source

0x1 : FIRCSEL_1

Fast IRC is the system clock source

End of enumeration elements list.

FIRCERR : Fast IRC Clock Error
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : FIRCERR_0

Error not detected with the Fast IRC trimming.

0x1 : FIRCERR_1

Error detected with the Fast IRC trimming.

End of enumeration elements list.


FIRCDIV

Fast IRC Divide Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIRCDIV FIRCDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIRCDIV1 FIRCDIV2 FIRCDIV3

FIRCDIV1 : Fast IRC Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FIRCDIV1_0

Output disabled

0x1 : FIRCDIV1_1

Divide by 1

0x2 : FIRCDIV1_2

Divide by 2

0x3 : FIRCDIV1_3

Divide by 4

0x4 : FIRCDIV1_4

Divide by 8

0x5 : FIRCDIV1_5

Divide by 16

0x6 : FIRCDIV1_6

Divide by 32

0x7 : FIRCDIV1_7

Divide by 64

End of enumeration elements list.

FIRCDIV2 : Fast IRC Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : FIRCDIV2_0

Output disabled

0x1 : FIRCDIV2_1

Divide by 1

0x2 : FIRCDIV2_2

Divide by 2

0x3 : FIRCDIV2_3

Divide by 4

0x4 : FIRCDIV2_4

Divide by 8

0x5 : FIRCDIV2_5

Divide by 16

0x6 : FIRCDIV2_6

Divide by 32

0x7 : FIRCDIV2_7

Divide by 64

End of enumeration elements list.

FIRCDIV3 : Fast IRC Clock Divider 3
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : FIRCDIV3_0

Clock disabled

0x1 : FIRCDIV3_1

Divide by 1

0x2 : FIRCDIV3_2

Divide by 2

0x3 : FIRCDIV3_3

Divide by 4

0x4 : FIRCDIV3_4

Divide by 8

0x5 : FIRCDIV3_5

Divide by 16

0x6 : FIRCDIV3_6

Divide by 32

0x7 : FIRCDIV3_7

Divide by 64

End of enumeration elements list.


FIRCCFG

Fast IRC Configuration Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIRCCFG FIRCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RANGE

RANGE : Frequency Range
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : RANGE_0

Fast IRC is trimmed to 48 MHz

0x1 : RANGE_1

Fast IRC is trimmed to 52 MHz

0x2 : RANGE_2

Fast IRC is trimmed to 56 MHz

0x3 : RANGE_3

Fast IRC is trimmed to 60 MHz

End of enumeration elements list.


FIRCTCFG

Fast IRC Trim Configuration Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIRCTCFG FIRCTCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIMSRC TRIMDIV

TRIMSRC : Trim Source
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x2 : TRIMSRC_2

no description available

0x3 : TRIMSRC_3

no description available

End of enumeration elements list.

TRIMDIV : Fast IRC Trim Predivide
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : TRIMDIV_0

Divide by 1

0x1 : TRIMDIV_1

Divide by 128

0x2 : TRIMDIV_2

Divide by 256

0x3 : TRIMDIV_3

Divide by 512

0x4 : TRIMDIV_4

Divide by 1024

0x5 : TRIMDIV_5

Divide by 2048

End of enumeration elements list.


FIRCSTAT

Fast IRC Status Register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIRCSTAT FIRCSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIMFINE TRIMCOAR

TRIMFINE : Trim Fine Status
bits : 0 - 6 (7 bit)
access : read-write

TRIMCOAR : Trim Coarse
bits : 8 - 13 (6 bit)
access : read-write


PARAM

Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PARAM PARAM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKPRES DIVPRES

CLKPRES : Clock Present
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#xxxxxx1x : CLKPRES_2

System OSC (SOSC) is present.

End of enumeration elements list.

DIVPRES : Divider Present
bits : 27 - 31 (5 bit)
access : read-only

Enumeration:

#xxxx1 : DIVPRES_1

System DIVSLOW is present.

End of enumeration elements list.


ROSCCSR

RTC OSC Control Status Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROSCCSR ROSCCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROSCCM ROSCCMRE LK ROSCVLD ROSCSEL ROSCERR

ROSCCM : RTC OSC Clock Monitor
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : ROSCCM_0

RTC OSC Clock Monitor is disabled

0x1 : ROSCCM_1

RTC OSC Clock Monitor is enabled

End of enumeration elements list.

ROSCCMRE : RTC OSC Clock Monitor Reset Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : ROSCCMRE_0

Clock Monitor generates interrupt when error detected

0x1 : ROSCCMRE_1

Clock Monitor generates reset when error detected

End of enumeration elements list.

LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Control Status Register can be written.

0x1 : LK_1

Control Status Register cannot be written.

End of enumeration elements list.

ROSCVLD : RTC OSC Valid
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0 : ROSCVLD_0

RTC OSC is not enabled or clock is not valid

0x1 : ROSCVLD_1

RTC OSC is enabled and output clock is valid

End of enumeration elements list.

ROSCSEL : RTC OSC Selected
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

0 : ROSCSEL_0

RTC OSC is not the system clock source

0x1 : ROSCSEL_1

RTC OSC is the system clock source

End of enumeration elements list.

ROSCERR : RTC OSC Clock Error
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : ROSCERR_0

RTC OSC Clock Monitor is disabled or has not detected an error

0x1 : ROSCERR_1

RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error

End of enumeration elements list.


APLLCSR

Auxiliary PLL Control Status Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLLCSR APLLCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APLLEN APLLSTEN LK APLLVLD APLLSEL

APLLEN : Auxiliary PLL (APLL) Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : APLLEN_0

APLL is disabled

0x1 : APLLEN_1

APLL is enabled

End of enumeration elements list.

APLLSTEN : APLL Stop Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : APLLSTEN_0

APLL is disabled in Stop modes

0x1 : APLLSTEN_1

APLL is enabled in Stop modes

End of enumeration elements list.

LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Control Status Register can be written.

0x1 : LK_1

Control Status Register cannot be written.

End of enumeration elements list.

APLLVLD : APLL Valid
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0 : APLLVLD_0

APLL is not enabled or clock is not valid

0x1 : APLLVLD_1

APLL is enabled and output clock is valid

End of enumeration elements list.

APLLSEL : APLL Selected
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

0 : APLLSEL_0

APLL is not the system clock source

0x1 : APLLSEL_1

APLL is the system clock source

End of enumeration elements list.


APLLDIV

Auxiliary PLL Divide Register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLLDIV APLLDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APLLDIV1 APLLDIV2 APLLDIV3

APLLDIV1 : Auxiliary PLL Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : APLLDIV1_0

Clock disabled

0x1 : APLLDIV1_1

Divide by 1

0x2 : APLLDIV1_2

Divide by 2

0x3 : APLLDIV1_3

Divide by 4

0x4 : APLLDIV1_4

Divide by 8

0x5 : APLLDIV1_5

Divide by 16

0x6 : APLLDIV1_6

Divide by 32

0x7 : APLLDIV1_7

Divide by 64

End of enumeration elements list.

APLLDIV2 : Auxiliary PLL Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : APLLDIV2_0

Clock disabled

0x1 : APLLDIV2_1

Divide by 1

0x2 : APLLDIV2_2

Divide by 2

0x3 : APLLDIV2_3

Divide by 4

0x4 : APLLDIV2_4

Divide by 8

0x5 : APLLDIV2_5

Divide by 16

0x6 : APLLDIV2_6

Divide by 32

0x7 : APLLDIV2_7

Divide by 64

End of enumeration elements list.

APLLDIV3 : Auxiliary PLL Clock Divide 3
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : APLLDIV3_0

Clock disabled

0x1 : APLLDIV3_1

Divide by 1

0x2 : APLLDIV3_2

Divide by 2

0x3 : APLLDIV3_3

Divide by 4

0x4 : APLLDIV3_4

Divide by 8

0x5 : APLLDIV3_5

Divide by 16

0x6 : APLLDIV3_6

Divide by 32

0x7 : APLLDIV3_7

Divide by 64

End of enumeration elements list.


APLLCFG

Auxiliary PLL Configuration Register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLLCFG APLLCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE PLLS PREDIV PFDSEL MULT PLLPOSTDIV1 PLLPOSTDIV2

SOURCE : Clock Source
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SOURCE_0

System OSC

End of enumeration elements list.

PLLS : PLL Select
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PLLS_0

APLL clock selected.

0x1 : PLLS_1

APLL PFD output clock selected

End of enumeration elements list.

PREDIV : PLL Reference Clock Divider
bits : 8 - 10 (3 bit)
access : read-write

PFDSEL : PFD Clock Select
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : PFDSEL_0

PFD0 output clock selected.

0x1 : PFDSEL_1

PFD1 output clock selected.

0x2 : PFDSEL_2

PFD2 output clock selected.

0x3 : PFDSEL_3

PFD3 output clock selected.

End of enumeration elements list.

MULT : Auxiliary PLL Multiplier
bits : 16 - 22 (7 bit)
access : read-write

PLLPOSTDIV1 : Auxiliary PLL Post Clock Divide1Ratio
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : PLLPOSTDIV1_0

Divide-by-1

0x1 : PLLPOSTDIV1_1

Divide-by-2

0x2 : PLLPOSTDIV1_2

Divide-by-3

0x3 : PLLPOSTDIV1_3

Divide-by-4

0x4 : PLLPOSTDIV1_4

Divide-by-5

0x5 : PLLPOSTDIV1_5

Divide-by-6

0x6 : PLLPOSTDIV1_6

Divide-by-7

0x7 : PLLPOSTDIV1_7

Divide-by-8

0x8 : PLLPOSTDIV1_8

Divide-by-9

0x9 : PLLPOSTDIV1_9

Divide-by-10

0xA : PLLPOSTDIV1_10

Divide-by-11

0xB : PLLPOSTDIV1_11

Divide-by-12

0xC : PLLPOSTDIV1_12

Divide-by-13

0xD : PLLPOSTDIV1_13

Divide-by-14

0xE : PLLPOSTDIV1_14

Divide-by-15

0xF : PLLPOSTDIV1_15

Divide-by-16

End of enumeration elements list.

PLLPOSTDIV2 : Auxiliary PLL Post Clock Divide2Ratio
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

0 : PLLPOSTDIV2_0

Divide-by-1

0x1 : PLLPOSTDIV2_1

Divide-by-2

0x2 : PLLPOSTDIV2_2

Divide-by-3

0x3 : PLLPOSTDIV2_3

Divide-by-4

0x4 : PLLPOSTDIV2_4

Divide-by-5

0x5 : PLLPOSTDIV2_5

Divide-by-6

0x6 : PLLPOSTDIV2_6

Divide-by-7

0x7 : PLLPOSTDIV2_7

Divide-by-8

0x8 : PLLPOSTDIV2_8

Divide-by-9

0x9 : PLLPOSTDIV2_9

Divide-by-10

0xA : PLLPOSTDIV2_10

Divide-by-11

0xB : PLLPOSTDIV2_11

Divide-by-12

0xC : PLLPOSTDIV2_12

Divide-by-13

0xD : PLLPOSTDIV2_13

Divide-by-14

0xE : PLLPOSTDIV2_14

Divide-by-15

0xF : PLLPOSTDIV2_15

Divide-by-16

End of enumeration elements list.


APLLPFD

Auxiliary PLL PFD Register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLLPFD APLLPFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PFD0 PFD0_VALID PFD0_CLKGATE PFD1 PFD1_VALID PFD1_CLKGATE PFD2 PFD2_VALID PFD2_CLKGATE PFD3 PFD3_VALID PFD3_CLKGATE

PFD0 : PLL Fractional Divider 0
bits : 0 - 5 (6 bit)
access : read-write

PFD0_VALID : PFD0_VALID
bits : 6 - 6 (1 bit)
access : read-only

PFD0_CLKGATE : PFD0_CLKGATE
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : PFD0_CLKGATE_0

PFD0 clock is not gated.

0x1 : PFD0_CLKGATE_1

PFD0 clock is gated.

End of enumeration elements list.

PFD1 : PLL Fractional Divider 1
bits : 8 - 13 (6 bit)
access : read-write

PFD1_VALID : PFD1_VALID
bits : 14 - 14 (1 bit)
access : read-only

PFD1_CLKGATE : PFD1_CLKGATE
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : PFD1_CLKGATE_0

PFD1 clock is not gated.

0x1 : PFD1_CLKGATE_1

PFD1 clock is gated.

End of enumeration elements list.

PFD2 : PLL Fractional Divider 2
bits : 16 - 21 (6 bit)
access : read-write

PFD2_VALID : PFD2_VALID
bits : 22 - 22 (1 bit)
access : read-only

PFD2_CLKGATE : PFD2_CLKGATE
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : PFD2_CLKGATE_0

PFD2 clock is not gated.

0x1 : PFD2_CLKGATE_1

PFD2 clock is gated.

End of enumeration elements list.

PFD3 : PLL Fractional Divider 3
bits : 24 - 29 (6 bit)
access : read-write

PFD3_VALID : PFD3_VALID
bits : 30 - 30 (1 bit)
access : read-only

PFD3_CLKGATE : PFD3_CLKGATE
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : PFD3_CLKGATE_0

PFD3 clock is not gated.

0x1 : PFD3_CLKGATE_1

PFD3 clock is gated.

End of enumeration elements list.


APLLNUM

Auxiliary PLL Numerator Register
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLLNUM APLLNUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM

NUM : 30-bit numerator of the Auxiliary PLLFractional-Loop divider
bits : 0 - 29 (30 bit)
access : read-write


APLLDENOM

Auxiliary PLL Denominator Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLLDENOM APLLDENOM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DENOM

DENOM : 30-bit denominator of the Auxiliary PLLFractional-Loop divider
bits : 0 - 29 (30 bit)
access : read-write


APLLSS

Auxiliary PLL Spread Spectrum Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLLSS APLLSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP ENABLE STOP

STEP : STOP and STEP together control the modulation depth(maximum frequency change) and modulation frequency. Modulation Depth =(STOP/DENOM)*Fref where DENOM is the DENOM field value in DENOMregister. Modulation Frequency = (STEP/(2*STOP))*Fref, where Fref =24Mhz.
bits : 0 - 14 (15 bit)
access : read-write

ENABLE : Enables the spread spectrummodulation.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

Spectrum modulation is disabled

0x1 : ENABLE_1

Spectrum modulation is enabled

End of enumeration elements list.

STOP : STOP and STEP together control the modulation depth(maximum frequency change) and modulation depth. Modulation Depth =(STOP/DENOM)*Fref where DENOM is the DENOM field value in DENOMregister. Modulation Frequency = (STEP/(2*STOP))*Fref, where Fref =24Mhz.
bits : 16 - 31 (16 bit)
access : read-write


APLLLOCK_CNFG

Auxiliary PLL LOCK Configuration Register
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APLLLOCK_CNFG APLLLOCK_CNFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK_TIME

LOCK_TIME : Configures the number of reference clocks to count beforeAPLL is considered locked and valid.
bits : 0 - 15 (16 bit)
access : read-write


SPLLCSR

System PLL Control Status Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPLLCSR SPLLCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPLLEN SPLLSTEN LK SPLLVLD SPLLSEL SPLLERR

SPLLEN : System PLL Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SPLLEN_0

System PLL is disabled

0x1 : SPLLEN_1

System PLL is enabled

End of enumeration elements list.

SPLLSTEN : System PLL Stop Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SPLLSTEN_0

System PLL is disabled in Stop modes

0x1 : SPLLSTEN_1

System PLL is enabled in Stop modes

End of enumeration elements list.

LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Control Status Register can be written.

0x1 : LK_1

Control Status Register cannot be written.

End of enumeration elements list.

SPLLVLD : System PLL Valid
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0 : SPLLVLD_0

System PLL is not enabled or clock is not valid

0x1 : SPLLVLD_1

System PLL is enabled and output clock is valid

End of enumeration elements list.

SPLLSEL : System PLL Selected
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

0 : SPLLSEL_0

System PLL is not the system clock source

0x1 : SPLLSEL_1

System PLL is the system clock source

End of enumeration elements list.

SPLLERR : System PLL Clock Error
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SPLLERR_0

System PLL Clock Monitor is disabled or has not detected an error

0x1 : SPLLERR_1

System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set.

End of enumeration elements list.


SPLLDIV

System PLL Divide Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPLLDIV SPLLDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPLLDIV1 SPLLDIV2 SPLLDIV3

SPLLDIV1 : System PLL Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : SPLLDIV1_0

Clock disabled

0x1 : SPLLDIV1_1

Divide by 1

0x2 : SPLLDIV1_2

Divide by 2

0x3 : SPLLDIV1_3

Divide by 4

0x4 : SPLLDIV1_4

Divide by 8

0x5 : SPLLDIV1_5

Divide by 16

0x6 : SPLLDIV1_6

Divide by 32

0x7 : SPLLDIV1_7

Divide by 64

End of enumeration elements list.

SPLLDIV2 : System PLL Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : SPLLDIV2_0

Clock disabled

0x1 : SPLLDIV2_1

Divide by 1

0x2 : SPLLDIV2_2

Divide by 2

0x3 : SPLLDIV2_3

Divide by 4

0x4 : SPLLDIV2_4

Divide by 8

0x5 : SPLLDIV2_5

Divide by 16

0x6 : SPLLDIV2_6

Divide by 32

0x7 : SPLLDIV2_7

Divide by 64

End of enumeration elements list.

SPLLDIV3 : System PLL Clock Divide 3
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : SPLLDIV3_0

Clock disabled

0x1 : SPLLDIV3_1

Divide by 1

0x2 : SPLLDIV3_2

Divide by 2

0x3 : SPLLDIV3_3

Divide by 4

0x4 : SPLLDIV3_4

Divide by 8

0x5 : SPLLDIV3_5

Divide by 16

0x6 : SPLLDIV3_6

Divide by 32

0x7 : SPLLDIV3_7

Divide by 64

End of enumeration elements list.


SPLLCFG

System PLL Configuration Register
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPLLCFG SPLLCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE PLLS PREDIV PFDSEL MULT

SOURCE : Clock Source
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SOURCE_0

System OSC (SOSC)

End of enumeration elements list.

PLLS : PLL Select
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PLLS_0

SPLL output clocks selected

0x1 : PLLS_1

SPLL PFD output clock selected.

End of enumeration elements list.

PREDIV : PLL Reference Clock Divider
bits : 8 - 10 (3 bit)
access : read-write

PFDSEL : PFD Clock Select
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : PFDSEL_0

PFD0 output clock selected.

0x1 : PFDSEL_1

PFD1 output clock selected.

0x2 : PFDSEL_2

PFD2 output clock selected.

0x3 : PFDSEL_3

PFD3 output clock selected.

End of enumeration elements list.

MULT : System PLL Multiplier
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x1 : MULT_1

MULT = 15

0x2 : MULT_2

MULT = 16

0x3 : MULT_3

MULT = 20

0x4 : MULT_4

MULT = 22

0x5 : MULT_5

MULT = 25

0x6 : MULT_6

MULT = 30

End of enumeration elements list.


SPLLPFD

System PLL PFD Register
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPLLPFD SPLLPFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PFD0 PFD0_VALID PFD0_CLKGATE PFD1 PFD1_VALID PFD1_CLKGATE PFD2 PFD2_VALID PFD2_CLKGATE PFD3 PFD3_VALID PFD3_CLKGATE

PFD0 : PLL Fractional Divider 0
bits : 0 - 5 (6 bit)
access : read-write

PFD0_VALID : PFD0_VALID
bits : 6 - 6 (1 bit)
access : read-only

PFD0_CLKGATE : PFD0_CLKGATE
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : PFD0_CLKGATE_0

PFD0 clock is not gated.

0x1 : PFD0_CLKGATE_1

PFD0 clock is gated.

End of enumeration elements list.

PFD1 : PLL Fractional Divider 5
bits : 8 - 13 (6 bit)
access : read-write

PFD1_VALID : PFD1_VALID
bits : 14 - 14 (1 bit)
access : read-only

PFD1_CLKGATE : PFD1_CLKGATE
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : PFD1_CLKGATE_0

PFD1 clock is not gated.

0x1 : PFD1_CLKGATE_1

PFD1 clock is gated.

End of enumeration elements list.

PFD2 : PLL Fractional Divider 2
bits : 16 - 21 (6 bit)
access : read-write

PFD2_VALID : PFD2_VALID
bits : 22 - 22 (1 bit)
access : read-only

PFD2_CLKGATE : PFD2_CLKGATE
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : PFD2_CLKGATE_0

PFD2 clock is not gated.

0x1 : PFD2_CLKGATE_1

PFD2 clock is gated.

End of enumeration elements list.

PFD3 : PLL Fractional Divider 3
bits : 24 - 29 (6 bit)
access : read-write

PFD3_VALID : PFD3_VALID
bits : 30 - 30 (1 bit)
access : read-only

PFD3_CLKGATE : PFD3_CLKGATE
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : PFD3_CLKGATE_0

PFD3 clock is not gated.

0x1 : PFD3_CLKGATE_1

PFD3 clock is gated.

End of enumeration elements list.


SPLLLOCK_CNFG

System PLL LOCK Configuration Register
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPLLLOCK_CNFG SPLLLOCK_CNFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK_TIME

LOCK_TIME : Configures the number of reference clocks to count beforeSPLL is considered locked and valid.
bits : 0 - 15 (16 bit)
access : read-write



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