Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected
PMC 0 Version register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : FEATURE_0
Standard features implemented
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
PMC 0 VLPR mode register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARRAYREG : Array Regulator
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ARRAYREG_0
LP Regulator is on
0x1 : ARRAYREG_1
HP Regulator is on
End of enumeration elements list.
COREREG : Core Regulator Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : COREREG_0
LP Regulator is on
0x1 : COREREG_1
HP Regulator is on
End of enumeration elements list.
MONLVD : 1.2V LVD HP Monitor Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MONLVD_0
LP monitor is enabled
0x1 : MONLVD_1
HP monitor is enabled
End of enumeration elements list.
MONHVD : 1.8V HVD HP Monitor Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MONHVD_0
The monitor is disabled
0x1 : MONHVD_1
The monitor is enabled
End of enumeration elements list.
FBGHP : Force HP band-gap
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : FBGHP_0
No action
0x1 : FBGHP_1
Turn on the HP band-gap
End of enumeration elements list.
COREREGVL : Core Regulator Voltage Level
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : COREREGVL_0
Core Voltage Level is 0.596V
0x1 : COREREGVL_1
Core Voltage Level is 0.607V
0x31 : COREREGVL_49
Core Voltage Level is 1.127V
0x32 : COREREGVL_50
Core Voltage Level is 1.138V
End of enumeration elements list.
RBBEN : Reverse Back Bias Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : RBBEN_0
RBB is disabled
0x1 : RBBEN_1
RBB is enabled
End of enumeration elements list.
PMC 0 STOP mode register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREREGVL : Core Regulator Voltage Level
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : COREREGVL_0
Core Voltage Level is 0.596V
0x1 : COREREGVL_1
Core Voltage Level is 0.607V
0x31 : COREREGVL_49
Core Voltage Level is 1.127V
0x32 : COREREGVL_50
Core Voltage Level is 1.138V
End of enumeration elements list.
PMC 0 VLPS mode register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARRAYREG : Array Regulator
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ARRAYREG_0
LP Regulator is on
0x1 : ARRAYREG_1
HP Regulator is on
End of enumeration elements list.
COREREG : Core Regulator
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : COREREG_0
LP Regulator is on
0x1 : COREREG_1
HP Regulator is on
End of enumeration elements list.
MONLVD : 1.2V LVD HP Monitor Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MONLVD_0
LP monitor is enabled
0x1 : MONLVD_1
HP monitor is enabled
End of enumeration elements list.
MONHVD : 1.8V HVD HP Monitor Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MONHVD_0
The monitor is disabled
0x1 : MONHVD_1
The monitor is enabled
End of enumeration elements list.
FBGHP : Force HP band-gap
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : FBGHP_0
No action
0x1 : FBGHP_1
Turn on the HP band-gap
End of enumeration elements list.
COREREGVL : Core Regulator Voltage Level
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : COREREGVL_0
Core Voltage Level is 0.596V
0x1 : COREREGVL_1
Core Voltage Level is 0.607V
0x31 : COREREGVL_49
Core Voltage Level is 1.127V
0x32 : COREREGVL_50
Core Voltage Level is 1.138V
End of enumeration elements list.
RBBEN : Reverse Back Bias Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : RBBEN_0
RBB is disabled
0x1 : RBBEN_1
RBB is enabled
End of enumeration elements list.
PMC 0 LLS mode register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARRAYREG : Array Regulator
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ARRAYREG_0
LP Regulator is on
0x1 : ARRAYREG_1
HP Regulator is on
End of enumeration elements list.
COREREG : Core Regulator
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : COREREG_0
LP Regulator is on
0x1 : COREREG_1
HP Regulator is on
End of enumeration elements list.
MONLVD : 1.2V LVD HP Monitor Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MONLVD_0
LP monitor is enabled
0x1 : MONLVD_1
HP monitor is enabled
End of enumeration elements list.
MONHVD : 1.8V HVD HP Monitor Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MONHVD_0
The monitor is disabled
0x1 : MONHVD_1
The monitor is enabled
End of enumeration elements list.
FBGHP : Force HP band-gap
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : FBGHP_0
No action
0x1 : FBGHP_1
Turn on the HP band-gap
End of enumeration elements list.
COREREGVL : Core Regulator Voltage Level
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : COREREGVL_0
Core Voltage Level is 0.596V
0x1 : COREREGVL_1
Core Voltage Level is 0.607V
0x31 : COREREGVL_49
Core Voltage Level is 1.127V
0x32 : COREREGVL_50
Core Voltage Level is 1.138V
End of enumeration elements list.
RBBEN : Reverse Back Bias Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : RBBEN_0
RBB is disabled
0x1 : RBBEN_1
RBB is enabled
End of enumeration elements list.
PMC 0 VLLS mode register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARRAYREG : Array Regulator
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ARRAYREG_0
Regulator is off
0x2 : ARRAYREG_2
LP Regulator is on
0x3 : ARRAYREG_3
HP Regulator is on
End of enumeration elements list.
MONLVD : 1.2V LVD HP Monitor Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MONLVD_0
LP monitor is enabled
0x1 : MONLVD_1
HP monitor is enabled
End of enumeration elements list.
MONHVD : 1.8V HVD HP Monitor Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MONHVD_0
The monitor is disabled
0x1 : MONHVD_1
The monitor is enabled
End of enumeration elements list.
FBGHP : Force HP band-gap
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : FBGHP_0
No action
0x1 : FBGHP_1
Turn on the HP band-gap
End of enumeration elements list.
PMC 0 Status register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LVDF : 1.2V Low-Voltage Detector Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : LVDF_0
Low-voltage event was not detected by the 1.2V LVD monitor in the PMC 0
0x1 : LVDF_1
Low-voltage event was detected by the 1.2V LVD monitor in the PMC 0
End of enumeration elements list.
LVDV : 1.2V Low-Voltage Detector Value
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : LVDV_0
Low-voltage event was not detected by the 1.2V LVD monitor in the PMC 0
0x1 : LVDV_1
Low-voltage event was detected by the 1.2V LVD monitor in the PMC 0
End of enumeration elements list.
HVDF : 1.8V High-Voltage Detector Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : HVDF_0
High-voltage event was not detected by the 1.8V HVD monitor in the PMC 0
0x1 : HVDF_1
High-voltage event was detected by the 1.8V HVD monitor in the PMC 0
End of enumeration elements list.
HVDV : 1.8V High-Voltage Detector Value
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : HVDV_0
High-voltage event was not detected by the 1.8V HVD monitor in the PMC 0
0x1 : HVDV_1
High-voltage event was detected by the 1.8V HVD monitor in the PMC 0
End of enumeration elements list.
COREVLF : Core Regulator Voltage Level Flag
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : COREVLF_0
Core Regulator Voltage Level is stable
0x1 : COREVLF_1
Core Regulator Voltage Level is changing
End of enumeration elements list.
SRAMF : SRAM Flag
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : SRAMF_0
No change request in the SRAMs.
0x1 : SRAMF_1
A change mode request is being processed in the SRAMs.
End of enumeration elements list.
PMC1VSRC : PMC 1 Voltage Source
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PMC1VSRC_0
The internal LDO supplies the PMC 1, the PMC 1's LVD/HVD sense point is at the supply of the LDO regulator.
0x1 : PMC1VSRC_1
The external PMIC supplies the PMC 1; the PMC 1's LVD/HVD sense point is at the pin connected to the PMIC.
End of enumeration elements list.
PMC 0 Control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDIE : 1.2V Low-Voltage Detector Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LVDIE_0
1.2V low-voltage detector interrupt is disabled
0x1 : LVDIE_1
1.2V low-voltage detector interrupt is enabled
End of enumeration elements list.
LVDACK : 1.2V Low-Voltage Detector Acknowledge
bits : 1 - 1 (1 bit)
access : write-only
HVDIE : 1.8V High-Voltage Detector Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : HVDIE_0
1.8V high-voltage detector interrupt is disabled
0x1 : HVDIE_1
1.8V high-voltage detector interrupt is enabled
End of enumeration elements list.
HVDACK : 1.8V High-Voltage Detector Acknowledge
bits : 3 - 3 (1 bit)
access : write-only
LVDRE : 1.2V Low-Voltage Detector Reset Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LVDRE_0
1.2V low-voltage detector reset is disabled
0x1 : LVDRE_1
1.2V low-voltage detector reset is enabled
End of enumeration elements list.
HVDRE : 1.8V High-Voltage Detector Reset Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : HVDRE_0
1.8V high-voltage detector reset is disabled
0x1 : HVDRE_1
1.8V high-voltage detector reset is enabled
End of enumeration elements list.
ISOACK : Isolation Acknowledge
bits : 14 - 14 (1 bit)
access : write-only
PMC1ON : PMC 1 Power On
bits : 24 - 24 (1 bit)
access : read-writeOnce
LDOOKDIS : Disable to Wait LDO OK Signal
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LDOOKDIS_0
The PMC will wait the signal OK from LDO Regulator
0x1 : LDOOKDIS_1
The PMC will not wait the signal OK from LDO Regulator
End of enumeration elements list.
LDOEN : PMC 1 LDO Regulator Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LDOEN_0
PMC 1 LDO Regulator is disabled.
0x1 : LDOEN_1
PMC 1 LDO Regulator is enabled.
End of enumeration elements list.
PMC 0 Analog Core Control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFEN : Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : BUFEN_0
Analog buffer is disabled.
0x1 : BUFEN_1
Analog buffer is enabled.
End of enumeration elements list.
BUFFLIP : Buffer Flip
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : BUFFLIP_0
Buffer input not flipped.
0x1 : BUFFLIP_1
Buffer input flipped.
End of enumeration elements list.
BUFSEL : Buffer Selection
bits : 2 - 3 (2 bit)
access : read-write
TSENSEN : Temperature Sensor Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TSENSEN_0
The temperature sensor is disabled.
0x1 : TSENSEN_1
The temperature sensor is enabled.
End of enumeration elements list.
TSENSM : Temperature Sensor Mode
bits : 12 - 14 (3 bit)
access : read-write
SWRBBEN : PMC 1 Switch RBB Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SWRBBEN_0
Switch RBB is disabled.
0x1 : SWRBBEN_1
Switch RBB is enabled.
End of enumeration elements list.
OSC1KHZSEL : 1KHz Oscillator Select
bits : 20 - 22 (3 bit)
access : read-write
CORECTRL : Controls to Analog PMC Core
bits : 24 - 31 (8 bit)
access : read-write
PMC 0 Biasing Control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBBNLEVEL : RBB N-Well Voltage Level
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : RBBNLEVEL_0
Voltage level at 0.5V.
0x1 : RBBNLEVEL_1
Voltage level at 0.6V.
0x2 : RBBNLEVEL_2
Voltage level at 0.7V.
0x3 : RBBNLEVEL_3
Voltage level at 0.8V.
0x4 : RBBNLEVEL_4
Voltage level at 0.9V.
0x5 : RBBNLEVEL_5
Voltage level at 1.0V.
0x6 : RBBNLEVEL_6
Voltage level at 1.1V.
0x7 : RBBNLEVEL_7
Voltage level at 1.2V.
0x8 : RBBNLEVEL_8
Voltage level at 1.3V.
End of enumeration elements list.
RBBPLEVEL : RBB P-Well Voltage Level
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RBBPLEVEL_0
Voltage level at -0.5V.
0x1 : RBBPLEVEL_1
Voltage level at -0.6V.
0x2 : RBBPLEVEL_2
Voltage level at -0.7V.
0x3 : RBBPLEVEL_3
Voltage level at -0.8V.
0x4 : RBBPLEVEL_4
Voltage level at -0.9V.
0x5 : RBBPLEVEL_5
Voltage level at -1.0V.
0x6 : RBBPLEVEL_6
Voltage level at -1.1V.
0x7 : RBBPLEVEL_7
Voltage level at -1.2V.
0x8 : RBBPLEVEL_8
Voltage level at -1.3V.
End of enumeration elements list.
RBBPDDIS : RBB Pull-down Disable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : RBBPDDIS_0
RBB pull-down is enabled.
0x1 : RBBPDDIS_1
RBB pull-down is disabled.
End of enumeration elements list.
FBBNLEVEL : FBB N-Well Voltage Level
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : FBBNLEVEL_0
No BIAS condition.
0x1 : FBBNLEVEL_1
Voltage level at -50mV.
0x2 : FBBNLEVEL_2
Voltage level at -150mV.
0x3 : FBBNLEVEL_3
Voltage level at -100mV.
0x4 : FBBNLEVEL_4
Voltage level at -350mV.
0x5 : FBBNLEVEL_5
Voltage level at -300mV.
0x6 : FBBNLEVEL_6
Voltage level at -200mV.
0x7 : FBBNLEVEL_7
Voltage level at -250mV.
End of enumeration elements list.
FBBPLEVEL : FBB P-Well Voltage Level
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : FBBPLEVEL_0
No BIAS condition.
0x1 : FBBPLEVEL_1
Voltage level at 50mV.
0x2 : FBBPLEVEL_2
Voltage level at 150mV.
0x3 : FBBPLEVEL_3
Voltage level at 100mV.
0x4 : FBBPLEVEL_4
Voltage level at 350mV.
0x5 : FBBPLEVEL_5
Voltage level at 300mV.
0x6 : FBBPLEVEL_6
Voltage level at 200mV.
0x7 : FBBPLEVEL_7
Voltage level at 250mV.
End of enumeration elements list.
PMC 0 Power Mode Status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PMC0CURRPM : PMC 0 Current Power Mode
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : PMC0CURRPM_0
HSRUN Mode
0x1 : PMC0CURRPM_1
RUN Mode
0x2 : PMC0CURRPM_2
STOP Mode
0x3 : PMC0CURRPM_3
VLPR Mode
0x4 : PMC0CURRPM_4
VLPS Mode
0x5 : PMC0CURRPM_5
LLS Mode
0x6 : PMC0CURRPM_6
VLLS Mode
End of enumeration elements list.
PMC0TRANPM : PMC 0 Power Mode transition status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : PMC0TRANPM_0
PMC 0 is not in a power mode transition.
0x1 : PMC0TRANPM_1
PMC 0 is in a power mode transition.
End of enumeration elements list.
PMC1CURRPM : PMC 1 Current Power Mode
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0 : PMC1CURRPM_0
HSRUN Mode
0x1 : PMC1CURRPM_1
RUN Mode
0x2 : PMC1CURRPM_2
STOP Mode
0x3 : PMC1CURRPM_3
VLPR Mode
0x4 : PMC1CURRPM_4
VLPS Mode
0x5 : PMC1CURRPM_5
LLS Mode
0x6 : PMC1CURRPM_6
VLLS Mode
End of enumeration elements list.
PMC1TRANPM : PMC 1 Power Mode transition status
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : PMC1TRANPM_0
PMC 1 is not in a power mode transition.
0x1 : PMC1TRANPM_1
PMC 1 is in a power mode transition.
End of enumeration elements list.
PMC 0 SRAMs Control 0 register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_PD : PMC 0 SRAM Bank Power Down
bits : 0 - 4 (5 bit)
access : read-write
PMC 0 SRAMs Control 1 register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_PDS : PMC 0 SRAM Bank Power Down in Stop Modes
bits : 0 - 4 (5 bit)
access : read-write
PMC 0 SRAMs Control 2 register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_STDY : PMC 0 SRAM Bank in Standby Mode
bits : 0 - 4 (5 bit)
access : read-write
PMC 0 HSRUN mode register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREREGVL : Core Regulator Voltage Level
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : COREREGVL_0
Core Voltage Level is 0.596V
0x1 : COREREGVL_1
Core Voltage Level is 0.607V
0x31 : COREREGVL_49
Core Voltage Level is 1.127V
0x32 : COREREGVL_50
Core Voltage Level is 1.138V
End of enumeration elements list.
FBBEN : Forward Back Bias Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : FBBEN_0
FBB is disabled
0x1 : FBBEN_1
FBB is enabled
End of enumeration elements list.
PMC 0 RUN mode register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREREGVL : Core Regulator Voltage Level
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : COREREGVL_0
Core Voltage Level is 0.596V
0x1 : COREREGVL_1
Core Voltage Level is 0.607V
0x31 : COREREGVL_49
Core Voltage Level is 1.127V
0x32 : COREREGVL_50
Core Voltage Level is 1.138V
End of enumeration elements list.
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