Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xE4 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : FEATURE_0
Standard feature set.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
SAI Transmit Configuration 2 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Bit Clock Divide
bits : 0 - 7 (8 bit)
access : read-write
BCD : Bit Clock Direction
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : BCD_0
Bit clock is generated externally in Slave mode.
0x1 : BCD_1
Bit clock is generated internally in Master mode.
End of enumeration elements list.
BCP : Bit Clock Polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : BCP_0
Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
0x1 : BCP_1
Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
End of enumeration elements list.
MSEL : MCLK Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : MSEL_0
Bus Clock selected.
0x1 : MSEL_1
Master Clock (MCLK) 1 option selected.
0x2 : MSEL_2
Master Clock (MCLK) 2 option selected.
0x3 : MSEL_3
Master Clock (MCLK) 3 option selected.
End of enumeration elements list.
BCI : Bit Clock Input
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : BCI_0
No effect.
0x1 : BCI_1
Internal logic is clocked as if bit clock was externally generated.
End of enumeration elements list.
BCS : Bit Clock Swap
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : BCS_0
Use the normal bit clock source.
0x1 : BCS_1
Swap the bit clock source.
End of enumeration elements list.
SYNC : Synchronous Mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : SYNC_0
Asynchronous mode.
0x1 : SYNC_1
Synchronous with receiver.
End of enumeration elements list.
SAI Transmit FIFO Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WCP_0
No effect.
0x1 : WCP_1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Transmit Data Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit Configuration 3 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDFL : Word Flag Configuration
bits : 0 - 4 (5 bit)
access : read-write
TCE : Transmit Channel Enable
bits : 16 - 23 (8 bit)
access : read-write
CFR : Channel FIFO Reset
bits : 24 - 31 (8 bit)
access : write-only
SAI Receive Data Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Transmit Data Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit FIFO Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WCP_0
No effect.
0x1 : WCP_1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Transmit Configuration 4 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSD : Frame Sync Direction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FSD_0
Frame sync is generated externally in Slave mode.
0x1 : FSD_1
Frame sync is generated internally in Master mode.
End of enumeration elements list.
FSP : Frame Sync Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FSP_0
Frame sync is active high.
0x1 : FSP_1
Frame sync is active low.
End of enumeration elements list.
ONDEM : On Demand Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ONDEM_0
Internal frame sync is generated continuously.
0x1 : ONDEM_1
Internal frame sync is generated when the FIFO warning flag is clear.
End of enumeration elements list.
FSE : Frame Sync Early
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FSE_0
Frame sync asserts with the first bit of the frame.
0x1 : FSE_1
Frame sync asserts one bit before the first bit of the frame.
End of enumeration elements list.
MF : MSB First
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MF_0
LSB is transmitted first.
0x1 : MF_1
MSB is transmitted first.
End of enumeration elements list.
CHMOD : Channel Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : CHMOD_0
TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
0x1 : CHMOD_1
Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
End of enumeration elements list.
SYWD : Sync Width
bits : 8 - 12 (5 bit)
access : read-write
FRSZ : Frame size
bits : 16 - 20 (5 bit)
access : read-write
FPACK : FIFO Packing Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : FPACK_0
FIFO packing is disabled
0x2 : FPACK_2
8-bit FIFO packing is enabled
0x3 : FPACK_3
16-bit FIFO packing is enabled
End of enumeration elements list.
FCOMB : FIFO Combine Mode
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : FCOMB_0
FIFO combine mode disabled.
0x1 : FCOMB_1
FIFO combine mode enabled on FIFO reads (from transmit shift registers).
0x2 : FCOMB_2
FIFO combine mode enabled on FIFO writes (by software).
0x3 : FCOMB_3
FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
End of enumeration elements list.
FCONT : FIFO Continue on Error
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : FCONT_0
On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
0x1 : FCONT_1
On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
End of enumeration elements list.
SAI Receive FIFO Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RCP_0
No effect.
0x1 : RCP_1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
SAI Transmit Data Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit FIFO Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WCP_0
No effect.
0x1 : WCP_1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Transmit Configuration 5 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBT : First Bit Shifted
bits : 8 - 12 (5 bit)
access : read-write
W0W : Word 0 Width
bits : 16 - 20 (5 bit)
access : read-write
WNW : Word N Width
bits : 24 - 28 (5 bit)
access : read-write
SAI Receive Data Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Transmit FIFO Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WCP_0
No effect.
0x1 : WCP_1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Receive FIFO Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RCP_0
No effect.
0x1 : RCP_1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
SAI Transmit FIFO Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WCP_0
No effect.
0x1 : WCP_1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Receive Data Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Transmit FIFO Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WCP_0
No effect.
0x1 : WCP_1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Receive FIFO Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RCP_0
No effect.
0x1 : RCP_1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
SAI Receive Data Register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RCP_0
No effect.
0x1 : RCP_1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
SAI Receive Data Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATALINE : Number of Datalines
bits : 0 - 3 (4 bit)
access : read-only
FIFO : FIFO Size
bits : 8 - 11 (4 bit)
access : read-only
FRAME : Frame Size
bits : 16 - 19 (4 bit)
access : read-only
SAI Transmit Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Receive Data Register
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RCP_0
No effect.
0x1 : RCP_1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
SAI Receive Data Register
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RCP_0
No effect.
0x1 : RCP_1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
SAI Transmit Mask Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWM : Transmit Word Mask
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : TWM_0
Word N is enabled.
0x1 : TWM_1
Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
End of enumeration elements list.
SAI Receive Data Register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Transmit Data Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Receive FIFO Register
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RCP_0
No effect.
0x1 : RCP_1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RCP_0
No effect.
0x1 : RCP_1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
SAI Transmit Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDE : FIFO Request DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FRDE_0
Disables the DMA request.
0x1 : FRDE_1
Enables the DMA request.
End of enumeration elements list.
FWDE : FIFO Warning DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FWDE_0
Disables the DMA request.
0x1 : FWDE_1
Enables the DMA request.
End of enumeration elements list.
FRIE : FIFO Request Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FRIE_0
Disables the interrupt.
0x1 : FRIE_1
Enables the interrupt.
End of enumeration elements list.
FWIE : FIFO Warning Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : FWIE_0
Disables the interrupt.
0x1 : FWIE_1
Enables the interrupt.
End of enumeration elements list.
FEIE : FIFO Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : FEIE_0
Disables the interrupt.
0x1 : FEIE_1
Enables the interrupt.
End of enumeration elements list.
SEIE : Sync Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SEIE_0
Disables interrupt.
0x1 : SEIE_1
Enables interrupt.
End of enumeration elements list.
WSIE : Word Start Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : WSIE_0
Disables interrupt.
0x1 : WSIE_1
Enables interrupt.
End of enumeration elements list.
FRF : FIFO Request Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : FRF_0
Transmit FIFO watermark has not been reached.
0x1 : FRF_1
Transmit FIFO watermark has been reached.
End of enumeration elements list.
FWF : FIFO Warning Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : FWF_0
No enabled transmit FIFO is empty.
0x1 : FWF_1
Enabled transmit FIFO is empty.
End of enumeration elements list.
FEF : FIFO Error Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : FEF_0
Transmit underrun not detected.
0x1 : FEF_1
Transmit underrun detected.
End of enumeration elements list.
SEF : Sync Error Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SEF_0
Sync error not detected.
0x1 : SEF_1
Frame sync error detected.
End of enumeration elements list.
WSF : Word Start Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : WSF_0
Start of word not detected.
0x1 : WSF_1
Start of word detected.
End of enumeration elements list.
SR : Software Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SR_0
No effect.
0x1 : SR_1
Software reset.
End of enumeration elements list.
FR : FIFO Reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
0 : FR_0
No effect.
0x1 : FR_1
FIFO reset.
End of enumeration elements list.
BCE : Bit Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : BCE_0
Transmit bit clock is disabled.
0x1 : BCE_1
Transmit bit clock is enabled.
End of enumeration elements list.
DBGE : Debug Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DBGE_0
Transmitter is disabled in Debug mode, after completing the current frame.
0x1 : DBGE_1
Transmitter is enabled in Debug mode.
End of enumeration elements list.
TE : Transmitter Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : TE_0
Transmitter is disabled.
0x1 : TE_1
Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
End of enumeration elements list.
SAI Transmit FIFO Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WCP_0
No effect.
0x1 : WCP_1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Receive Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDE : FIFO Request DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FRDE_0
Disables the DMA request.
0x1 : FRDE_1
Enables the DMA request.
End of enumeration elements list.
FWDE : FIFO Warning DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FWDE_0
Disables the DMA request.
0x1 : FWDE_1
Enables the DMA request.
End of enumeration elements list.
FRIE : FIFO Request Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FRIE_0
Disables the interrupt.
0x1 : FRIE_1
Enables the interrupt.
End of enumeration elements list.
FWIE : FIFO Warning Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : FWIE_0
Disables the interrupt.
0x1 : FWIE_1
Enables the interrupt.
End of enumeration elements list.
FEIE : FIFO Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : FEIE_0
Disables the interrupt.
0x1 : FEIE_1
Enables the interrupt.
End of enumeration elements list.
SEIE : Sync Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SEIE_0
Disables interrupt.
0x1 : SEIE_1
Enables interrupt.
End of enumeration elements list.
WSIE : Word Start Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : WSIE_0
Disables interrupt.
0x1 : WSIE_1
Enables interrupt.
End of enumeration elements list.
FRF : FIFO Request Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : FRF_0
Receive FIFO watermark not reached.
0x1 : FRF_1
Receive FIFO watermark has been reached.
End of enumeration elements list.
FWF : FIFO Warning Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : FWF_0
No enabled receive FIFO is full.
0x1 : FWF_1
Enabled receive FIFO is full.
End of enumeration elements list.
FEF : FIFO Error Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : FEF_0
Receive overflow not detected.
0x1 : FEF_1
Receive overflow detected.
End of enumeration elements list.
SEF : Sync Error Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SEF_0
Sync error not detected.
0x1 : SEF_1
Frame sync error detected.
End of enumeration elements list.
WSF : Word Start Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : WSF_0
Start of word not detected.
0x1 : WSF_1
Start of word detected.
End of enumeration elements list.
SR : Software Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SR_0
No effect.
0x1 : SR_1
Software reset.
End of enumeration elements list.
FR : FIFO Reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
0 : FR_0
No effect.
0x1 : FR_1
FIFO reset.
End of enumeration elements list.
BCE : Bit Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : BCE_0
Receive bit clock is disabled.
0x1 : BCE_1
Receive bit clock is enabled.
End of enumeration elements list.
DBGE : Debug Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DBGE_0
Receiver is disabled in Debug mode, after completing the current frame.
0x1 : DBGE_1
Receiver is enabled in Debug mode.
End of enumeration elements list.
RE : Receiver Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : RE_0
Receiver is disabled.
0x1 : RE_1
Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
End of enumeration elements list.
SAI Transmit Data Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Receive Configuration 1 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFW : Receive FIFO Watermark
bits : 0 - 6 (7 bit)
access : read-write
SAI Receive Configuration 2 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Bit Clock Divide
bits : 0 - 7 (8 bit)
access : read-write
BCD : Bit Clock Direction
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : BCD_0
Bit clock is generated externally in Slave mode.
0x1 : BCD_1
Bit clock is generated internally in Master mode.
End of enumeration elements list.
BCP : Bit Clock Polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : BCP_0
Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
0x1 : BCP_1
Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
End of enumeration elements list.
MSEL : MCLK Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : MSEL_0
Bus Clock selected.
0x1 : MSEL_1
Master Clock (MCLK) 1 option selected.
0x2 : MSEL_2
Master Clock (MCLK) 2 option selected.
0x3 : MSEL_3
Master Clock (MCLK) 3 option selected.
End of enumeration elements list.
BCI : Bit Clock Input
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : BCI_0
No effect.
0x1 : BCI_1
Internal logic is clocked as if bit clock was externally generated.
End of enumeration elements list.
BCS : Bit Clock Swap
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : BCS_0
Use the normal bit clock source.
0x1 : BCS_1
Swap the bit clock source.
End of enumeration elements list.
SYNC : Synchronous Mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : SYNC_0
Asynchronous mode.
0x1 : SYNC_1
Synchronous with transmitter.
End of enumeration elements list.
SAI Receive Configuration 3 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDFL : Word Flag Configuration
bits : 0 - 4 (5 bit)
access : read-write
RCE : Receive Channel Enable
bits : 16 - 23 (8 bit)
access : read-write
CFR : Channel FIFO Reset
bits : 24 - 31 (8 bit)
access : write-only
SAI Receive Configuration 4 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSD : Frame Sync Direction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FSD_0
Frame Sync is generated externally in Slave mode.
0x1 : FSD_1
Frame Sync is generated internally in Master mode.
End of enumeration elements list.
FSP : Frame Sync Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FSP_0
Frame sync is active high.
0x1 : FSP_1
Frame sync is active low.
End of enumeration elements list.
ONDEM : On Demand Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ONDEM_0
Internal frame sync is generated continuously.
0x1 : ONDEM_1
Internal frame sync is generated when the FIFO warning flag is clear.
End of enumeration elements list.
FSE : Frame Sync Early
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FSE_0
Frame sync asserts with the first bit of the frame.
0x1 : FSE_1
Frame sync asserts one bit before the first bit of the frame.
End of enumeration elements list.
MF : MSB First
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MF_0
LSB is received first.
0x1 : MF_1
MSB is received first.
End of enumeration elements list.
SYWD : Sync Width
bits : 8 - 12 (5 bit)
access : read-write
FRSZ : Frame Size
bits : 16 - 20 (5 bit)
access : read-write
FPACK : FIFO Packing Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : FPACK_0
FIFO packing is disabled
0x2 : FPACK_2
8-bit FIFO packing is enabled
0x3 : FPACK_3
16-bit FIFO packing is enabled
End of enumeration elements list.
FCOMB : FIFO Combine Mode
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : FCOMB_0
FIFO combine mode disabled.
0x1 : FCOMB_1
FIFO combine mode enabled on FIFO writes (from receive shift registers).
0x2 : FCOMB_2
FIFO combine mode enabled on FIFO reads (by software).
0x3 : FCOMB_3
FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
End of enumeration elements list.
FCONT : FIFO Continue on Error
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : FCONT_0
On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
0x1 : FCONT_1
On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
End of enumeration elements list.
SAI Receive Configuration 5 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBT : First Bit Shifted
bits : 8 - 12 (5 bit)
access : read-write
W0W : Word 0 Width
bits : 16 - 20 (5 bit)
access : read-write
WNW : Word N Width
bits : 24 - 28 (5 bit)
access : read-write
SAI Transmit Data Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit Configuration 1 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFW : Transmit FIFO Watermark
bits : 0 - 6 (7 bit)
access : read-write
SAI Transmit FIFO Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 7 (8 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 23 (8 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WCP_0
No effect.
0x1 : WCP_1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Receive Mask Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWM : Receive Word Mask
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : RWM_0
Word N is enabled.
0x1 : RWM_1
Word N is masked.
End of enumeration elements list.
SAI Transmit Data Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
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