\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C0 byte (0x0)
mem_usage : registers
protection : not protected
Arm platform Channel 0 Pointer
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MC0PTR : Channel 0 Pointer contains the 32-bit address, in Arm platform memory, of channel 0 control block (the boot channel)
bits : 0 - 31 (32 bit)
access : read-write
Channel Event Override
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EO : The Channel Event Override register contains the 32 EO[i] bits
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel BP Override
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DO : This register is reserved
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : DO_0
- Reserved
0x1 : DO_1
- Reset value.
End of enumeration elements list.
Channel Priority Registers
address_offset : 0x1420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x1564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0x16AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x17F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Arm platform Override
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HO : The Channel Arm platform Override register contains the 32 HO[i] bits
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x1948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0x1A9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x1BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Event Pending
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP : The Channel Event Pending register contains the 32 EP[i] bits
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x1D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0x1EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0x2014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0x217C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x22E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Reset Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESET : When set, this bit causes the SDMA to be held in a software reset
bits : 0 - 0 (1 bit)
access : read-only
RESCHED : When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction
bits : 1 - 1 (1 bit)
access : read-only
Channel Priority Registers
address_offset : 0x2458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0x25CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x2744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
DMA Request Error Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHNERR : This register is used by the SDMA to warn the Arm platform when an incoming DMA request was detected and it triggers a channel that is already pending or being serviced
bits : 0 - 31 (32 bit)
access : read-only
Channel Enable RAM
address_offset : 0x2864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x28C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Arm platform Interrupt Mask
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIMASK : The Interrupt Mask Register contains 32 interrupt generation mask bits
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x2CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x2F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Schedule Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CCR : The Current Channel Register indicates the number of the channel that is being executed by the SDMA
bits : 0 - 3 (4 bit)
access : read-only
CCP : The Current Channel Priority indicates the priority of the current active channel
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : CCP_0
No running channel
0x1 : CCP_1
Active channel priority
End of enumeration elements list.
NCR : The Next Channel Register indicates the number of the next scheduled pending channel with the highest priority
bits : 8 - 12 (5 bit)
access : read-only
NCP : The Next Channel Priority gives the next pending channel priority
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
0 : NCP_0
No running channel
0x1 : NCP_1
Active channel priority
End of enumeration elements list.
Channel Priority Registers
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x319C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x33F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
DMA Request Error Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHNERR : This register is the same as EVTERR, except reading it does not clear its contents
bits : 0 - 31 (32 bit)
access : read-only
Channel Enable RAM
address_offset : 0x3650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSM : Selects the Context Switch Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : CSM_0
static
0x1 : CSM_1
dynamic low power
0x2 : CSM_2
dynamic with no loop
0x3 : CSM_3
dynamic
End of enumeration elements list.
ACR : Arm platform DMA / SDMA Core Clock Ratio
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ACR_0
Arm platform DMA interface frequency equals twice core frequency
0x1 : ACR_1
Arm platform DMA interface frequency equals core frequency
End of enumeration elements list.
RTDOBS : Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power consumption
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : RTDOBS_0
RTD pins disabled
0x1 : RTDOBS_1
RTD pins enabled
End of enumeration elements list.
DSPDMA : This bit's function is reserved and should be configured as zero.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DSPDMA_0
- Reset Value
0x1 : DSPDMA_1
- Reserved
End of enumeration elements list.
Channel Enable RAM
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
SDMA LOCK
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts and through the OnCE interface under Arm platform control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
LOCK disengaged.
0x1 : LOCK_1
LOCK enabled.
End of enumeration elements list.
SRESET_LOCK_CLR : The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing to the RESET register
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRESET_LOCK_CLR_0
Software Reset does not clear the LOCK bit.
0x1 : SRESET_LOCK_CLR_1
Software Reset clears the LOCK bit.
End of enumeration elements list.
Channel Enable RAM
address_offset : 0x3D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Interrupts
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HI : The Arm platform Interrupts register contains the 32 HI[i] bits
bits : 0 - 31 (32 bit)
access : read-write
OnCE Enable
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENB : The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers are accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the Arm platform through the addresses described, as follows
bits : 0 - 0 (1 bit)
access : read-write
Channel Enable RAM
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x4258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
OnCE Data Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data register of the OnCE JTAG controller
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x44CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x4744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
OnCE Instruction Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INSTR : Instruction register of the OnCE JTAG controller
bits : 0 - 15 (16 bit)
access : read-write
Channel Enable RAM
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
OnCE Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECDR : Event Cell Debug Request
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : ECDR_0
1 matched addra_cond
0x1 : ECDR_1
1 matched addrb_cond
0x2 : ECDR_2
1 matched data_cond
End of enumeration elements list.
MST : This flag is raised when the OnCE is controlled from the Arm platform peripheral interface.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : MST_0
The JTAG interface controls the OnCE.
0x1 : MST_1
The Arm platform peripheral interface controls the OnCE.
End of enumeration elements list.
SWB : This flag is raised when the SDMA has entered debug mode after a software breakpoint.
bits : 8 - 8 (1 bit)
access : read-only
ODR : This flag is raised when the SDMA has entered debug mode after a OnCE debug request.
bits : 9 - 9 (1 bit)
access : read-only
EDR : This flag is raised when the SDMA has entered debug mode after an external debug request.
bits : 10 - 10 (1 bit)
access : read-only
RCV : After each write access to the real time buffer (RTB), the RCV bit is set
bits : 11 - 11 (1 bit)
access : read-only
PST : The Processor Status bits reflect the state of the SDMA RISC engine
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : PST_0
Program
0x1 : PST_1
Data
0x2 : PST_2
Change of Flow
0x3 : PST_3
Change of Flow in Loop
0x4 : PST_4
Debug
0x5 : PST_5
Functional Unit
0x6 : PST_6
Sleep
0x7 : PST_7
Save
0x8 : PST_8
Program in Sleep
0x9 : PST_9
Data in Sleep
0xC : PST_12
Debug in Sleep
0xD : PST_13
Functional Unit in Sleep
0xE : PST_14
Sleep after Reset
0xF : PST_15
Restore
End of enumeration elements list.
Channel Enable RAM
address_offset : 0x4C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x4EC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
OnCE Command Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Writing to this register will cause the OnCE to execute the command that is written
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : CMD_0
rstatus
0x1 : CMD_1
dmov
0x2 : CMD_2
exec_once
0x3 : CMD_3
run_core
0x4 : CMD_4
exec_core
0x5 : CMD_5
debug_rqst
0x6 : CMD_6
rbuffer
End of enumeration elements list.
Channel Enable RAM
address_offset : 0x514C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x53D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x5668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Illegal Instruction Trap Address
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ILLINSTADDR : The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is executed
bits : 0 - 13 (14 bit)
access : read-write
Channel Enable RAM
address_offset : 0x58FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x5B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel 0 Boot Address
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHN0ADDR : This 14-bit register is used by the boot code of the SDMA
bits : 0 - 13 (14 bit)
access : read-write
SMSZ : The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel context
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SMSZ_0
24 words per context
0x1 : SMSZ_1
32 words per context
End of enumeration elements list.
Channel Enable RAM
address_offset : 0x5E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
DMA Requests
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EVENTS : This register reflects the DMA requests received by the SDMA for events 31-0
bits : 0 - 31 (32 bit)
access : read-only
Enumeration:
0 : EVENTS_0
DMA request event not pending
0x1 : EVENTS_1
DMA request event pending
End of enumeration elements list.
Channel Enable RAM
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x60D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0x6374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
DMA Requests 2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EVENTS : This register reflects the DMA requests received by the SDMA for events 47-32
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : EVENTS_0
- DMA request event not pending
End of enumeration elements list.
Channel Enable RAM
address_offset : 0x661C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x68C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x6B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x6E2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Cross-Trigger Events Configuration Register 1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUM0 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 0 - 5 (6 bit)
access : read-write
CNF0 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CNF0_0
channel
0x1 : CNF0_1
DMA request
End of enumeration elements list.
NUM1 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 8 - 13 (6 bit)
access : read-write
CNF1 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : CNF1_0
channel
0x1 : CNF1_1
DMA request
End of enumeration elements list.
NUM2 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 16 - 21 (6 bit)
access : read-write
CNF2 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CNF2_0
channel
0x1 : CNF2_1
DMA request
End of enumeration elements list.
NUM3 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 24 - 29 (6 bit)
access : read-write
CNF3 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CNF3_0
channel
0x1 : CNF3_1
DMA request
End of enumeration elements list.
Channel Enable RAM
address_offset : 0x70E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x73A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Cross-Trigger Events Configuration Register 2
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUM4 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 0 - 5 (6 bit)
access : read-write
CNF4 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CNF4_0
channel
0x1 : CNF4_1
DMA request
End of enumeration elements list.
NUM5 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 8 - 13 (6 bit)
access : read-write
CNF5 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : CNF5_0
channel
0x1 : CNF5_1
DMA request
End of enumeration elements list.
NUM6 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 16 - 21 (6 bit)
access : read-write
CNF6 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CNF6_0
channel
0x1 : CNF6_1
DMA request
End of enumeration elements list.
NUM7 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 24 - 29 (6 bit)
access : read-write
CNF7 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CNF7_0
channel
0x1 : CNF7_1
DMA request
End of enumeration elements list.
Channel Stop/Channel Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HE : This 32-bit register gives access to the Arm platform Enable bits
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Start
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTART_HE : The HSTART_HE registers are 32 bits wide with one bit for every channel
bits : 0 - 31 (32 bit)
access : read-write
Channel Enable RAM
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Priority Registers
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Channel Enable RAM
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Registers
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.