\n

SDMAARM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MC0PTR

EVTOVR

CHNENBL6

SDMA_CHNPRI13

SDMA_CHNPRI14

CHNENBL7

SDMA_CHNPRI15

DSPOVR

SDMA_CHNPRI16

CHNENBL8

SDMA_CHNPRI17

SDMA_CHNPRI18

CHNENBL9

SDMA_CHNPRI19

HOSTOVR

CHNENBL10

SDMA_CHNPRI20

SDMA_CHNPRI21

CHNENBL11

SDMA_CHNPRI22

EVTPEND

CHNENBL12

SDMA_CHNPRI23

SDMA_CHNPRI24

CHNENBL13

SDMA_CHNPRI0

SDMA_CHNPRI25

SDMA_CHNPRI26

CHNENBL14

SDMA_CHNPRI27

CHNENBL15

RESET

SDMA_CHNPRI28

SDMA_CHNPRI29

CHNENBL16

SDMA_CHNPRI30

EVTERR

CHNENBL17

SDMA_CHNPRI31

CHNENBL18

INTRMASK

CHNENBL19

CHNENBL20

PSW

SDMA_CHNPRI1

CHNENBL21

CHNENBL22

EVTERRDBG

CHNENBL23

CONFIG

CHNENBL24

CHNENBL25

SDMA_LOCK

CHNENBL26

CHNENBL27

INTR

ONCE_ENB

CHNENBL0

SDMA_CHNPRI2

CHNENBL28

ONCE_DATA

CHNENBL29

CHNENBL30

ONCE_INSTR

CHNENBL31

ONCE_STAT

CHNENBL32

CHNENBL33

ONCE_CMD

CHNENBL34

SDMA_CHNPRI3

CHNENBL35

CHNENBL36

ILLINSTADDR

CHNENBL37

CHNENBL38

CHN0ADDR

CHNENBL39

EVT_MIRROR

CHNENBL1

CHNENBL40

SDMA_CHNPRI4

CHNENBL41

EVT_MIRROR2

CHNENBL42

CHNENBL43

CHNENBL44

CHNENBL45

XTRIG_CONF1

CHNENBL46

CHNENBL47

SDMA_CHNPRI5

XTRIG_CONF2

STOP_STAT

CHNENBL2

SDMA_CHNPRI6

SDMA_CHNPRI7

CHNENBL3

SDMA_CHNPRI8

SDMA_CHNPRI9

HSTART

CHNENBL4

SDMA_CHNPRI10

SDMA_CHNPRI11

CHNENBL5

SDMA_CHNPRI12


MC0PTR

Arm platform Channel 0 Pointer
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MC0PTR MC0PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC0PTR

MC0PTR : Channel 0 Pointer contains the 32-bit address, in Arm platform memory, of channel 0 control block (the boot channel)
bits : 0 - 31 (32 bit)
access : read-write


EVTOVR

Channel Event Override
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVTOVR EVTOVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EO

EO : The Channel Event Override register contains the 32 EO[i] bits
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL6

Channel Enable RAM
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL6 CHNENBL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI13

Channel Priority Registers
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI13 SDMA_CHNPRI13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI14

Channel Priority Registers
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI14 SDMA_CHNPRI14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL7

Channel Enable RAM
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL7 CHNENBL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI15

Channel Priority Registers
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI15 SDMA_CHNPRI15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


DSPOVR

Channel BP Override
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSPOVR DSPOVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DO

DO : This register is reserved
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : DO_0

- Reserved

0x1 : DO_1

- Reset value.

End of enumeration elements list.


SDMA_CHNPRI16

Channel Priority Registers
address_offset : 0x1420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI16 SDMA_CHNPRI16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL8

Channel Enable RAM
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL8 CHNENBL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI17

Channel Priority Registers
address_offset : 0x1564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI17 SDMA_CHNPRI17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI18

Channel Priority Registers
address_offset : 0x16AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI18 SDMA_CHNPRI18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL9

Channel Enable RAM
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL9 CHNENBL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI19

Channel Priority Registers
address_offset : 0x17F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI19 SDMA_CHNPRI19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


HOSTOVR

Channel Arm platform Override
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOSTOVR HOSTOVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HO

HO : The Channel Arm platform Override register contains the 32 HO[i] bits
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL10

Channel Enable RAM
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL10 CHNENBL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI20

Channel Priority Registers
address_offset : 0x1948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI20 SDMA_CHNPRI20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI21

Channel Priority Registers
address_offset : 0x1A9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI21 SDMA_CHNPRI21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL11

Channel Enable RAM
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL11 CHNENBL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI22

Channel Priority Registers
address_offset : 0x1BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI22 SDMA_CHNPRI22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


EVTPEND

Channel Event Pending
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVTPEND EVTPEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP

EP : The Channel Event Pending register contains the 32 EP[i] bits
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL12

Channel Enable RAM
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL12 CHNENBL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI23

Channel Priority Registers
address_offset : 0x1D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI23 SDMA_CHNPRI23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI24

Channel Priority Registers
address_offset : 0x1EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI24 SDMA_CHNPRI24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL13

Channel Enable RAM
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL13 CHNENBL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI0

Channel Priority Registers
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI0 SDMA_CHNPRI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI25

Channel Priority Registers
address_offset : 0x2014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI25 SDMA_CHNPRI25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI26

Channel Priority Registers
address_offset : 0x217C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI26 SDMA_CHNPRI26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL14

Channel Enable RAM
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL14 CHNENBL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI27

Channel Priority Registers
address_offset : 0x22E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI27 SDMA_CHNPRI27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL15

Channel Enable RAM
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL15 CHNENBL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


RESET

Reset Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESET RESET read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET RESCHED

RESET : When set, this bit causes the SDMA to be held in a software reset
bits : 0 - 0 (1 bit)
access : read-only

RESCHED : When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction
bits : 1 - 1 (1 bit)
access : read-only


SDMA_CHNPRI28

Channel Priority Registers
address_offset : 0x2458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI28 SDMA_CHNPRI28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI29

Channel Priority Registers
address_offset : 0x25CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI29 SDMA_CHNPRI29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL16

Channel Enable RAM
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL16 CHNENBL16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI30

Channel Priority Registers
address_offset : 0x2744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI30 SDMA_CHNPRI30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


EVTERR

DMA Request Error Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EVTERR EVTERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNERR

CHNERR : This register is used by the SDMA to warn the Arm platform when an incoming DMA request was detected and it triggers a channel that is already pending or being serviced
bits : 0 - 31 (32 bit)
access : read-only


CHNENBL17

Channel Enable RAM
address_offset : 0x2864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL17 CHNENBL17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI31

Channel Priority Registers
address_offset : 0x28C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI31 SDMA_CHNPRI31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL18

Channel Enable RAM
address_offset : 0x2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL18 CHNENBL18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


INTRMASK

Channel Arm platform Interrupt Mask
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTRMASK INTRMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIMASK

HIMASK : The Interrupt Mask Register contains 32 interrupt generation mask bits
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL19

Channel Enable RAM
address_offset : 0x2CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL19 CHNENBL19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL20

Channel Enable RAM
address_offset : 0x2F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL20 CHNENBL20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


PSW

Schedule Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSW PSW read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR CCP NCR NCP

CCR : The Current Channel Register indicates the number of the channel that is being executed by the SDMA
bits : 0 - 3 (4 bit)
access : read-only

CCP : The Current Channel Priority indicates the priority of the current active channel
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

0 : CCP_0

No running channel

0x1 : CCP_1

Active channel priority

End of enumeration elements list.

NCR : The Next Channel Register indicates the number of the next scheduled pending channel with the highest priority
bits : 8 - 12 (5 bit)
access : read-only

NCP : The Next Channel Priority gives the next pending channel priority
bits : 13 - 15 (3 bit)
access : read-only

Enumeration:

0 : NCP_0

No running channel

0x1 : NCP_1

Active channel priority

End of enumeration elements list.


SDMA_CHNPRI1

Channel Priority Registers
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI1 SDMA_CHNPRI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL21

Channel Enable RAM
address_offset : 0x319C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL21 CHNENBL21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL22

Channel Enable RAM
address_offset : 0x33F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL22 CHNENBL22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


EVTERRDBG

DMA Request Error Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EVTERRDBG EVTERRDBG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNERR

CHNERR : This register is the same as EVTERR, except reading it does not clear its contents
bits : 0 - 31 (32 bit)
access : read-only


CHNENBL23

Channel Enable RAM
address_offset : 0x3650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL23 CHNENBL23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CONFIG

Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSM ACR RTDOBS DSPDMA

CSM : Selects the Context Switch Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : CSM_0

static

0x1 : CSM_1

dynamic low power

0x2 : CSM_2

dynamic with no loop

0x3 : CSM_3

dynamic

End of enumeration elements list.

ACR : Arm platform DMA / SDMA Core Clock Ratio
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : ACR_0

Arm platform DMA interface frequency equals twice core frequency

0x1 : ACR_1

Arm platform DMA interface frequency equals core frequency

End of enumeration elements list.

RTDOBS : Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power consumption
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : RTDOBS_0

RTD pins disabled

0x1 : RTDOBS_1

RTD pins enabled

End of enumeration elements list.

DSPDMA : This bit's function is reserved and should be configured as zero.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DSPDMA_0

- Reset Value

0x1 : DSPDMA_1

- Reserved

End of enumeration elements list.


CHNENBL24

Channel Enable RAM
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL24 CHNENBL24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL25

Channel Enable RAM
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL25 CHNENBL25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_LOCK

SDMA LOCK
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_LOCK SDMA_LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK SRESET_LOCK_CLR

LOCK : The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts and through the OnCE interface under Arm platform control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

LOCK disengaged.

0x1 : LOCK_1

LOCK enabled.

End of enumeration elements list.

SRESET_LOCK_CLR : The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing to the RESET register
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRESET_LOCK_CLR_0

Software Reset does not clear the LOCK bit.

0x1 : SRESET_LOCK_CLR_1

Software Reset clears the LOCK bit.

End of enumeration elements list.


CHNENBL26

Channel Enable RAM
address_offset : 0x3D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL26 CHNENBL26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL27

Channel Enable RAM
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL27 CHNENBL27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


INTR

Channel Interrupts
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HI

HI : The Arm platform Interrupts register contains the 32 HI[i] bits
bits : 0 - 31 (32 bit)
access : read-write


ONCE_ENB

OnCE Enable
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONCE_ENB ONCE_ENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENB

ENB : The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers are accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the Arm platform through the addresses described, as follows
bits : 0 - 0 (1 bit)
access : read-write


CHNENBL0

Channel Enable RAM
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL0 CHNENBL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI2

Channel Priority Registers
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI2 SDMA_CHNPRI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL28

Channel Enable RAM
address_offset : 0x4258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL28 CHNENBL28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


ONCE_DATA

OnCE Data Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONCE_DATA ONCE_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data register of the OnCE JTAG controller
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL29

Channel Enable RAM
address_offset : 0x44CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL29 CHNENBL29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL30

Channel Enable RAM
address_offset : 0x4744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL30 CHNENBL30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


ONCE_INSTR

OnCE Instruction Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONCE_INSTR ONCE_INSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTR

INSTR : Instruction register of the OnCE JTAG controller
bits : 0 - 15 (16 bit)
access : read-write


CHNENBL31

Channel Enable RAM
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL31 CHNENBL31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


ONCE_STAT

OnCE Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ONCE_STAT ONCE_STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECDR MST SWB ODR EDR RCV PST

ECDR : Event Cell Debug Request
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : ECDR_0

1 matched addra_cond

0x1 : ECDR_1

1 matched addrb_cond

0x2 : ECDR_2

1 matched data_cond

End of enumeration elements list.

MST : This flag is raised when the OnCE is controlled from the Arm platform peripheral interface.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

0 : MST_0

The JTAG interface controls the OnCE.

0x1 : MST_1

The Arm platform peripheral interface controls the OnCE.

End of enumeration elements list.

SWB : This flag is raised when the SDMA has entered debug mode after a software breakpoint.
bits : 8 - 8 (1 bit)
access : read-only

ODR : This flag is raised when the SDMA has entered debug mode after a OnCE debug request.
bits : 9 - 9 (1 bit)
access : read-only

EDR : This flag is raised when the SDMA has entered debug mode after an external debug request.
bits : 10 - 10 (1 bit)
access : read-only

RCV : After each write access to the real time buffer (RTB), the RCV bit is set
bits : 11 - 11 (1 bit)
access : read-only

PST : The Processor Status bits reflect the state of the SDMA RISC engine
bits : 12 - 15 (4 bit)
access : read-only

Enumeration:

0 : PST_0

Program

0x1 : PST_1

Data

0x2 : PST_2

Change of Flow

0x3 : PST_3

Change of Flow in Loop

0x4 : PST_4

Debug

0x5 : PST_5

Functional Unit

0x6 : PST_6

Sleep

0x7 : PST_7

Save

0x8 : PST_8

Program in Sleep

0x9 : PST_9

Data in Sleep

0xC : PST_12

Debug in Sleep

0xD : PST_13

Functional Unit in Sleep

0xE : PST_14

Sleep after Reset

0xF : PST_15

Restore

End of enumeration elements list.


CHNENBL32

Channel Enable RAM
address_offset : 0x4C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL32 CHNENBL32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL33

Channel Enable RAM
address_offset : 0x4EC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL33 CHNENBL33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


ONCE_CMD

OnCE Command Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ONCE_CMD ONCE_CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : Writing to this register will cause the OnCE to execute the command that is written
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : CMD_0

rstatus

0x1 : CMD_1

dmov

0x2 : CMD_2

exec_once

0x3 : CMD_3

run_core

0x4 : CMD_4

exec_core

0x5 : CMD_5

debug_rqst

0x6 : CMD_6

rbuffer

End of enumeration elements list.


CHNENBL34

Channel Enable RAM
address_offset : 0x514C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL34 CHNENBL34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI3

Channel Priority Registers
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI3 SDMA_CHNPRI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL35

Channel Enable RAM
address_offset : 0x53D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL35 CHNENBL35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL36

Channel Enable RAM
address_offset : 0x5668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL36 CHNENBL36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


ILLINSTADDR

Illegal Instruction Trap Address
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ILLINSTADDR ILLINSTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ILLINSTADDR

ILLINSTADDR : The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is executed
bits : 0 - 13 (14 bit)
access : read-write


CHNENBL37

Channel Enable RAM
address_offset : 0x58FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL37 CHNENBL37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL38

Channel Enable RAM
address_offset : 0x5B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL38 CHNENBL38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHN0ADDR

Channel 0 Boot Address
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHN0ADDR CHN0ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHN0ADDR SMSZ

CHN0ADDR : This 14-bit register is used by the boot code of the SDMA
bits : 0 - 13 (14 bit)
access : read-write

SMSZ : The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel context
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SMSZ_0

24 words per context

0x1 : SMSZ_1

32 words per context

End of enumeration elements list.


CHNENBL39

Channel Enable RAM
address_offset : 0x5E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL39 CHNENBL39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


EVT_MIRROR

DMA Requests
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EVT_MIRROR EVT_MIRROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS

EVENTS : This register reflects the DMA requests received by the SDMA for events 31-0
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

0 : EVENTS_0

DMA request event not pending

0x1 : EVENTS_1

DMA request event pending

End of enumeration elements list.


CHNENBL1

Channel Enable RAM
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL1 CHNENBL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL40

Channel Enable RAM
address_offset : 0x60D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL40 CHNENBL40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI4

Channel Priority Registers
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI4 SDMA_CHNPRI4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL41

Channel Enable RAM
address_offset : 0x6374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL41 CHNENBL41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


EVT_MIRROR2

DMA Requests 2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EVT_MIRROR2 EVT_MIRROR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS

EVENTS : This register reflects the DMA requests received by the SDMA for events 47-32
bits : 0 - 15 (16 bit)
access : read-only

Enumeration:

0 : EVENTS_0

- DMA request event not pending

End of enumeration elements list.


CHNENBL42

Channel Enable RAM
address_offset : 0x661C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL42 CHNENBL42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL43

Channel Enable RAM
address_offset : 0x68C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL43 CHNENBL43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL44

Channel Enable RAM
address_offset : 0x6B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL44 CHNENBL44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL45

Channel Enable RAM
address_offset : 0x6E2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL45 CHNENBL45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


XTRIG_CONF1

Cross-Trigger Events Configuration Register 1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTRIG_CONF1 XTRIG_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM0 CNF0 NUM1 CNF1 NUM2 CNF2 NUM3 CNF3

NUM0 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 0 - 5 (6 bit)
access : read-write

CNF0 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : CNF0_0

channel

0x1 : CNF0_1

DMA request

End of enumeration elements list.

NUM1 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 8 - 13 (6 bit)
access : read-write

CNF1 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : CNF1_0

channel

0x1 : CNF1_1

DMA request

End of enumeration elements list.

NUM2 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 16 - 21 (6 bit)
access : read-write

CNF2 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : CNF2_0

channel

0x1 : CNF2_1

DMA request

End of enumeration elements list.

NUM3 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 24 - 29 (6 bit)
access : read-write

CNF3 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CNF3_0

channel

0x1 : CNF3_1

DMA request

End of enumeration elements list.


CHNENBL46

Channel Enable RAM
address_offset : 0x70E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL46 CHNENBL46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL47

Channel Enable RAM
address_offset : 0x73A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL47 CHNENBL47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI5

Channel Priority Registers
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI5 SDMA_CHNPRI5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


XTRIG_CONF2

Cross-Trigger Events Configuration Register 2
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTRIG_CONF2 XTRIG_CONF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM4 CNF4 NUM5 CNF5 NUM6 CNF6 NUM7 CNF7

NUM4 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 0 - 5 (6 bit)
access : read-write

CNF4 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : CNF4_0

channel

0x1 : CNF4_1

DMA request

End of enumeration elements list.

NUM5 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 8 - 13 (6 bit)
access : read-write

CNF5 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : CNF5_0

channel

0x1 : CNF5_1

DMA request

End of enumeration elements list.

NUM6 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 16 - 21 (6 bit)
access : read-write

CNF6 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : CNF6_0

channel

0x1 : CNF6_1

DMA request

End of enumeration elements list.

NUM7 : Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i
bits : 24 - 29 (6 bit)
access : read-write

CNF7 : Configuration of the SDMA event line number i that is connected to the cross-trigger
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CNF7_0

channel

0x1 : CNF7_1

DMA request

End of enumeration elements list.


STOP_STAT

Channel Stop/Channel Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STOP_STAT STOP_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HE

HE : This 32-bit register gives access to the Arm platform Enable bits
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL2

Channel Enable RAM
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL2 CHNENBL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI6

Channel Priority Registers
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI6 SDMA_CHNPRI6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI7

Channel Priority Registers
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI7 SDMA_CHNPRI7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL3

Channel Enable RAM
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL3 CHNENBL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI8

Channel Priority Registers
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI8 SDMA_CHNPRI8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI9

Channel Priority Registers
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI9 SDMA_CHNPRI9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


HSTART

Channel Start
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTART HSTART read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSTART_HE

HSTART_HE : The HSTART_HE registers are 32 bits wide with one bit for every channel
bits : 0 - 31 (32 bit)
access : read-write


CHNENBL4

Channel Enable RAM
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL4 CHNENBL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI10

Channel Priority Registers
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI10 SDMA_CHNPRI10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


SDMA_CHNPRI11

Channel Priority Registers
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI11 SDMA_CHNPRI11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write


CHNENBL5

Channel Enable RAM
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHNENBL5 CHNENBL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBLn

ENBLn : This 32-bit value selects the channels that are triggered by the DMA request number n
bits : 0 - 31 (32 bit)
access : read-write


SDMA_CHNPRI12

Channel Priority Registers
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA_CHNPRI12 SDMA_CHNPRI12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNPRIn

CHNPRIn : This contains the priority of channel number n
bits : 0 - 2 (3 bit)
access : read-write



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