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LUT_LD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL_STATUS

BASE_ADDR

CTRL_STATUS_SET

CTRL_STATUS_CLR

CTRL_STATUS_TOG


CTRL_STATUS

Control/Status register for LUT Loader.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STATUS CTRL_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE BYTES_PER_REQ RD_ERR_EN RD_ERR

ENABLE : Enable LUT_LD
bits : 0 - 0 (1 bit)
access : read-write

BYTES_PER_REQ : bytes per request control
bits : 1 - 1 (1 bit)
access : read-write

RD_ERR_EN : AXI Read Error IRQ enable.
bits : 8 - 8 (1 bit)
access : read-write

RD_ERR : AXI Read Error.
bits : 16 - 16 (1 bit)
access : read-write


BASE_ADDR

Address for data fetch.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASE_ADDR BASE_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDR

BASE_ADDR : Base Address
bits : 0 - 31 (32 bit)
access : read-write


CTRL_STATUS_SET

Control/Status register for LUT Loader.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STATUS_SET CTRL_STATUS_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE BYTES_PER_REQ RD_ERR_EN RD_ERR

ENABLE : Enable LUT_LD
bits : 0 - 0 (1 bit)
access : read-write

BYTES_PER_REQ : bytes per request control
bits : 1 - 1 (1 bit)
access : read-write

RD_ERR_EN : AXI Read Error IRQ enable.
bits : 8 - 8 (1 bit)
access : read-write

RD_ERR : AXI Read Error.
bits : 16 - 16 (1 bit)
access : read-write


CTRL_STATUS_CLR

Control/Status register for LUT Loader.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STATUS_CLR CTRL_STATUS_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE BYTES_PER_REQ RD_ERR_EN RD_ERR

ENABLE : Enable LUT_LD
bits : 0 - 0 (1 bit)
access : read-write

BYTES_PER_REQ : bytes per request control
bits : 1 - 1 (1 bit)
access : read-write

RD_ERR_EN : AXI Read Error IRQ enable.
bits : 8 - 8 (1 bit)
access : read-write

RD_ERR : AXI Read Error.
bits : 16 - 16 (1 bit)
access : read-write


CTRL_STATUS_TOG

Control/Status register for LUT Loader.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STATUS_TOG CTRL_STATUS_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE BYTES_PER_REQ RD_ERR_EN RD_ERR

ENABLE : Enable LUT_LD
bits : 0 - 0 (1 bit)
access : read-write

BYTES_PER_REQ : bytes per request control
bits : 1 - 1 (1 bit)
access : read-write

RD_ERR_EN : AXI Read Error IRQ enable.
bits : 8 - 8 (1 bit)
access : read-write

RD_ERR : AXI Read Error.
bits : 16 - 16 (1 bit)
access : read-write



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