Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
AUDIO PLL1 Configuration 0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_OUTPUT_DIV_VAL : PLL output clock divide value Settings must maintain the PLL operational range
bits : 0 - 4 (5 bit)
access : read-write
PLL_REFCLK_DIV_VAL : PLL reference clock divide value
bits : 5 - 10 (6 bit)
access : read-write
PLL_NEWDIV_ACK : PLL new fraction divide handshake signal
bits : 11 - 11 (1 bit)
access : read-only
PLL_NEWDIV_VAL : PLL new fraction divide input control active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_BYPASS : PLL bypass control active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_LOCK_SEL : PLL Lock signal select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_REFCLK_SEL : PLL reference clocks select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
VIDEO PLL Configuration 0 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_OUTPUT_DIV_VAL : PLL output clock divide value Settings must maintain the PLL operational range
bits : 0 - 4 (5 bit)
access : read-write
PLL_REFCLK_DIV_VAL : PLL reference clock divide value
bits : 5 - 10 (6 bit)
access : read-write
PLL_NEWDIV_ACK : PLL new fraction divide handshake signal
bits : 11 - 11 (1 bit)
access : read-only
PLL_NEWDIV_VAL : PLL new fraction divide input control active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_BYPASS : PLL bypass control active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_LOCK_SEL : PLL Lock signal select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_REFCLK_SEL : PLL reference clocks select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
VIDEO PLL Configuration 1 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_INT_DIV_CTL : PLL Integer divide control Settings must maintain the PLL operational range
bits : 0 - 6 (7 bit)
access : read-write
PLL_FRAC_DIV_CTL : PLL fraction divide control Settings must maintain the PLL operational range
bits : 7 - 30 (24 bit)
access : read-write
GPU PLL Configuration 0 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_OUTPUT_DIV_VAL : PLL output clock divide value Settings must maintain the PLL operational range
bits : 0 - 4 (5 bit)
access : read-write
PLL_REFCLK_DIV_VAL : PLL reference clock divide value
bits : 5 - 10 (6 bit)
access : read-write
PLL_NEWDIV_ACK : PLL new fraction divide handshake signal
bits : 11 - 11 (1 bit)
access : read-only
PLL_NEWDIV_VAL : PLL new fraction divide input control active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_BYPASS : PLL bypass control active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_LOCK_SEL : PLL Lock signal select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_REFCLK_SEL : PLL reference clocks select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
GPU PLL Configuration 1 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_INT_DIV_CTL : PLL Integer divide control Settings must maintain the PLL operational range
bits : 0 - 6 (7 bit)
access : read-write
PLL_FRAC_DIV_CTL : PLL fraction divide control Settings must maintain the PLL operational range
bits : 7 - 30 (24 bit)
access : read-write
VPU PLL Configuration 0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_OUTPUT_DIV_VAL : PLL output clock divide value Settings must maintain the PLL operational range
bits : 0 - 4 (5 bit)
access : read-write
PLL_REFCLK_DIV_VAL : PLL reference clock divide value
bits : 5 - 10 (6 bit)
access : read-write
PLL_NEWDIV_ACK : PLL new fraction divide handshake signal
bits : 11 - 11 (1 bit)
access : read-only
PLL_NEWDIV_VAL : PLL new fraction divide input control active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_BYPASS : PLL bypass control active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_LOCK_SEL : PLL Lock signal select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_REFCLK_SEL : PLL reference clocks select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
VPU PLL Configuration 1 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_INT_DIV_CTL : PLL Integer divide control Settings must maintain the PLL operational range
bits : 0 - 6 (7 bit)
access : read-write
PLL_FRAC_DIV_CTL : PLL fraction divide control Settings must maintain the PLL operational range
bits : 7 - 30 (24 bit)
access : read-write
ARM PLL Configuration 0 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_OUTPUT_DIV_VAL : PLL output clock divide value Settings must maintain the PLL operational range
bits : 0 - 4 (5 bit)
access : read-write
PLL_REFCLK_DIV_VAL : PLL reference clock divide value
bits : 5 - 10 (6 bit)
access : read-write
PLL_NEWDIV_ACK : PLL new fraction divide handshake signal
bits : 11 - 11 (1 bit)
access : read-only
PLL_NEWDIV_VAL : PLL new fraction divide input control active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_BYPASS : PLL bypass control active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_LOCK_SEL : PLL Lock signal select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_REFCLK_SEL : PLL reference clocks select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
ARM PLL Configuration 1 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_INT_DIV_CTL : PLL Integer divide control Settings must maintain the PLL operational range
bits : 0 - 6 (7 bit)
access : read-write
PLL_FRAC_DIV_CTL : PLL fraction divide control Settings must maintain the PLL operational range
bits : 7 - 30 (24 bit)
access : read-write
System PLL Configuration 0 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_REFCLK_SEL : PLL reference clocks select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_LOCK_SEL : PLL Lock signal select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_BYPASS2 : Internal PLL2 bypass control active high
bits : 4 - 4 (1 bit)
access : read-write
PLL_BYPASS1 : Internal PLL1 bypass control active high
bits : 5 - 5 (1 bit)
access : read-write
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 6 - 6 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 7 - 7 (1 bit)
access : read-write
PLL_DIV20_OVERRIDE : Override the PLL_DIV20_CLKE, clock gating enable signal from CCM block active high
bits : 8 - 8 (1 bit)
access : read-write
PLL_DIV20_CLKE : PLL output clock divide by 20 clock gating enable active high
bits : 9 - 9 (1 bit)
access : read-write
PLL_DIV10_OVERRIDE : Override the PLL_DIV10_CLKE, clock gating enable signal from CCM block active high
bits : 10 - 10 (1 bit)
access : read-write
PLL_DIV10_CLKE : PLL output clock divide by 10 clock gating enable active high
bits : 11 - 11 (1 bit)
access : read-write
PLL_DIV8_OVERRIDE : Override the PLL_DIV8_CLKE, clock gating enable signal from CCM block active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_DIV8_CLKE : PLL output clock divide by 8 clock gating enable active high
bits : 13 - 13 (1 bit)
access : read-write
PLL_DIV6_OVERRIDE : Override the PLL_DIV6_CLKE, clock gating enable signal from CCM block active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_DIV6_CLKE : PLL output clock divide by 6 clock gating enable active high
bits : 15 - 15 (1 bit)
access : read-write
PLL_DIV5_OVERRIDE : Override the PLL_DIV5_CLKE, clock gating enable signal from CCM block active high
bits : 16 - 16 (1 bit)
access : read-write
PLL_DIV5_CLKE : PLL output clock divide by 5 clock gating enable active high
bits : 17 - 17 (1 bit)
access : read-write
PLL_DIV4_OVERRIDE : Override the PLL_DIV4_CLKE, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_DIV4_CLKE : PLL output clock divide by 4 clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_DIV3_OVERRIDE : Override the PLL_DIV3_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_DIV3_CLKE : PLL output clock divide by 3 clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_DIV2_OVERRIDE : Override the PLL_DIV2_CLKE, clock gating enable signal from CCM block active high
bits : 22 - 22 (1 bit)
access : read-write
PLL_DIV2_CLKE : PLL output clock divide by 2 clock gating enable active high
bits : 23 - 23 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 24 - 24 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 25 - 25 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
System_PLL Configuration 1 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_SSE : Enables Spread Spectrum Mode active high
bits : 0 - 0 (1 bit)
access : read-write
PLL_SSMF : Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658
bits : 1 - 4 (4 bit)
access : read-write
PLL_SSMD : Controls Spread Spectrum modulation depth
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : PLL_SSMD_0
0.25
0x1 : PLL_SSMD_1
0.5
0x2 : PLL_SSMD_2
0.75
0x3 : PLL_SSMD_3
1.0
0x4 : PLL_SSMD_4
1.5
0x5 : PLL_SSMD_5
2.0
0x6 : PLL_SSMD_6
3.0
0x7 : PLL_SSMD_7
4.0
End of enumeration elements list.
PLL_SSDS : Selects between Spread Spectrum Center Spread and Down Spread Modes.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PLL_SSDS_0
Center Spread
0x1 : PLL_SSDS_1
Down Spread
End of enumeration elements list.
System_PLL Configuration 2 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_FILTER_RANGE : This sets the internal PLL1 loop filter to work with the post-reference divider frequency.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PLL_FILTER_RANGE_0
25 to 35 MHz
0x1 : PLL_FILTER_RANGE_1
35 to 54 MHz
End of enumeration elements list.
PLL_OUTPUT_DIV_VAL : Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz
bits : 1 - 6 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF2 : Internal PLL2 reference clock divider value
bits : 7 - 12 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF1 : Internal PLL1 reference clock divider value
bits : 13 - 18 (6 bit)
access : read-write
PLL_REF_DIVR2 : Internal PLL2 reference clock divider value
bits : 19 - 24 (6 bit)
access : read-write
PLL_REF_DIVR1 : Internal PLL1 reference clock divider value
bits : 25 - 27 (3 bit)
access : read-write
System PLL Configuration 0 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_REFCLK_SEL : PLL reference clocks select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_LOCK_SEL : PLL Lock signal select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_BYPASS2 : Internal PLL2 bypass control active high
bits : 4 - 4 (1 bit)
access : read-write
PLL_BYPASS1 : Internal PLL1 bypass control active high
bits : 5 - 5 (1 bit)
access : read-write
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 6 - 6 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 7 - 7 (1 bit)
access : read-write
PLL_DIV20_OVERRIDE : Override the PLL_DIV20_CLKE, clock gating enable signal from CCM block active high
bits : 8 - 8 (1 bit)
access : read-write
PLL_DIV20_CLKE : PLL output clock divide by 20 clock gating enable active high
bits : 9 - 9 (1 bit)
access : read-write
PLL_DIV10_OVERRIDE : Override the PLL_DIV10_CLKE, clock gating enable signal from CCM block active high
bits : 10 - 10 (1 bit)
access : read-write
PLL_DIV10_CLKE : PLL output clock divide by 10 clock gating enable active high
bits : 11 - 11 (1 bit)
access : read-write
PLL_DIV8_OVERRIDE : Override the PLL_DIV8_CLKE, clock gating enable signal from CCM block active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_DIV8_CLKE : PLL output clock divide by 8 clock gating enable active high
bits : 13 - 13 (1 bit)
access : read-write
PLL_DIV6_OVERRIDE : Override the PLL_DIV6_CLKE, clock gating enable signal from CCM block active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_DIV6_CLKE : PLL output clock divide by 6 clock gating enable active high
bits : 15 - 15 (1 bit)
access : read-write
PLL_DIV5_OVERRIDE : Override the PLL_DIV5_CLKE, clock gating enable signal from CCM block active high
bits : 16 - 16 (1 bit)
access : read-write
PLL_DIV5_CLKE : PLL output clock divide by 5 clock gating enable active high
bits : 17 - 17 (1 bit)
access : read-write
PLL_DIV4_OVERRIDE : Override the PLL_DIV4_CLKE, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_DIV4_CLKE : PLL output clock divide by 4 clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_DIV3_OVERRIDE : Override the PLL_DIV3_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_DIV3_CLKE : PLL output clock divide by 3 clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_DIV2_OVERRIDE : Override the PLL_DIV2_CLKE, clock gating enable signal from CCM block active high
bits : 22 - 22 (1 bit)
access : read-write
PLL_DIV2_CLKE : PLL output clock divide by 2 clock gating enable active high
bits : 23 - 23 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 24 - 24 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 25 - 25 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
AUDIO PLL1 Configuration 1 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_INT_DIV_CTL : PLL Integer divide control Settings must maintain the PLL operational range
bits : 0 - 6 (7 bit)
access : read-write
PLL_FRAC_DIV_CTL : PLL fraction divide control Settings must maintain the PLL operational range
bits : 7 - 30 (24 bit)
access : read-write
System_PLL Configuration 1 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_SSE : Enables Spread Spectrum Mode active high
bits : 0 - 0 (1 bit)
access : read-write
PLL_SSMF : Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658
bits : 1 - 4 (4 bit)
access : read-write
PLL_SSMD : Controls Spread Spectrum modulation depth
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : PLL_SSMD_0
0.25
0x1 : PLL_SSMD_1
0.5
0x2 : PLL_SSMD_2
0.75
0x3 : PLL_SSMD_3
1.0
0x4 : PLL_SSMD_4
1.5
0x5 : PLL_SSMD_5
2.0
0x6 : PLL_SSMD_6
3.0
0x7 : PLL_SSMD_7
4.0
End of enumeration elements list.
PLL_SSDS : Selects between Spread Spectrum Center Spread and Down Spread Modes.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PLL_SSDS_0
Center Spread
0x1 : PLL_SSDS_1
Down Spread
End of enumeration elements list.
System_PLL Configuration 2 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_FILTER_RANGE : This sets the internal PLL1 loop filter to work with the post-reference divider frequency.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PLL_FILTER_RANGE_0
25 to 35 MHz
0x1 : PLL_FILTER_RANGE_1
35 to 54 MHz
End of enumeration elements list.
PLL_OUTPUT_DIV_VAL : Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz
bits : 1 - 6 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF2 : Internal PLL2 reference clock divider value
bits : 7 - 12 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF1 : Internal PLL1 reference clock divider value
bits : 13 - 18 (6 bit)
access : read-write
PLL_REF_DIVR2 : Internal PLL2 reference clock divider value
bits : 19 - 24 (6 bit)
access : read-write
PLL_REF_DIVR1 : Internal PLL1 reference clock divider value
bits : 25 - 27 (3 bit)
access : read-write
System PLL Configuration 0 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_REFCLK_SEL : PLL reference clocks select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_LOCK_SEL : PLL Lock signal select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_BYPASS2 : Internal PLL2 bypass control active high
bits : 4 - 4 (1 bit)
access : read-write
PLL_BYPASS1 : Internal PLL1 bypass control active high
bits : 5 - 5 (1 bit)
access : read-write
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 6 - 6 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 7 - 7 (1 bit)
access : read-write
PLL_DIV20_OVERRIDE : Override the PLL_DIV20_CLKE, clock gating enable signal from CCM block active high
bits : 8 - 8 (1 bit)
access : read-write
PLL_DIV20_CLKE : PLL output clock divide by 20 clock gating enable active high
bits : 9 - 9 (1 bit)
access : read-write
PLL_DIV10_OVERRIDE : Override the PLL_DIV10_CLKE, clock gating enable signal from CCM block active high
bits : 10 - 10 (1 bit)
access : read-write
PLL_DIV10_CLKE : PLL output clock divide by 10 clock gating enable active high
bits : 11 - 11 (1 bit)
access : read-write
PLL_DIV8_OVERRIDE : Override the PLL_DIV8_CLKE, clock gating enable signal from CCM block active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_DIV8_CLKE : PLL output clock divide by 8 clock gating enable active high
bits : 13 - 13 (1 bit)
access : read-write
PLL_DIV6_OVERRIDE : Override the PLL_DIV6_CLKE, clock gating enable signal from CCM block active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_DIV6_CLKE : PLL output clock divide by 6 clock gating enable active high
bits : 15 - 15 (1 bit)
access : read-write
PLL_DIV5_OVERRIDE : Override the PLL_DIV5_CLKE, clock gating enable signal from CCM block active high
bits : 16 - 16 (1 bit)
access : read-write
PLL_DIV5_CLKE : PLL output clock divide by 5 clock gating enable active high
bits : 17 - 17 (1 bit)
access : read-write
PLL_DIV4_OVERRIDE : Override the PLL_DIV4_CLKE, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_DIV4_CLKE : PLL output clock divide by 4 clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_DIV3_OVERRIDE : Override the PLL_DIV3_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_DIV3_CLKE : PLL output clock divide by 3 clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_DIV2_OVERRIDE : Override the PLL_DIV2_CLKE, clock gating enable signal from CCM block active high
bits : 22 - 22 (1 bit)
access : read-write
PLL_DIV2_CLKE : PLL output clock divide by 2 clock gating enable active high
bits : 23 - 23 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 24 - 24 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 25 - 25 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
System_PLL Configuration 1 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_SSE : Enables Spread Spectrum Mode active high
bits : 0 - 0 (1 bit)
access : read-write
PLL_SSMF : Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658
bits : 1 - 4 (4 bit)
access : read-write
PLL_SSMD : Controls Spread Spectrum modulation depth
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : PLL_SSMD_0
0.25
0x1 : PLL_SSMD_1
0.5
0x2 : PLL_SSMD_2
0.75
0x3 : PLL_SSMD_3
1.0
0x4 : PLL_SSMD_4
1.5
0x5 : PLL_SSMD_5
2.0
0x6 : PLL_SSMD_6
3.0
0x7 : PLL_SSMD_7
4.0
End of enumeration elements list.
PLL_SSDS : Selects between Spread Spectrum Center Spread and Down Spread Modes.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PLL_SSDS_0
Center Spread
0x1 : PLL_SSDS_1
Down Spread
End of enumeration elements list.
System_PLL Configuration 2 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_FILTER_RANGE : This sets the internal PLL1 loop filter to work with the post-reference divider frequency.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PLL_FILTER_RANGE_0
25 to 35 MHz
0x1 : PLL_FILTER_RANGE_1
35 to 54 MHz
End of enumeration elements list.
PLL_OUTPUT_DIV_VAL : Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz
bits : 1 - 6 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF2 : Internal PLL2 reference clock divider value
bits : 7 - 12 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF1 : Internal PLL1 reference clock divider value
bits : 13 - 18 (6 bit)
access : read-write
PLL_REF_DIVR2 : Internal PLL2 reference clock divider value
bits : 19 - 24 (6 bit)
access : read-write
PLL_REF_DIVR1 : Internal PLL1 reference clock divider value
bits : 25 - 27 (3 bit)
access : read-write
VIDEO PLL2 Configuration 0 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_REFCLK_SEL : PLL reference clocks select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_LOCK_SEL : PLL Lock signal select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_BYPASS2 : Internal PLL2 bypass control active high
bits : 4 - 4 (1 bit)
access : read-write
PLL_BYPASS1 : Internal PLL1 bypass control active high
bits : 5 - 5 (1 bit)
access : read-write
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 6 - 6 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 7 - 7 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 8 - 8 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 9 - 9 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
VIDEO PLL2 Configuration 1 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_SSE : Enables Spread Spectrum Mode active high
bits : 0 - 0 (1 bit)
access : read-write
PLL_SSMF : Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658
bits : 1 - 4 (4 bit)
access : read-write
PLL_SSMD : Controls Spread Spectrum modulation depth
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : PLL_SSMD_0
0.25
0x1 : PLL_SSMD_1
0.5
0x2 : PLL_SSMD_2
0.75
0x3 : PLL_SSMD_3
1.0
0x4 : PLL_SSMD_4
1.5
0x5 : PLL_SSMD_5
2.0
0x6 : PLL_SSMD_6
3.0
0x7 : PLL_SSMD_7
4.0
End of enumeration elements list.
PLL_SSDS : Selects between Spread Spectrum Center Spread and Down Spread Modes.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PLL_SSDS_0
Center Spread
0x1 : PLL_SSDS_1
Down Spread
End of enumeration elements list.
VIDEO PLL2 Configuration 2 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_FILTER_RANGE : This sets the internal PLL1 loop filter to work with the post-reference divider frequency.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PLL_FILTER_RANGE_0
25 to 35 MHz
0x1 : PLL_FILTER_RANGE_1
35 to 54 MHz
End of enumeration elements list.
PLL_OUTPUT_DIV_VAL : Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz
bits : 1 - 6 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF2 : Internal PLL2 reference clock divider value
bits : 7 - 12 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF1 : Internal PLL1 reference clock divider value
bits : 13 - 18 (6 bit)
access : read-write
PLL_REF_DIVR2 : Internal PLL2 reference clock divider value
bits : 19 - 24 (6 bit)
access : read-write
PLL_REF_DIVR1 : Internal PLL1 reference clock divider value
bits : 25 - 27 (3 bit)
access : read-write
DRAM PLL Configuration 0 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_REFCLK_SEL : PLL reference clocks select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_LOCK_SEL : PLL Lock signal select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_BYPASS2 : Internal PLL2 bypass control active high
bits : 4 - 4 (1 bit)
access : read-write
PLL_BYPASS1 : Internal PLL1 bypass control active high
bits : 5 - 5 (1 bit)
access : read-write
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 6 - 6 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 7 - 7 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 8 - 8 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 9 - 9 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
DRAM PLL Configuration 1 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_SSE : Enables Spread Spectrum Mode active high
bits : 0 - 0 (1 bit)
access : read-write
PLL_SSMF : Controls Spread Spectrum Modulation Frequency Fmod = SSMF[3:0]*2*Fvco1/251658
bits : 1 - 4 (4 bit)
access : read-write
PLL_SSMD : Controls Spread Spectrum modulation depth
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : PLL_SSMD_0
0.25
0x1 : PLL_SSMD_1
0.5
0x2 : PLL_SSMD_2
0.75
0x3 : PLL_SSMD_3
1.0
0x4 : PLL_SSMD_4
1.5
0x5 : PLL_SSMD_5
2.0
0x6 : PLL_SSMD_6
3.0
0x7 : PLL_SSMD_7
4.0
End of enumeration elements list.
PLL_SSDS : Selects between Spread Spectrum Center Spread and Down Spread Modes.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PLL_SSDS_0
Center Spread
0x1 : PLL_SSDS_1
Down Spread
End of enumeration elements list.
DRAM PLL Configuration 2 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_FILTER_RANGE : This sets the internal PLL1 loop filter to work with the post-reference divider frequency.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PLL_FILTER_RANGE_0
25 to 35 MHz
0x1 : PLL_FILTER_RANGE_1
35 to 54 MHz
End of enumeration elements list.
PLL_OUTPUT_DIV_VAL : Internal PLL2 output clock divider value Fout must be within the range 20MHz ~ 1200MHz
bits : 1 - 6 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF2 : Internal PLL2 reference clock divider value
bits : 7 - 12 (6 bit)
access : read-write
PLL_FEEDBACK_DIVF1 : Internal PLL1 reference clock divider value
bits : 13 - 18 (6 bit)
access : read-write
PLL_REF_DIVR2 : Internal PLL2 reference clock divider value
bits : 19 - 24 (6 bit)
access : read-write
PLL_REF_DIVR1 : Internal PLL1 reference clock divider value
bits : 25 - 27 (3 bit)
access : read-write
DIGPROG Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DIGPROG_MINOR : Bit[7:4] is the base layer revision, Bit[3:0] is the metal layer revision 0x10 stands for Tapeout 1
bits : 0 - 7 (8 bit)
access : read-only
DIGPROG_MAJOR_LOWER : Bit[7:4] is 0x4, stands for "Quad" Bit[3:0] is 0x0, stands for "Lite"
bits : 8 - 15 (8 bit)
access : read-only
DIGPROG_MAJOR_UPPER : Bit[7:4] is 0x8, stands for "i.MX8" Bit[3:0] is 0x2, stands for "M"
bits : 16 - 23 (8 bit)
access : read-only
Osc Misc Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSC_32K_SEL : 32KHz OSC input select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : OSC_32K_SEL_0
25M_REF_CLK_DIV800
0x1 : OSC_32K_SEL_1
RTC
End of enumeration elements list.
OSC_25M_CLKE_OVERRIDE : Override the OSC_27M_CLKE, clock gating enable signal from CCM block active high
bits : 1 - 1 (1 bit)
access : read-write
OSC_25M_CLKE : 25MHz OSC output clock gating enable active high
bits : 2 - 2 (1 bit)
access : read-write
OSC_27M_CLKE_OVERRIDE : Override the OSC_27M_CLKE, clock gating enable signal from CCM block active high
bits : 3 - 3 (1 bit)
access : read-write
OSC_27M_CLKE : 27MHz OSC output clock gating enable active high
bits : 4 - 4 (1 bit)
access : read-write
PLLOUT Monitor Configuration Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLOUT_MONITOR_CLK_SEL : Clock monitor output clock
bits : 0 - 3 (4 bit)
access : read-write
PLLOUT_MONITOR_CKE : Clock monitor output clock gating enable active high
bits : 4 - 4 (1 bit)
access : read-write
Fractional PLLOUT Divider Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUDIO_PLL1_DIV_VAL : AUDIO PLL1 clock divider value, for test purpose.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : AUDIO_PLL1_DIV_VAL_0
Divide by 1
0x1 : AUDIO_PLL1_DIV_VAL_1
Divide by 2
0x2 : AUDIO_PLL1_DIV_VAL_2
Divide by 3
0x3 : AUDIO_PLL1_DIV_VAL_3
Divide by 4
0x4 : AUDIO_PLL1_DIV_VAL_4
Divide by 5
0x5 : AUDIO_PLL1_DIV_VAL_5
Divide by 6
0x6 : AUDIO_PLL1_DIV_VAL_6
Divide by 7
0x7 : AUDIO_PLL1_DIV_VAL_7
Divide by 8
End of enumeration elements list.
AUDIO_PLL2_DIV_VAL : AUDIO PLL2 clock divider value, for test purpose.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : AUDIO_PLL2_DIV_VAL_0
Divide by 1
0x1 : AUDIO_PLL2_DIV_VAL_1
Divide by 2
0x2 : AUDIO_PLL2_DIV_VAL_2
Divide by 3
0x3 : AUDIO_PLL2_DIV_VAL_3
Divide by 4
0x4 : AUDIO_PLL2_DIV_VAL_4
Divide by 5
0x5 : AUDIO_PLL2_DIV_VAL_5
Divide by 6
0x6 : AUDIO_PLL2_DIV_VAL_6
Divide by 7
0x7 : AUDIO_PLL2_DIV_VAL_7
Divide by 8
End of enumeration elements list.
VIDEO_PLL1_DIV_VAL : VIDEO PLL1 clock divider value, for test purpose.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : VIDEO_PLL1_DIV_VAL_0
Divide by 1
0x1 : VIDEO_PLL1_DIV_VAL_1
Divide by 2
0x2 : VIDEO_PLL1_DIV_VAL_2
Divide by 3
0x3 : VIDEO_PLL1_DIV_VAL_3
Divide by 4
0x4 : VIDEO_PLL1_DIV_VAL_4
Divide by 5
0x5 : VIDEO_PLL1_DIV_VAL_5
Divide by 6
0x6 : VIDEO_PLL1_DIV_VAL_6
Divide by 7
0x7 : VIDEO_PLL1_DIV_VAL_7
Divide by 8
End of enumeration elements list.
GPU_PLL_DIV_VAL : GPU PLL clock divider value, for test purpose.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : GPU_PLL_DIV_VAL_0
Divide by 1
0x1 : GPU_PLL_DIV_VAL_1
Divide by 2
0x2 : GPU_PLL_DIV_VAL_2
Divide by 3
0x3 : GPU_PLL_DIV_VAL_3
Divide by 4
0x4 : GPU_PLL_DIV_VAL_4
Divide by 5
0x5 : GPU_PLL_DIV_VAL_5
Divide by 6
0x6 : GPU_PLL_DIV_VAL_6
Divide by 7
0x7 : GPU_PLL_DIV_VAL_7
Divide by 8
End of enumeration elements list.
VPU_PLL_DIV_VAL : VPU PLL clock divider value, for test purpose.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : VPU_PLL_DIV_VAL_0
Divide by 1
0x1 : VPU_PLL_DIV_VAL_1
Divide by 2
0x2 : VPU_PLL_DIV_VAL_2
Divide by 3
0x3 : VPU_PLL_DIV_VAL_3
Divide by 4
0x4 : VPU_PLL_DIV_VAL_4
Divide by 5
0x5 : VPU_PLL_DIV_VAL_5
Divide by 6
0x6 : VPU_PLL_DIV_VAL_6
Divide by 7
0x7 : VPU_PLL_DIV_VAL_7
Divide by 8
End of enumeration elements list.
ARM_PLL_DIV_VAL : ARM PLL clock divider value, for test purpose.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : ARM_PLL_DIV_VAL_0
Divide by 1
0x1 : ARM_PLL_DIV_VAL_1
Divide by 2
0x2 : ARM_PLL_DIV_VAL_2
Divide by 3
0x3 : ARM_PLL_DIV_VAL_3
Divide by 4
0x4 : ARM_PLL_DIV_VAL_4
Divide by 5
0x5 : ARM_PLL_DIV_VAL_5
Divide by 6
0x6 : ARM_PLL_DIV_VAL_6
Divide by 7
0x7 : ARM_PLL_DIV_VAL_7
Divide by 8
End of enumeration elements list.
SCCG PLLOUT Divider Configuration Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_PLL1_DIV_VAL : System PLL1 clock divider value, for test purpose.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SYSTEM_PLL1_DIV_VAL_0
Divide by 1
0x1 : SYSTEM_PLL1_DIV_VAL_1
Divide by 2
0x2 : SYSTEM_PLL1_DIV_VAL_2
Divide by 3
0x3 : SYSTEM_PLL1_DIV_VAL_3
Divide by 4
0x4 : SYSTEM_PLL1_DIV_VAL_4
Divide by 5
0x5 : SYSTEM_PLL1_DIV_VAL_5
Divide by 6
0x6 : SYSTEM_PLL1_DIV_VAL_6
Divide by 7
0x7 : SYSTEM_PLL1_DIV_VAL_7
Divide by 8
End of enumeration elements list.
SYSTEM_PLL2_DIV_VAL : System PLL2 clock divider value, for test purpose.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : SYSTEM_PLL2_DIV_VAL_0
Divide by 1
0x1 : SYSTEM_PLL2_DIV_VAL_1
Divide by 2
0x2 : SYSTEM_PLL2_DIV_VAL_2
Divide by 3
0x3 : SYSTEM_PLL2_DIV_VAL_3
Divide by 4
0x4 : SYSTEM_PLL2_DIV_VAL_4
Divide by 5
0x5 : SYSTEM_PLL2_DIV_VAL_5
Divide by 6
0x6 : SYSTEM_PLL2_DIV_VAL_6
Divide by 7
0x7 : SYSTEM_PLL2_DIV_VAL_7
Divide by 8
End of enumeration elements list.
SYSTEM_PLL3_DIV_VAL : System PLL3 clock divider value, for test purpose.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SYSTEM_PLL3_DIV_VAL_0
Divide by 1
0x1 : SYSTEM_PLL3_DIV_VAL_1
Divide by 2
0x2 : SYSTEM_PLL3_DIV_VAL_2
Divide by 3
0x3 : SYSTEM_PLL3_DIV_VAL_3
Divide by 4
0x4 : SYSTEM_PLL3_DIV_VAL_4
Divide by 5
0x5 : SYSTEM_PLL3_DIV_VAL_5
Divide by 6
0x6 : SYSTEM_PLL3_DIV_VAL_6
Divide by 7
0x7 : SYSTEM_PLL3_DIV_VAL_7
Divide by 8
End of enumeration elements list.
DRAM_PLL_DIV_VAL : DRAM PLL clock divider value, for test purpose.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : DRAM_PLL_DIV_VAL_0
Divide by 1
0x1 : DRAM_PLL_DIV_VAL_1
Divide by 2
0x2 : DRAM_PLL_DIV_VAL_2
Divide by 3
0x3 : DRAM_PLL_DIV_VAL_3
Divide by 4
0x4 : DRAM_PLL_DIV_VAL_4
Divide by 5
0x5 : DRAM_PLL_DIV_VAL_5
Divide by 6
0x6 : DRAM_PLL_DIV_VAL_6
Divide by 7
0x7 : DRAM_PLL_DIV_VAL_7
Divide by 8
End of enumeration elements list.
VIDEO_PLL2_DIV_VAL : VIDEO PLL2 clock divider value, for test purpose.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : VIDEO_PLL2_DIV_VAL_0
Divide by 1
0x1 : VIDEO_PLL2_DIV_VAL_1
Divide by 2
0x2 : VIDEO_PLL2_DIV_VAL_2
Divide by 3
0x3 : VIDEO_PLL2_DIV_VAL_3
Divide by 4
0x4 : VIDEO_PLL2_DIV_VAL_4
Divide by 5
0x5 : VIDEO_PLL2_DIV_VAL_5
Divide by 6
0x6 : VIDEO_PLL2_DIV_VAL_6
Divide by 7
0x7 : VIDEO_PLL2_DIV_VAL_7
Divide by 8
End of enumeration elements list.
AUDIO PLL2 Configuration 0 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_OUTPUT_DIV_VAL : PLL output clock divide value Settings must maintain the PLL operational range
bits : 0 - 4 (5 bit)
access : read-write
PLL_REFCLK_DIV_VAL : PLL reference clock divide value
bits : 5 - 10 (6 bit)
access : read-write
PLL_NEWDIV_ACK : PLL new fraction divide handshake signal
bits : 11 - 11 (1 bit)
access : read-only
PLL_NEWDIV_VAL : PLL new fraction divide input control active high
bits : 12 - 12 (1 bit)
access : read-write
PLL_COUNTCLK_SEL : PLL maximum lock time counter clock select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PLL_COUNTCLK_SEL_0
25M_REF_CLK
0x1 : PLL_COUNTCLK_SEL_1
27M_REF_CLK
End of enumeration elements list.
PLL_BYPASS : PLL bypass control active high
bits : 14 - 14 (1 bit)
access : read-write
PLL_LOCK_SEL : PLL Lock signal select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : PLL_LOCK_SEL_0
Select PLL lock output
0x1 : PLL_LOCK_SEL_1
Select maximum lock time counter output
End of enumeration elements list.
PLL_REFCLK_SEL : PLL reference clocks select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PLL_REFCLK_SEL_0
25M_REF_CLK
0x1 : PLL_REFCLK_SEL_1
27M_REF_CLK
0x2 : PLL_REFCLK_SEL_2
HDMI_PHY_27M_CLK
0x3 : PLL_REFCLK_SEL_3
CLK_P_N
End of enumeration elements list.
PLL_PD_OVERRIDE : Override the PLL_PD, clock gating enable signal from CCM block active high
bits : 18 - 18 (1 bit)
access : read-write
PLL_PD : PLL output clock clock gating enable active high
bits : 19 - 19 (1 bit)
access : read-write
PLL_CLKE_OVERRIDE : Override the PLL_CLKE, clock gating enable signal from CCM block active high
bits : 20 - 20 (1 bit)
access : read-write
PLL_CLKE : PLL output clock clock gating enable active high
bits : 21 - 21 (1 bit)
access : read-write
PLL_LOCK : PLL lock status active high
bits : 31 - 31 (1 bit)
access : read-only
AUDIO PLL2 Configuration 1 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_INT_DIV_CTL : PLL Integer divide control Settings must maintain the PLL operational range
bits : 0 - 6 (7 bit)
access : read-write
PLL_FRAC_DIV_CTL : PLL fraction divide control Settings must maintain the PLL operational range
bits : 7 - 30 (24 bit)
access : read-write
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