Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
Receive Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECSPI_RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only
Interrupt Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEEN : TXFIFO Empty Interrupt enable. This bit enables the TXFIFO Empty Interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TEEN_0
Disable
0x1 : TEEN_1
Enable
End of enumeration elements list.
TDREN : TXFIFO Data Request Interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TDREN_0
Disable
0x1 : TDREN_1
Enable
End of enumeration elements list.
TFEN : TXFIFO Full Interrupt enable. This bit enables the TXFIFO Full Interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TFEN_0
Disable
0x1 : TFEN_1
Enable
End of enumeration elements list.
RREN : RXFIFO Ready Interrupt enable. This bit enables the RXFIFO Ready Interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RREN_0
Disable
0x1 : RREN_1
Enable
End of enumeration elements list.
RDREN : RXFIFO Data Request Interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : RDREN_0
Disable
0x1 : RDREN_1
Enable
End of enumeration elements list.
RFEN : RXFIFO Full Interrupt enable. This bit enables the RXFIFO Full Interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RFEN_0
Disable
0x1 : RFEN_1
Enable
End of enumeration elements list.
ROEN : RXFIFO Overflow Interrupt enable. This bit enables the RXFIFO Overflow Interrupt.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : ROEN_0
Disable
0x1 : ROEN_1
Enable
End of enumeration elements list.
TCEN : Transfer Completed Interrupt enable. This bit enables the Transfer Completed Interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TCEN_0
Disable
0x1 : TCEN_1
Enable
End of enumeration elements list.
DMA Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THRESHOLD : TX THRESHOLD
bits : 0 - 5 (6 bit)
access : read-write
TEDEN : TXFIFO Empty DMA Request Enable. This bit enables/disables the TXFIFO Empty DMA Request.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TEDEN_0
Disable
0x1 : TEDEN_1
Enable
End of enumeration elements list.
RX_THRESHOLD : RX THRESHOLD
bits : 16 - 21 (6 bit)
access : read-write
RXDEN : RXFIFO DMA Request Enable. This bit enables/disables the RXFIFO DMA Request.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : RXDEN_0
Disable
0x1 : RXDEN_1
Enable
End of enumeration elements list.
RX_DMA_LENGTH : RX DMA LENGTH
bits : 24 - 29 (6 bit)
access : read-write
RXTDEN : RXFIFO TAIL DMA Request/Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : RXTDEN_0
Disable
0x1 : RXTDEN_1
Enable
End of enumeration elements list.
Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TE : TXFIFO Empty. This bit is set if the TXFIFO is empty.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : TE_0
TXFIFO contains one or more words.
0x1 : TE_1
TXFIFO is empty.
End of enumeration elements list.
TDR : TXFIFO Data Request.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : TDR_0
Number of valid data slots in TXFIFO is greater than TX_THRESHOLD.
0x1 : TDR_1
Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD.
End of enumeration elements list.
TF : TXFIFO Full. This bit is set when if the TXFIFO is full.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : TF_0
TXFIFO is not Full.
0x1 : TF_1
TXFIFO is Full.
End of enumeration elements list.
RR : RXFIFO Ready. This bit is set when one or more words are stored in the RXFIFO.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : RR_0
No valid data in RXFIFO.
0x1 : RR_1
More than 1 word in RXFIFO.
End of enumeration elements list.
RDR : RXFIFO Data Request.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : RDR_0
When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
0x1 : RDR_1
When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists.
End of enumeration elements list.
RF : RXFIFO Full. This bit is set when the RXFIFO is full.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : RF_0
Not Full.
0x1 : RF_1
Full.
End of enumeration elements list.
RO : RXFIFO Overflow
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : RO_0
RXFIFO has no overflow.
0x1 : RO_1
RXFIFO has overflowed.
End of enumeration elements list.
TC : Transfer Completed Status bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TC_0
Transfer in progress.
0x1 : TC_1
Transfer completed.
End of enumeration elements list.
Sample Period Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLE_PERIOD : Sample Period Control
bits : 0 - 14 (15 bit)
access : read-write
Enumeration:
0 : SAMPLE_PERIOD_0
0 wait states inserted
0x1 : SAMPLE_PERIOD_1
1 wait state inserted
0x7FFE : SAMPLE_PERIOD_32766
32766 wait states inserted
0x7FFF : SAMPLE_PERIOD_32767
32767 wait states inserted
End of enumeration elements list.
CSRC : Clock Source Control. This bit selects the clock source for the sample period counter.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CSRC_0
SPI Clock (SCLK)
0x1 : CSRC_1
Low-Frequency Reference Clock (32.768 KHz)
End of enumeration elements list.
CSD_CTL : Chip Select Delay Control bits
bits : 16 - 21 (6 bit)
access : read-write
Test Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCNT : TXFIFO Counter. This field indicates the number of words in the TXFIFO.
bits : 0 - 6 (7 bit)
access : read-write
RXCNT : RXFIFO Counter. This field indicates the number of words in the RXFIFO.
bits : 8 - 14 (7 bit)
access : read-write
LBC : Loop Back Control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LBC_0
Not connected.
0x1 : LBC_1
Transmitter and receiver sections internally connected for Loopback.
End of enumeration elements list.
Transmit Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ECSPI_TXDATA : Transmit Data
bits : 0 - 31 (32 bit)
access : write-only
Message Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ECSPI_MSGDATA : ECSPI_MSGDATA holds the top word of MSG Data FIFO
bits : 0 - 31 (32 bit)
access : write-only
Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : SPI Block Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_0
Disable the block.
0x1 : EN_1
Enable the block.
End of enumeration elements list.
HT : Hardware Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HT_0
Disable HT mode.
0x1 : HT_1
Enable HT mode.
End of enumeration elements list.
XCH : SPI Exchange Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : XCH_0
Idle.
0x1 : XCH_1
Initiates exchange (write) or busy (read).
End of enumeration elements list.
SMC : Start Mode Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SMC_0
SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions.
0x1 : SMC_1
Immediately starts a SPI burst when data is written in TXFIFO.
End of enumeration elements list.
CHANNEL_MODE : SPI CHANNEL MODE selects the mode for each SPI channel
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : CHANNEL_MODE_0
Slave mode.
0x1 : CHANNEL_MODE_1
Master mode.
End of enumeration elements list.
POST_DIVIDER : SPI Post Divider
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : POST_DIVIDER_0
Divide by 1.
0x1 : POST_DIVIDER_1
Divide by 2.
0x2 : POST_DIVIDER_2
Divide by 4.
0xE : POST_DIVIDER_14
Divide by 2 14 .
0xF : POST_DIVIDER_15
Divide by 2 15 .
End of enumeration elements list.
PRE_DIVIDER : SPI Pre Divider
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : PRE_DIVIDER_0
Divide by 1.
0x1 : PRE_DIVIDER_1
Divide by 2.
0x2 : PRE_DIVIDER_2
Divide by 3.
0xD : PRE_DIVIDER_13
Divide by 14.
0xE : PRE_DIVIDER_14
Divide by 15.
0xF : PRE_DIVIDER_15
Divide by 16.
End of enumeration elements list.
DRCTL : SPI Data Ready Control
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : DRCTL_0
The SPI_RDY signal is a don't care.
0x1 : DRCTL_1
Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
0x2 : DRCTL_2
Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
End of enumeration elements list.
CHANNEL_SELECT : SPI CHANNEL SELECT bits
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : CHANNEL_SELECT_0
Channel 0 is selected. Chip Select 0 (SS0) will be asserted.
0x1 : CHANNEL_SELECT_1
Channel 1 is selected. Chip Select 1 (SS1) will be asserted.
0x2 : CHANNEL_SELECT_2
Channel 2 is selected. Chip Select 2 (SS2) will be asserted.
0x3 : CHANNEL_SELECT_3
Channel 3 is selected. Chip Select 3 (SS3) will be asserted.
End of enumeration elements list.
BURST_LENGTH : Burst Length
bits : 20 - 31 (12 bit)
access : read-write
Enumeration:
0 : BURST_LENGTH_0
A SPI burst contains the 1 LSB in a word.
0x1 : BURST_LENGTH_1
A SPI burst contains the 2 LSB in a word.
0x2 : BURST_LENGTH_2
A SPI burst contains the 3 LSB in a word.
0x1F : BURST_LENGTH_31
A SPI burst contains all 32 bits in a word.
0x20 : BURST_LENGTH_32
A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
0x21 : BURST_LENGTH_33
A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
0xFFE : BURST_LENGTH_4094
A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
0xFFF : BURST_LENGTH_4095
A SPI burst contains 2^7 words.
End of enumeration elements list.
Config Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCLK_PHA : SPI Clock/Data Phase Control
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : SCLK_PHA_0
Phase 0 operation.
0x1 : SCLK_PHA_1
Phase 1 operation.
End of enumeration elements list.
SCLK_POL : SPI Clock Polarity Control
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : SCLK_POL_0
Active high polarity (0 = Idle).
0x1 : SCLK_POL_1
Active low polarity (1 = Idle).
End of enumeration elements list.
SS_CTL : SPI SS Wave Form Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : SS_CTL_0
In master mode - only one SPI burst will be transmitted.
0x1 : SS_CTL_1
In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.
End of enumeration elements list.
SS_POL : SPI SS Polarity Select
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : SS_POL_0
Active low.
0x1 : SS_POL_1
Active high.
End of enumeration elements list.
DATA_CTL : DATA CTL
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : DATA_CTL_0
Stay high.
0x1 : DATA_CTL_1
Stay low.
End of enumeration elements list.
SCLK_CTL : SCLK CTL
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : SCLK_CTL_0
Stay low.
0x1 : SCLK_CTL_1
Stay high.
End of enumeration elements list.
HT_LENGTH : HT LENGTH
bits : 24 - 28 (5 bit)
access : read-write
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