DSI_HOST_TX_PAYLOAD

DSI_HOST_PKT_FIFO_WR_LEVEL

DSI_HOST_PKT_FIFO_RD_LEVEL

DSI_HOST_PKT_RX_PAYLOAD

DSI_HOST_PKT_RX_PKT_HEADER

DSI_HOST_IRQ_STATUS

DSI_HOST_IRQ_STATUS2

DSI_HOST_IRQ_MASK

DSI_HOST_IRQ_MASK2

DSI_HOST_PKT_CONTROL

DSI_HOST_SEND_PACKET

DSI_HOST_PKT_STATUS

dsi_host_tx_payload : Tx Payload data write register. Writes to this registers load the payload fifo with 32 bit values.
bits : 0 - 31 (32 bit)
access : read-write

dsi_host_pkt_fifo_wr_level : Write level of APB to pkt interface fifo
bits : 0 - 15 (16 bit)
access : read-only

dsi_host_pkt_fifo_rd_level : Read level of APB to pkt interface fifo
bits : 0 - 15 (16 bit)
access : read-only

dsi_host_pkt_rx_payload : APB to pkt interface rx payload read
bits : 0 - 31 (32 bit)
access : read-only

dsi_host_pkt_rx_pkt_header : APB to pkt interface rx packet header [15:0] word count [21:16] data type [23:22] Virtual Channel
bits : 0 - 23 (24 bit)
access : read-only

dsi_host_irq_status : Status of APB to packet interface [0] - state machine not idle [1] - Tx packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all rx packet payload data has been received [28:9] - map directory to dsi host controller status_out port bit descriptions [29] - host bta timeout, host controller host_bta_timeout port [30] - low power rx timeout, host controller lp_rx_timeout port [31] - high speed tx timeout, host controller hs_tx_timeout port
bits : 0 - 31 (32 bit)
access : read-only

dsi_host_irq_status2 : Status of APB to packet interface part 2. Read part 2 first then dsi_host_irq_status. Reading dsi_host_irq_status will clear both status and status 2. [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error
bits : 0 - 2 (3 bit)
access : read-only

dsi_host_irq_mask : irq mask [0] - state machine not idle [1] - Tx packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all rx packet payload data has been received [28:9] - map directory to dsi host controller status_out port bit descriptions [29] - host bta timeout, host controller host_bta_timeout port [30] - low power rx timeout, host controller lp_rx_timeout port [31] - high speed tx timeout, host controller hs_tx_timeout port
bits : 0 - 31 (32 bit)
access : read-write

dsi_host_irq_mask2 : irq mask 2 [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error
bits : 0 - 2 (3 bit)
access : read-write

dsi_host_pkt_control : Tx packet control register. [15:0] - Packet word count [17:16] - Packet Virtual Channel [23:18] - Packet Header DSI Data Type [24] - Lp or HS select. 0 - LP mode, 1 - HS mode [25] - perform BTA after packet is sent [26] - perform BTA only, no packet tx
bits : 0 - 26 (27 bit)
access : read-write

dsi_host_send_packet : Tx send packet. Writing to this register causes the packet described in dsi_host_pkt_control to be sent.
bits : 0 - 0 (1 bit)
access : read-write

dsi_host_pkt_status : Status of APB to packet interface [0] - state machine not idle [1] - Tx packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all rx packet payload data has been receive d
bits : 0 - 8 (9 bit)
access : read-only