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DTG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

TC_CONTROL_STATUS

TC_CH1_REG4

TC_CH1_REG5

TC_CH2_REG6

TC_CH2_REG7

TC_CH3_REG8

TC_CH3_REG9

TC_CTX_LD_REG10

TC_CH1_BKRND_REG11

TC_CH2_BKRND_REG12

BLENDER_DBY_EOTF_RANGEINV

BLENDER_DBY_EOTF_RANGEMIN

TC_DTG_REG1

BLENDER_DBY_BDP

BLENDER_BKRND_I_GRAPHICS

BLENDER_BKRND_P_GRAPHICS

BLENDER_BKRND_T_GRAPHICS

TC_LINE1_INT_REG13

TC_LINE2_INT_REG14

TC_ALPHA_DEFAULT_REG15

TC_INTERRUPT_STATUS

TC_INTRERRUPT_CONTROL_REG17

TC_CH3_BKRND_REG18

TC_INTRERRUPT_MASK

TC_LINE3_INT_REG

TC_LINE4_INT_REG

TC_OL_DE_CONTROL_REG

TC_BL_DE_CONTROL_REG

TC_EL_DE_CONTROL_REG

TC_DISPLAY_REG2

TC_DISPLAY_REG3


TC_CONTROL_STATUS

Timing Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CONTROL_STATUS TC_CONTROL_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_VIDEO_BASE_PATH_ENABLE TC_VIDEO_ENH_PATH_ENABLE TC_OVERLAY_PATH_ENABLE TC_OVERLAY_FIFO_DATA_MODE TC_BLENDER_VIDEO_ALPHA_SELECT TC_GO TC_DOLBY_MODE TC_CH1_PER_PEL_ALPHA_SEL TC_CSS_PIX_COMP_SWAP TC_DEFAULT_OVERLAY_ALPHA

TC_VIDEO_BASE_PATH_ENABLE : Enable channel3 (Dolby_mode:Base Layer channel ) processing
bits : 0 - 0 (1 bit)
access : read-write

TC_VIDEO_ENH_PATH_ENABLE : Enable channel_2 (Dolby_mode:Enhancement channel ) processing
bits : 1 - 1 (1 bit)
access : read-write

TC_OVERLAY_PATH_ENABLE : Enable channel_1 (Dolby_mode:Overlay /HDR10: (GFX)) processing
bits : 2 - 2 (1 bit)
access : read-write

TC_OVERLAY_FIFO_DATA_MODE : Overlay fifo output data in yuv or RGB mode 0: YUV 1: RGB
bits : 3 - 3 (1 bit)
access : read-write

TC_BLENDER_VIDEO_ALPHA_SELECT : alpha_valid 0: No alpha in the ch1 pixel so use default foreground alpha TC_DEFAULT_OVERLAY_ALPHA 1: there is an alpha in ch1 pixel
bits : 7 - 7 (1 bit)
access : read-write

TC_GO : Used to start and stop timing controller 0: timing controller inactive
bits : 8 - 8 (1 bit)
access : read-write

TC_DOLBY_MODE : Enables Dolby mode
bits : 9 - 9 (1 bit)
access : read-write

TC_CH1_PER_PEL_ALPHA_SEL : Enables per pixel alpha for channel1 (Overlay or Graphics) 0: use alpha from TC_DEFAULT_OVERLAY_ALPHA or foreground alpha 1: use alpha from channel1 Data stream and apply blending per pixel
bits : 10 - 10 (1 bit)
access : read-write

TC_CSS_PIX_COMP_SWAP : Permutes the pixel conponent ordering into the chroma subsampler (CSS) block
bits : 12 - 14 (3 bit)
access : read-write

TC_DEFAULT_OVERLAY_ALPHA : Default alpha foreground used for the active regions where graphics channel does not provide an alpha value This is used when Graphics channel is ONLY RGB
bits : 24 - 31 (8 bit)
access : read-write


TC_CH1_REG4

Channel 1 window Register: TOP Window Coordinates for channel1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH1_REG4 TC_CH1_REG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CHANNEL_1_UPPER_LEFT_X TC_CHANNEL_1_UPPER_LEFT_Y

TC_CHANNEL_1_UPPER_LEFT_X : upper left corner X (horizontal) coordinate of the channel_1 window
bits : 0 - 12 (13 bit)
access : read-write

TC_CHANNEL_1_UPPER_LEFT_Y : upper left corner Y (vertical) coordinate of the channel_1 window
bits : 16 - 28 (13 bit)
access : read-write


TC_CH1_REG5

Channel_1 window Register: BOTTOM Window Coordinates for channel_1 window
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH1_REG5 TC_CH1_REG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CHANNEL_1_LOWER_RIGHT_X TC_CHANNEL_1_LOWER_RIGHT_Y

TC_CHANNEL_1_LOWER_RIGHT_X : lower rignt corner X (horizontal) coordinate of the channel_1 window
bits : 0 - 12 (13 bit)
access : read-write

TC_CHANNEL_1_LOWER_RIGHT_Y : lower right corner Y (vertical) coordinate of the channel_1 window
bits : 16 - 28 (13 bit)
access : read-write


TC_CH2_REG6

Channel 2 window Register: TOP Window Coordinates for channel_2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH2_REG6 TC_CH2_REG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CHANNEL_2_UPPER_LEFT_X TC_CHANNEL_2_UPPER_LEFT_Y

TC_CHANNEL_2_UPPER_LEFT_X : upper left corner X (horizontal) coordinate of the channel_2 window
bits : 0 - 12 (13 bit)
access : read-write

TC_CHANNEL_2_UPPER_LEFT_Y : upper left corner Y (vertical) coordinate of the channel_2 window
bits : 16 - 28 (13 bit)
access : read-write


TC_CH2_REG7

Channel_2 window Register: BOTTOM Window Coordinates for channel_2 pixel window
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH2_REG7 TC_CH2_REG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CHANNEL_2_LOWER_RIGHT_X TC_CHANNEL_2_LOWER_RIGHT_Y

TC_CHANNEL_2_LOWER_RIGHT_X : lower rignt corner X (horizontal) coordinate of the channel_2 window
bits : 0 - 12 (13 bit)
access : read-write

TC_CHANNEL_2_LOWER_RIGHT_Y : lower right corner Y (vertical) coordinate of the channel_2 window
bits : 16 - 28 (13 bit)
access : read-write


TC_CH3_REG8

Channel 3 window Register: TOP Window Coordinates for channel_3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH3_REG8 TC_CH3_REG8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CHANNEL_3_UPPER_LEFT_X TC_CHANNEL_3_UPPER_LEFT_Y

TC_CHANNEL_3_UPPER_LEFT_X : upper left corner X (horizontal) coordinate of the channel_3 window
bits : 0 - 12 (13 bit)
access : read-write

TC_CHANNEL_3_UPPER_LEFT_Y : upper left corner Y (vertical) coordinate of the channel_3 window
bits : 16 - 28 (13 bit)
access : read-write


TC_CH3_REG9

Channel_3 window Register: BOTTOM Window Coordinates for channel_3 pixel window
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH3_REG9 TC_CH3_REG9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CHANNEL_3_LOWER_RIGHT_X TC_CHANNEL_3_LOWER_RIGHT_Y

TC_CHANNEL_3_LOWER_RIGHT_X : lower rignt corner X (horizontal) coordinate of the channel_3 window
bits : 0 - 12 (13 bit)
access : read-write

TC_CHANNEL_3_LOWER_RIGHT_Y : lower right corner Y (vertical) coordinate of the channel_3 window
bits : 16 - 28 (13 bit)
access : read-write


TC_CTX_LD_REG10

Context Loader Register: Coordinates in the raster table where the context loader is started.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CTX_LD_REG10 TC_CTX_LD_REG10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CNTXT_DB_LINE_COUNT TC_CNTXT_SB_LINE_COUNT

TC_CNTXT_DB_LINE_COUNT : Line Count for Double Buffered (DB) Context Loading
bits : 0 - 12 (13 bit)
access : read-write

TC_CNTXT_SB_LINE_COUNT : Line Count for Sngle Bufferend (SB) Context Loading
bits : 16 - 28 (13 bit)
access : read-write


TC_CH1_BKRND_REG11

Channel_1 background pixel color.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH1_BKRND_REG11 TC_CH1_BKRND_REG11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CH1_BKRND_PEL_COMP_3 TC_CH1_BKRND_PEL_COMP_2 TC_CH1_BKRND_PEL_COMP_1

TC_CH1_BKRND_PEL_COMP_3 : 10-bit component ( B or Cr )
bits : 0 - 9 (10 bit)
access : read-write

TC_CH1_BKRND_PEL_COMP_2 : 10-bit component ( G or Cb )
bits : 10 - 19 (10 bit)
access : read-write

TC_CH1_BKRND_PEL_COMP_1 : 10-bit component ( R or Y )
bits : 20 - 29 (10 bit)
access : read-write


TC_CH2_BKRND_REG12

Channel_2 background pixel color.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH2_BKRND_REG12 TC_CH2_BKRND_REG12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CH2_BKRND_PEL_COMP_3 TC_CH2_BKRND_PEL_COMP_2 TC_CH2_BKRND_PEL_COMP_1

TC_CH2_BKRND_PEL_COMP_3 : 10-bit component ( B or Cr )
bits : 0 - 9 (10 bit)
access : read-write

TC_CH2_BKRND_PEL_COMP_2 : 10-bit component ( G or Cb )
bits : 10 - 19 (10 bit)
access : read-write

TC_CH2_BKRND_PEL_COMP_1 : 10-bit component ( R or Y )
bits : 20 - 29 (10 bit)
access : read-write


BLENDER_DBY_EOTF_RANGEINV

DBY MODE Blender control.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLENDER_DBY_EOTF_RANGEINV BLENDER_DBY_EOTF_RANGEINV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLENDER_EOTF_RANGEINV

BLENDER_EOTF_RANGEINV : eotf_rangeInv parameter for DBY blender
bits : 0 - 16 (17 bit)
access : read-write


BLENDER_DBY_EOTF_RANGEMIN

DBY MODE Blender control.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLENDER_DBY_EOTF_RANGEMIN BLENDER_DBY_EOTF_RANGEMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLENDER_EOTF_RANGEMIN

BLENDER_EOTF_RANGEMIN : eotf_rangeMin parameter for DBY blender
bits : 0 - 16 (17 bit)
access : read-write


TC_DTG_REG1

DTG lower right corner locations
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_DTG_REG1 TC_DTG_REG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_DTG_LOWER_RIGHT_X TC_DTG_LOWER_RIGHT_Y

TC_DTG_LOWER_RIGHT_X : lower right corner X (horizontal) coordinate of the raster table
bits : 0 - 12 (13 bit)
access : read-write

TC_DTG_LOWER_RIGHT_Y : lower right corner Y (vertical) coordinate of the raster table
bits : 16 - 28 (13 bit)
access : read-write


BLENDER_DBY_BDP

DBY MODE blender control.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLENDER_DBY_BDP BLENDER_DBY_BDP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLENDER_BDP

BLENDER_BDP : bitDepth parameter in DBY blender
bits : 0 - 4 (5 bit)
access : read-write


BLENDER_BKRND_I_GRAPHICS

Backgound pixel color component sent to blender. Used when no valid pixels
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLENDER_BKRND_I_GRAPHICS BLENDER_BKRND_I_GRAPHICS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLENDER_BCKRND_I_COMP

BLENDER_BCKRND_I_COMP : 28-bit component I component in DBY mode R/Y component in HDR10 MODE
bits : 0 - 27 (28 bit)
access : read-write


BLENDER_BKRND_P_GRAPHICS

Backgound pixel color component sent to blender. Used when no valid pixels
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLENDER_BKRND_P_GRAPHICS BLENDER_BKRND_P_GRAPHICS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLENDER_BCKRND_P_COMP

BLENDER_BCKRND_P_COMP : 28-bit component P component in DBY mode G/Cb component in HDR10 MODE
bits : 0 - 27 (28 bit)
access : read-write


BLENDER_BKRND_T_GRAPHICS

Backgound pixel color component sent to blender. Used when no valid pixels
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLENDER_BKRND_T_GRAPHICS BLENDER_BKRND_T_GRAPHICS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLENDER_BCKRND_T_COMP

BLENDER_BCKRND_T_COMP : 28-bit component T component in DBY mode B/Cr component in HDR10 MODE
bits : 0 - 27 (28 bit)
access : read-write


TC_LINE1_INT_REG13

LINE1 interrupt control: Coordinate where line1 interrupt is asserted
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_LINE1_INT_REG13 TC_LINE1_INT_REG13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_LINE1_INT_X TC_LINE1_INT_Y

TC_LINE1_INT_X : X (horizontal) coordinate for line1 interrupt
bits : 0 - 12 (13 bit)
access : read-write

TC_LINE1_INT_Y : Y (vertical) coordinate for line1 interrupt
bits : 16 - 28 (13 bit)
access : read-write


TC_LINE2_INT_REG14

LINE2 interrupt control: Coordinate where line2 interrupt is asserted
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_LINE2_INT_REG14 TC_LINE2_INT_REG14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_LINE2_INT_X TC_LINE2_INT_Y

TC_LINE2_INT_X : X (horizontal) coordinate for line2 interrupt
bits : 0 - 12 (13 bit)
access : read-write

TC_LINE2_INT_Y : Y (vertical) coordinate for line2 interrupt
bits : 16 - 28 (13 bit)
access : read-write


TC_ALPHA_DEFAULT_REG15

default alpha
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_ALPHA_DEFAULT_REG15 TC_ALPHA_DEFAULT_REG15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_ALPHA_DEF

TC_ALPHA_DEF : default background alpha value
bits : 0 - 7 (8 bit)
access : read-write


TC_INTERRUPT_STATUS

Timing Controller interrupt status
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TC_INTERRUPT_STATUS TC_INTERRUPT_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_LINE0_INTERRUPT TC_LINE1_INTERRUPT TC_LINE2_INTERRUPT TC_LINE3_INTERRUPT TC_RTRAM_CH1_PANIC_INTERRUPT TC_RTRAM_CH2_PANIC_INTERRUPT TC_RTRAM_CH3_PANIC_INTERRUPT

TC_LINE0_INTERRUPT : LINE0 interrupt status
bits : 0 - 0 (1 bit)
access : read-only

TC_LINE1_INTERRUPT : LINE1 interrupt status
bits : 1 - 1 (1 bit)
access : read-only

TC_LINE2_INTERRUPT : LINE2 interrupt status
bits : 2 - 2 (1 bit)
access : read-only

TC_LINE3_INTERRUPT : LINE3 interrupt status
bits : 3 - 3 (1 bit)
access : read-only

TC_RTRAM_CH1_PANIC_INTERRUPT : Panic interrupt is asserted by the scaler for channel1
bits : 4 - 4 (1 bit)
access : read-only

TC_RTRAM_CH2_PANIC_INTERRUPT : Panic interrupt is asserted by the scaler for channel2
bits : 5 - 5 (1 bit)
access : read-only

TC_RTRAM_CH3_PANIC_INTERRUPT : Panic interrupt is asserted by the scaler for channel3
bits : 6 - 6 (1 bit)
access : read-only


TC_INTRERRUPT_CONTROL_REG17

Timing Controller interrupt control.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_INTRERRUPT_CONTROL_REG17 TC_INTRERRUPT_CONTROL_REG17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_LINE0_INTERRUPT_CLR TC_LINE1_INTERRUPT_CLR TC_LINE2_INTERRUPT_CLR TC_LINE3_INTERRUPT_CLR TC_RTRAM_CH1_PANIC_INTERRUPT_CLR TC_RTRAM_CH2_PANIC_INTERRUPT_CLR TC_RTRAM_CH3_PANIC_INTERRUPT_CLR

TC_LINE0_INTERRUPT_CLR : Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register.
bits : 0 - 0 (1 bit)
access : read-write

TC_LINE1_INTERRUPT_CLR : Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register.
bits : 1 - 1 (1 bit)
access : read-write

TC_LINE2_INTERRUPT_CLR : Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register.
bits : 2 - 2 (1 bit)
access : read-write

TC_LINE3_INTERRUPT_CLR : Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register.
bits : 3 - 3 (1 bit)
access : read-write

TC_RTRAM_CH1_PANIC_INTERRUPT_CLR : Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register
bits : 4 - 4 (1 bit)
access : read-write

TC_RTRAM_CH2_PANIC_INTERRUPT_CLR : Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register
bits : 5 - 5 (1 bit)
access : read-write

TC_RTRAM_CH3_PANIC_INTERRUPT_CLR : Writing a 1 to this bit clears the respective interrupt in the TC_INTERRUPT_STATUS register
bits : 6 - 6 (1 bit)
access : read-write


TC_CH3_BKRND_REG18

Channel_3 background pixel color.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_CH3_BKRND_REG18 TC_CH3_BKRND_REG18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_CH3_BKRND_PEL_COMP_3 TC_CH3_BKRND_PEL_COMP_2 TC_CH3_BKRND_PEL_COMP_1

TC_CH3_BKRND_PEL_COMP_3 : 10-bit component ( B or Cr )
bits : 0 - 9 (10 bit)
access : read-write

TC_CH3_BKRND_PEL_COMP_2 : 10-bit component ( G or Cb )
bits : 10 - 19 (10 bit)
access : read-write

TC_CH3_BKRND_PEL_COMP_1 : 10-bit component ( R or Y )
bits : 20 - 29 (10 bit)
access : read-write


TC_INTRERRUPT_MASK

Timing Controller interrupt masks
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_INTRERRUPT_MASK TC_INTRERRUPT_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_LINE0_INT_MASK TC_LINE1_INT_MASK TC_LINE2_INT_MASK TC_LINE3_INT_MASK TC_RTRAM_CH1_PANIC_INT_MASK TC_RTRAM_CH2_PANIC_INT_MASK TC_RTRAM_CH3_PANIC_INT_MASK

TC_LINE0_INT_MASK : LINE0 interrupt status
bits : 0 - 0 (1 bit)
access : read-write

TC_LINE1_INT_MASK : LINE1 interrupt status
bits : 1 - 1 (1 bit)
access : read-write

TC_LINE2_INT_MASK : LINE2 interrupt status
bits : 2 - 2 (1 bit)
access : read-write

TC_LINE3_INT_MASK : LINE3 interrupt status
bits : 3 - 3 (1 bit)
access : read-write

TC_RTRAM_CH1_PANIC_INT_MASK : Mask bit for Channel 1 Panic interrupt asserted by the scaler 0: interrupt is disabled (masked) 1: panic interrupt is enabled
bits : 4 - 4 (1 bit)
access : read-write

TC_RTRAM_CH2_PANIC_INT_MASK : Mask bit for Channel 2 Panic interrupt asserted by the scaler 0: interrupt is disabled (masked) 1: panic interrupt is enabled
bits : 5 - 5 (1 bit)
access : read-write

TC_RTRAM_CH3_PANIC_INT_MASK : Mask bit for Channel 3 Panic interrupt asserted by the scaler 0: interrupt is disabled (masked) 1: panic interrupt is enabled
bits : 6 - 6 (1 bit)
access : read-write


TC_LINE3_INT_REG

LINE3 interrupt control: Coordinate where line3 interrupt is asserted
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_LINE3_INT_REG TC_LINE3_INT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_LINE3_INT_X TC_LINE3_INT_Y

TC_LINE3_INT_X : X (horizontal) coordinate for line3 interrupt
bits : 0 - 12 (13 bit)
access : read-write

TC_LINE3_INT_Y : Y (vertical) coordinate for line3 interrupt
bits : 16 - 28 (13 bit)
access : read-write


TC_LINE4_INT_REG

LINE4 interrupt control: Coordinate where line4 interrupt is asserted
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_LINE4_INT_REG TC_LINE4_INT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_LINE4_INT_X TC_LINE4_INT_Y

TC_LINE4_INT_X : X (horizontal) coordinate for line4 interrupt
bits : 0 - 12 (13 bit)
access : read-write

TC_LINE4_INT_Y : Y (vertical) coordinate for line4 interrupt
bits : 16 - 28 (13 bit)
access : read-write


TC_OL_DE_CONTROL_REG

For DBY Mode: Controls the assertion and de-assertion DE signal (Overlay channel).
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_OL_DE_CONTROL_REG TC_OL_DE_CONTROL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_DE_SET_LOW_X TC_DE_SET_HIGH_X TC_INVERT_DE_X

TC_DE_SET_LOW_X : X (horizontal) coordinate Where DE control signal is set to 0 in a line.
bits : 0 - 12 (13 bit)
access : read-write

TC_DE_SET_HIGH_X : X (horizontal) coordinate Where DE control signal is set to 1 in a line.
bits : 16 - 28 (13 bit)
access : read-write

TC_INVERT_DE_X : 0: DE signal is not inverted 1: DE signal is INVERTED
bits : 31 - 31 (1 bit)
access : read-write


TC_BL_DE_CONTROL_REG

For DBY Mode: Controls the assertion and de-assertion DE signal (Base layer (BL) channel).
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_BL_DE_CONTROL_REG TC_BL_DE_CONTROL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_DE_SET_LOW_X TC_DE_SET_HIGH_X TC_INVERT_DE_X

TC_DE_SET_LOW_X : X (horizontal) coordinate Where DE control signal is set to 0 in a line.
bits : 0 - 12 (13 bit)
access : read-write

TC_DE_SET_HIGH_X : X (horizontal) coordinate Where DE control signal is set to 1 in a line.
bits : 16 - 28 (13 bit)
access : read-write

TC_INVERT_DE_X : 0: DE signal is not inverted 1: DE signal is INVERTED
bits : 31 - 31 (1 bit)
access : read-write


TC_EL_DE_CONTROL_REG

For DBY Mode: Controls the assertion and de-assertion DE signal (Enhancement layer (EL) channel).
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_EL_DE_CONTROL_REG TC_EL_DE_CONTROL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_DE_SET_LOW_X TC_DE_SET_HIGH_X TC_INVERT_DE_X

TC_DE_SET_LOW_X : X (horizontal) coordinate Where DE control signal is set to 0 in a line.
bits : 0 - 12 (13 bit)
access : read-write

TC_DE_SET_HIGH_X : X (horizontal) coordinate Where DE control signal is set to 1 in a line.
bits : 16 - 28 (13 bit)
access : read-write

TC_INVERT_DE_X : 0: DE signal is not inverted 1: DE signal is INVERTED
bits : 31 - 31 (1 bit)
access : read-write


TC_DISPLAY_REG2

Display Register: TOP Window Coordinates for Active display area
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_DISPLAY_REG2 TC_DISPLAY_REG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_DISPLAY_UPPER_LEFT_X TC_DISPLAY_UPPER_LEFT_Y

TC_DISPLAY_UPPER_LEFT_X : upper left corner X (horizontal) coordinate of the active dispplay region
bits : 0 - 12 (13 bit)
access : read-write

TC_DISPLAY_UPPER_LEFT_Y : upper left corner Y (vertical) coordinate of the active display region
bits : 16 - 28 (13 bit)
access : read-write


TC_DISPLAY_REG3

Display Register: BOTTOM Window Coordinates for Active display area
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_DISPLAY_REG3 TC_DISPLAY_REG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC_DISPLAY_LOWER_RIGHT_X TC_DISPLAY_LOWER_RIGHT_Y

TC_DISPLAY_LOWER_RIGHT_X : lower rignt corner X (horizontal) coordinate of the active dispplay region
bits : 0 - 12 (13 bit)
access : read-write

TC_DISPLAY_LOWER_RIGHT_Y : lower right corner Y (vertical) coordinate of the active display region
bits : 16 - 28 (13 bit)
access : read-write



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