Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xCC30 byte (0x0)
mem_usage : registers
protection : not protected
GTXFIFOSIZ[1]-GTXFIFOSIZ[0]-GTXFIFOSIZ
GRXFIFOSIZ[1]-GRXFIFOSIZ[0]-GRXFIFOSIZ
GTXFIFOSIZ[2]-GTXFIFOSIZ[1]-GTXFIFOSIZ[0]-GTXFIFOSIZ
GRXFIFOSIZ[2]-GRXFIFOSIZ[1]-GRXFIFOSIZ[0]-GRXFIFOSIZ
GTXFIFOSIZ[3]-GTXFIFOSIZ[2]-GTXFIFOSIZ[1]-GTXFIFOSIZ[0]-GTXFIFOSIZ
Capability registers length and HC interface version number
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPLENGTH : Capability registers length
bits : 0 - 7 (8 bit)
access : read-only
HCIVERSION : HC interface version number
bits : 16 - 31 (16 bit)
access : read-only
Host controller capability parameters 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AC64 : 64-bit addressing capability
bits : 0 - 0 (1 bit)
access : read-only
BNC : BW negotiation capability
bits : 1 - 1 (1 bit)
access : read-only
CSZ : Context size
bits : 2 - 2 (1 bit)
access : read-only
PPC : Port power control
bits : 3 - 3 (1 bit)
access : read-only
PIND : Port indicators
bits : 4 - 4 (1 bit)
access : read-only
LHRC : Light HC reset capability
bits : 5 - 5 (1 bit)
access : read-only
LTC : Latency tolerance messaging capability
bits : 6 - 6 (1 bit)
access : read-only
NSS : No secondary SID support
bits : 7 - 7 (1 bit)
access : read-only
PAE : Parse all event data
bits : 8 - 8 (1 bit)
access : read-only
SPC : Short packet capability
bits : 9 - 9 (1 bit)
access : read-only
SEC : Stopped EDLTA capability
bits : 10 - 10 (1 bit)
access : read-only
CFC : Contiguous frame ID capability
bits : 11 - 11 (1 bit)
access : read-only
MAXPSASIZE : Maximum primary stream array size set as 15
bits : 12 - 15 (4 bit)
access : read-only
xECP : xHCI extended capabilities pointer set as 544
bits : 16 - 31 (16 bit)
access : read-only
Doorbell offset
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOORBELL_ARRAY_OFFSET : Doorbell array offset set as 1152
bits : 2 - 31 (30 bit)
access : read-only
Runtime register space offset
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUNTIME_REG_SPACE_OFFSET : Runtime register space offset set as 1088
bits : 5 - 31 (27 bit)
access : read-only
Global transmit FIFO size register
address_offset : 0x18610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFDEP_N : TXFIFO depth This bit contains the depth of TXFIFOn in MDWIDTH-bit words
bits : 0 - 15 (16 bit)
access : read-write
TXFSTADDR_N : Transmit FIFOn RAM start address This bit contains the memory start address for TXFIFOn in MDWIDTH-bit words
bits : 16 - 31 (16 bit)
access : read-write
Global receive FIFO size register
address_offset : 0x18710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFDEP_N : RXFIFO depth This bits contains the depth of RXFIFOn in MDWIDTH-bit words
bits : 0 - 15 (16 bit)
access : read-write
RXFSTADDR_N : RXFIFOn RAM start address This bit contains the memory start address for RXFIFOn in MDWIDTH-bit words
bits : 16 - 31 (16 bit)
access : read-write
Host controller capability parameters 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
U3C : U3 entry capability
bits : 0 - 0 (1 bit)
access : read-only
CMC : Configure endpoint command max exit latency too large capability
bits : 1 - 1 (1 bit)
access : read-only
FSC : Force save context capability
bits : 2 - 2 (1 bit)
access : read-only
CTC : Compliance transition capability
bits : 3 - 3 (1 bit)
access : read-only
LEC : Large ESIT payload capability
bits : 4 - 4 (1 bit)
access : read-only
CIC : Configuration information capability
bits : 5 - 5 (1 bit)
access : read-only
Global transmit FIFO size register
address_offset : 0x24930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFDEP_N : TXFIFO depth This bit contains the depth of TXFIFOn in MDWIDTH-bit words
bits : 0 - 15 (16 bit)
access : read-write
TXFSTADDR_N : Transmit FIFOn RAM start address This bit contains the memory start address for TXFIFOn in MDWIDTH-bit words
bits : 16 - 31 (16 bit)
access : read-write
Global receive FIFO size register
address_offset : 0x24AB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFDEP_N : RXFIFO depth This bits contains the depth of RXFIFOn in MDWIDTH-bit words
bits : 0 - 15 (16 bit)
access : read-write
RXFSTADDR_N : RXFIFOn RAM start address This bit contains the memory start address for RXFIFOn in MDWIDTH-bit words
bits : 16 - 31 (16 bit)
access : read-write
Global transmit FIFO size register
address_offset : 0x30C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFDEP_N : TXFIFO depth This bit contains the depth of TXFIFOn in MDWIDTH-bit words
bits : 0 - 15 (16 bit)
access : read-write
TXFSTADDR_N : Transmit FIFOn RAM start address This bit contains the memory start address for TXFIFOn in MDWIDTH-bit words
bits : 16 - 31 (16 bit)
access : read-write
Host controller structural parameters 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXSLOTS : Number of device slots set as 127.
bits : 0 - 7 (8 bit)
access : read-only
MAXINTRS : Number of interrupters set as 1.
bits : 8 - 18 (11 bit)
access : read-only
MAXPORTS : Maximum number of ports set as 2.
bits : 24 - 31 (8 bit)
access : read-only
Host controller structural parameters 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IST : Isochronous scheduling threshold set as 1.
bits : 0 - 3 (4 bit)
access : read-only
ERSTMAX : Event ring segment table max set as 15
bits : 4 - 7 (4 bit)
access : read-only
MAXSCRATCHPADBUFS_HI : Max scratchpad buffers high
bits : 21 - 25 (5 bit)
access : read-only
SPR : Scratchpad restore
bits : 26 - 26 (1 bit)
access : read-only
MAXSCRATCHPADBUFS : Max scratchpad buffers low set as 2
bits : 27 - 31 (5 bit)
access : read-only
Host controller structural parameters 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
U1_DEVICE_EXIT_LAT : U1 device exit latency set as 32'hA
bits : 0 - 7 (8 bit)
access : read-only
U2_DEVICE_EXIT_LAT : U2 device exit latency set as 32'h7FF
bits : 16 - 31 (16 bit)
access : read-only
Global SoC bus configuration register 0
address_offset : 0xC100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCRBRSTENA : Undefined length INCR burst type enable
bits : 0 - 0 (1 bit)
access : read-write
INCR4BRSTENA : INCR4 burst type enable
bits : 1 - 1 (1 bit)
access : read-write
INCR8BRSTENA : INCR8 burst type enable Input to BUS-GM
bits : 2 - 2 (1 bit)
access : read-write
INCR16BRSTENA : INCR16 burst type enable Input to BUS-GM
bits : 3 - 3 (1 bit)
access : read-write
INCR32BRSTENA : INCR32 burst type enable Input to BUS-GM
bits : 4 - 4 (1 bit)
access : read-write
INCR64BRSTENA : INCR64 burst type enable Input to BUS-GM
bits : 5 - 5 (1 bit)
access : read-write
INCR128BRSTENA : NCR128 burst type enable Input to BUS-GM
bits : 6 - 6 (1 bit)
access : read-write
INCR256BRSTENA : NCR256 burst type enable Input to BUS-GM
bits : 7 - 7 (1 bit)
access : read-write
DESWRREQINFO : AXI-cache for descriptor write Input to BUS-GM.
bits : 16 - 19 (4 bit)
access : read-write
DATWRREQINFO : AXI-cache for data write Input to BUS-GM.
bits : 20 - 23 (4 bit)
access : read-write
DESRDREQINFO : AXI-cache for descriptor read Input to BUS-GM.
bits : 24 - 27 (4 bit)
access : read-write
DATRDREQINFO : AXI-cache for data read Input to BUS-GM.
bits : 28 - 31 (4 bit)
access : read-write
Global SoC bus configuration register 1
address_offset : 0xC104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPETRANSLIMIT : AXI pipelined transfers burst request limit The bit controls the number of outstanding pipelined transfers requests the AXI master pushes to the AXI slave
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : PIPETRANSLIMIT_0
1 request
0x1 : PIPETRANSLIMIT_1
2 requests
0x2 : PIPETRANSLIMIT_2
3 requests
0x3 : PIPETRANSLIMIT_3
4 requests ...
0xF : PIPETRANSLIMIT_15
16 requests
End of enumeration elements list.
EN1KPAGE : 1K page boundary enable By default (this bit is disabled), the AXI breaks transfers at the 4K page boundary
bits : 12 - 12 (1 bit)
access : read-write
Global Tx threshold control register
address_offset : 0xC108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBMAXTXBURSTSIZE : USB maximum Tx burst size When USBTXPKTCNTSEL is set to 1, this bit specifies the maximum bulk OUT burst, the core can do
bits : 16 - 23 (8 bit)
access : read-write
USBTXPKTCNT : USB transmit packet count This bit specifies the number of packets that must be in the TXFIFO before the core can start transmission for the corresponding USB transaction (burst)
bits : 24 - 27 (4 bit)
access : read-write
USBTXPKTCNTSEL : USB transmit packet count enable This bit enables/disables the USB transmission multi-packet thresholding
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : USBTXPKTCNTSEL_0
USB transmission multi-packet thresholding is disabled, the core can only start transmission on the USB after the entire packet has been fetched into the corresponding TXFIFO.
0x1 : USBTXPKTCNTSEL_1
USB transmission multi-packet thresholding is enabled. The core can only start transmission on the USB after USB transmit packet count amount of packets for the USB transaction (burst) are already in the corresponding TXFIFO. This mode is only valid in the host mode. It is only used for SuperSpeed.
End of enumeration elements list.
Global Rx threshold control register
address_offset : 0xC10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBMAXRXBURSTSIZE : USB maximum receive burst size In host mode, this bit specifies the maximum bulk IN burst, the USB 3
bits : 19 - 23 (5 bit)
access : read-write
USBRXPKTCNT : USB receive packet count In host mode, this bit specifies the space (in terms of the number of packets) that must be available in the RXFIFO before the core can start the corresponding USB RX transaction (burst)
bits : 24 - 27 (4 bit)
access : read-write
USBRXPKTCNTSEL : USB receive packet count enable This bit enables/disables the USB reception multi-packet thresholding
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : USBRXPKTCNTSEL_0
The core can only start reception on the USB when the RXFIFO has space for at least one packet.
0x1 : USBRXPKTCNTSEL_1
The core can only start reception on the USB when the RXFIFO has space for at least USBRXPKTCNT amount of packets. This mode is valid in both host and device mode. It is only used for SuperSpeed.
End of enumeration elements list.
Global core control register
address_offset : 0xC110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSBLCLKGTNG : Disable clock gating When this bit is set to 1 and the core is in low power mode, internal clock gating is disabled
bits : 0 - 0 (1 bit)
access : read-write
U2EXIT_LFPS : This bit is added to improve interoperability with a third party host controller
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : U2EXIT_LFPS_0
The link treats 248 ns LFPS as a valid U2 exit.
0x1 : U2EXIT_LFPS_1
The link waits for 8 us of LFPS before it detects a valid U2 exit.
End of enumeration elements list.
DISSCRAMBLE : Disable scrambling Transmit request to link partner on next transition to recovery or polling.
bits : 3 - 3 (1 bit)
access : read-write
RAMCLKSEL : RAM clock select On USB-reset, hardware clears these bits to 2'b00
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : RAMCLKSEL_0
Bus clock
0x1 : RAMCLKSEL_1
Pipe clock
0x2 : RAMCLKSEL_2
Pipe/2 clock
End of enumeration elements list.
SOFITPSYNC : The bit is set to 0
bits : 10 - 10 (1 bit)
access : read-only
CORESOFTRESET : Core Soft Reset 0 No soft reset 1 Soft reset to core Clears the interrupts and all the CSRs except the following registers: GCTL GUCTL GSTS GGPIO GUID GUSB2PHYCFGn registers GUSB3PIPECTLn registers DCFG DCTL DEVTEN DSTS While resetting PHYs (using GUBS3PHYCFG or GUSB3PIPECTL registers), the core must be in reset state until PHY clocks are stable
bits : 11 - 11 (1 bit)
access : read-write
PRTCAPDIR : Port capability direction The sequence for switching modes in DRD configuration is as follows: Switching from device to host: Reset the controller using GCTL[CORESOFTRESET]
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x1 : PRTCAPDIR_1
For host configurations
0x2 : PRTCAPDIR_2
For device configurations
0x3 : PRTCAPDIR_3
For OTG configurations For OTG, if PRTCAPDIR is 2'b11, it acts as an OTG 2.0 device with A-device or B-device determined by the IDDIG input, and host or peripheral role based on HNP. If PRTCAPDIR is 2'b01, it acts as a DRD in host mode. If PRTCAPDIR is 2'b10, it acts as a DRD in device mode. The OTG device can be programmed to enable/disable SRP and HNP by using the bits present in the OCFG register.
End of enumeration elements list.
FRMSCLDWN : This bit scales down device view of a SoF/USOF/ITP duration
bits : 14 - 15 (2 bit)
access : read-write
U2RSTECN : If the SuperSpeed connection fails during POLL or LMP exchange, the device connects at non-SS mode
bits : 16 - 16 (1 bit)
access : read-write
BYPSSETADDR : Bypass SetAddress in device mode When this bit is set, the device core uses the value in DCFG[DEVADDR] bits directly for comparing the device address in the tokens
bits : 17 - 17 (1 bit)
access : read-write
MASTERFILTBYPASS : Master filter bypass
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : MASTERFILTBYPASS_0
Enable all the filter modules
0x1 : MASTERFILTBYPASS_1
Bypass all the filter modules
End of enumeration elements list.
PWRDNSCALE : Power down scale The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to a small part of the USB3 core that operates when the SS PHY is in its lowest power (P3) state, and therefore does not provide a clock
bits : 19 - 31 (13 bit)
access : read-write
Global status register
address_offset : 0xC118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURMOD : Current mode of operation
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : CURMOD_0
Device mode
0x1 : CURMOD_1
Host mode
End of enumeration elements list.
BUSERRADDRVLD : Bus error address valid Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error
bits : 4 - 4 (1 bit)
access : read-write
CSRTIMEOUT : CSR timeout When this bit is set to 1, it indicates that software performed a write or read to a core register that could not be completed within 17'h1FFFF bus clock cycles
bits : 5 - 5 (1 bit)
access : read-write
DEVICE_IP : Device interrupt pending This bit indicates that there is a pending interrupt pertaining to peripheral (device) operation in the device event queue
bits : 6 - 6 (1 bit)
access : read-only
HOST_IP : Host interrupt pending This bit indicates that there is a pending interrupt pertaining to xHC in the host event queue
bits : 7 - 7 (1 bit)
access : read-only
OTG_IP : OTG interrupt pending This bit indicates that there is a pending interrupt pertaining to OTG in OEVT register
bits : 10 - 10 (1 bit)
access : read-only
Global user control register 1
address_offset : 0xC11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOA_FILTER_EN : If this bit is set, the USB 2
bits : 0 - 0 (1 bit)
access : read-write
OVRLD_L1_SUSP_COM : If this bit is set, the utmi_l1_suspend_com_n is overloaded with the utmi_sleep_n signal
bits : 1 - 1 (1 bit)
access : read-write
HC_PARCHK_DISABLE : Host parameter check disable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : HC_PARCHK_DISABLE_0
The xHC checks that the input slot/EP context bits comply to the xHCI Specification. Upon detection of a parameter error during command execution, the xHC generates an event TRB with completion code indicating 'PARAMETER ERROR'. (default)
0x1 : HC_PARCHK_DISABLE_1
The xHC does not perform parameter checks and does not generate 'PARAMETER ERROR' completion code.
End of enumeration elements list.
HC_ERRATA_ENABLE : Host ELD enable When this bit is set to 1, it enables the exit latency delta (ELD) support defined in the xHCI 1
bits : 3 - 3 (1 bit)
access : read-write
L1_SUSP_THRLD_FOR_HOST : This bit is effective only when the L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1
bits : 4 - 7 (4 bit)
access : read-write
L1_SUSP_THRLD_EN_FOR_HOST : This bit is used only in host mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : L1_SUSP_THRLD_EN_FOR_HOST_0
Disable
0x1 : L1_SUSP_THRLD_EN_FOR_HOST_1
Enable
End of enumeration elements list.
PARKMODE_DISABLE_HS : This bit is used only in host mode
bits : 16 - 16 (1 bit)
access : read-write
NAK_PER_ENH_HS : If a periodic endpoint is present , and if a bulk endpoint which is also active is being NAKed by the device, then this could result in a decrease in performance of other high-speed bulk endpoint which is ACKed by the device
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NAK_PER_ENH_HS_0
Enhancement not applied
0x1 : NAK_PER_ENH_HS_1
Enables performance enhancement for HS async endpoints in the presence of NAKs
End of enumeration elements list.
NAK_PER_ENH_FS : If a periodic endpoint is present , and if a bulk endpoint which is also active is being NAKed by the device, then this could result in a decrease in performance of other full-speed bulk endpoint which is ACked by the device
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NAK_PER_ENH_FS_0
Enhancement not applied
0x1 : NAK_PER_ENH_FS_1
Enables performance enhancement for FS async endpoints in the presence of NAKs
End of enumeration elements list.
DEV_LSP_TAIL_LOCK_DIS : This is a bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DEV_LSP_TAIL_LOCK_DIS_0
Enables device lsp lock logic for tail TRB update (default)
0x1 : DEV_LSP_TAIL_LOCK_DIS_1
Fix disabled
End of enumeration elements list.
IP_GAP_ADD_ON : This bit is used to add on to the default inter packet gap setting in the USB 2.0 MAC.
bits : 21 - 23 (3 bit)
access : read-write
DEV_L1_EXIT_BY_HW : This bit is applicable for device mode (2
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DEV_L1_EXIT_BY_HW_0
Disables device L1 hardware exit logic (default)
0x1 : DEV_L1_EXIT_BY_HW_1
Feature enabled
End of enumeration elements list.
P3_IN_U2 : Setting this bit enables P3 power state when the SuperSpeed link is in U2
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : P3_IN_U2_0
When SuperSpeed link is in U2 , PowerState P2 is attempted on the PIPE interface (default)
0x1 : P3_IN_U2_1
When SuperSpeed link is in U2, PowerState P3 is attempted if GUSB3PIPECTL[17] is set
End of enumeration elements list.
DEV_FORCE_20_CLK_FOR_30_CLK : This bit is applicable (and to be set) for device mode (DCFG[SPEED] != SS) only
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DEV_FORCE_20_CLK_FOR_30_CLK_0
Uses 3.0 clock when operating in 2.0 mode (default)
0x1 : DEV_FORCE_20_CLK_FOR_30_CLK_1
Feature enabled
End of enumeration elements list.
DEV_TRB_OUT_SPR_IND : This bit is applicable for device mode only (and ignored in host mode)
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DEV_TRB_OUT_SPR_IND_0
No change in TRB status DWORD (default)
0x1 : DEV_TRB_OUT_SPR_IND_1
Feature enabled, OUT TRB status indicates short packet
End of enumeration elements list.
TX_IPGAP_LINECHECK_DIS : This bit is applicable for HS operation of u2mac
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : TX_IPGAP_LINECHECK_DIS_0
No change in linestate check (default)
0x1 : TX_IPGAP_LINECHECK_DIS_1
Feature enabled, 2.0 MAC disables linestate check during HS transmit
End of enumeration elements list.
FILTER_SE0_FSLS_EOP : This bit is applicable for FS/LS operation
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : FILTER_SE0_FSLS_EOP_0
No change in linestate check for SE0 detection in FS/LS (default)
0x1 : FILTER_SE0_FSLS_EOP_1
Feature enabled, FS/LS SE0 is filtered for 2 clocks for detecting EOP
End of enumeration elements list.
Global user ID register
address_offset : 0xC128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USERID : User ID
bits : 0 - 31 (32 bit)
access : read-write
Global user control register
address_offset : 0xC12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTFT : Device timeout fine tuning This bit is a host mode parameter which determines how long the host waits for a response from device before considering a timeout
bits : 0 - 8 (9 bit)
access : read-write
DTCT : Device timeout coarse tuning This bit is a host mode parameter which determines how long the host waits for a response from device before considering a timeout
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : DTCT_0
0 us -> use DTFT value instead
0x1 : DTCT_1
500 us
0x2 : DTCT_2
1.5 us
0x3 : DTCT_3
6.5 us
End of enumeration elements list.
INSRTEXTRFSBODl : Insert extra delay between FS bulk OUT transactions Some FS devices are slow to receive bulk OUT data and can get stuck when there are consecutive bulk OUT transactions with short inter-transaction delays
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : INSRTEXTRFSBODl_0
Host doesn't insert extra delay between consecutive bulk OUT transactions to a FS Endpoint
0x1 : INSRTEXTRFSBODl_1
Host inserts about 12 us extra delay between consecutive bulk OUT transactions to a FS Endpoint to work around the device issue. Setting this bit to 1 reduces the bulk OUT transfer performance for most of the FS devices.
End of enumeration elements list.
EXTCAPSUPTEN : External extended capability support enable When set, this bit enables extended capabilities to be implemented outside the core
bits : 12 - 12 (1 bit)
access : read-write
ENOVERLAPCHK : Enable check for LFPS overlap during remote Ux exit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : ENOVERLAPCHK_0
When the link exists U1/U2/U3 because of a remote exit, it does not look for an LFPS overlap.
0x1 : ENOVERLAPCHK_1
The SuperSpeed link when exiting U1/U2/U3 waits for either the remote link LFPS or TS1/TS2 training symbols before it confirms that the LFPS handshake is complete. This is done to handle the case where the LFPS glitch causes the link to start exiting from the low power state. Looking for the LFPS overlap makes sure that the link partner also sees the LFPS.
End of enumeration elements list.
USBHSTINAUTORETRYEN : Host IN auto retry When set, this bit enables the auto retry feature
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : USBHSTINAUTORETRYEN_0
Auto retry disabled (default)
0x1 : USBHSTINAUTORETRYEN_1
Auto retry enabled
End of enumeration elements list.
CMDEVADDR : Compliance mode for device address When this bit is 1'b1, Slot ID may have different value than device address if max_slot_enabled < 128
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CMDEVADDR_0
Device address is equal to Slot ID
0x1 : CMDEVADDR_1
Increment device address on each address device command
End of enumeration elements list.
RESBWHSEPS : Reserving 85% bandwidth for HS periodic EPs By default, HC reserves 80% of the bandwidth for periodic EPs
bits : 16 - 16 (1 bit)
access : read-write
SPRSCTRLTRANSEN : Sparse control transaction enable Some devices are slow in responding to control transfers
bits : 17 - 17 (1 bit)
access : read-write
NOEXTRDl : No extra delay between SOF and the first packet Some HS devices misbehave when the host sends a packet immediately after a SOF
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOEXTRDl_0
Host waits for 2 us after a SOF before it sends the first USB packet
0x1 : NOEXTRDl_1
Host doesn't wait after a SOF before it sends the first USB packet
End of enumeration elements list.
REFCLKPER : This bit indicates in terms of nano seconds the period of ref_clk
bits : 22 - 31 (10 bit)
access : read-write
Global SoC bus error address register low
address_offset : 0xC130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSERRADDR : Bus address - low This 64-bit register contains the lower 32 bits of the first bus address that encountered a SoC bus error
bits : 0 - 31 (32 bit)
access : read-only
Global SoC bus error address register high
address_offset : 0xC134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSERRADDR : Bus address - high This 64-bit register contains the higher 32 bits of the first bus address that encountered a SoC bus error
bits : 0 - 31 (32 bit)
access : read-only
Global SS port to bus instance mapping register - low
address_offset : 0xC138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BINUM1 : SS USB instance number for port. Value set as 0.
bits : 0 - 3 (4 bit)
access : read-write
Global SS port to bus instance mapping register - high
address_offset : 0xC13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BINUM9 : SS USB instance number for port 9.
bits : 0 - 3 (4 bit)
access : read-write
Global hardware parameters register 0
address_offset : 0xC140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_MODE : Mode of operation It selects the controller mode for USB 3
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x2 : DWC_USB3_MODE_2
DRD
End of enumeration elements list.
DWC_USB3_MBUS_TYPE : Master bus (DMA bus) interface type It selects the chip master bus interface type
bits : 3 - 5 (3 bit)
access : read-only
Enumeration:
0x1 : DWC_USB3_MBUS_TYPE_1
AXI
End of enumeration elements list.
DWC_USB3_SBUS_TYPE : Slave bus (Register access bus) interface type It selects the chip slave bus interface type
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0 : DWC_USB3_SBUS_TYPE_0
AHB
End of enumeration elements list.
DWC_USB3_MDWIDTH : Master bus (DMA bus) data bus width It selects the data bus width of the master bus interface
bits : 8 - 15 (8 bit)
access : read-only
DWC_USB3_SDWIDTH : Slave bus (Register access bus) data bus width: 32 bit
bits : 16 - 23 (8 bit)
access : read-only
DWC_USB3_AWIDTH : Master/Slave address bus width: 64 bit
bits : 24 - 31 (8 bit)
access : read-only
Global hardware parameters register 1
address_offset : 0xC144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_IDWIDTH1 : Master ID port width It selects the ID port width of the master bus interface
bits : 0 - 2 (3 bit)
access : read-only
DWC_USB3_BURSTWIDTH : DWC_USB3_BURSTWIDTH 1 It selects the burst port width of the master and slave bus interfaces
bits : 3 - 5 (3 bit)
access : read-only
DWC_USB3_DATAINFOWIDTH : It selects the data info port width of the master and slave bus interfaces
bits : 6 - 8 (3 bit)
access : read-only
DWC_USB3_REQINFOWIDTH : It selects the request/response info port width of the master and slave bus interfaces
bits : 9 - 11 (3 bit)
access : read-only
DWC_USB3_ASPACEWIDTH : It selects the address space port width of the master and slave bus interfaces
bits : 12 - 14 (3 bit)
access : read-only
DWC_USB3_DEVICE_NUM_INT : Number of device mode event buffers It selects the number of event buffers in device mode
bits : 15 - 20 (6 bit)
access : read-only
DWC_USB3_NUM_RAMS : Number of RAMs It selects the number of RAMs. The possible values are 1, 2 and 3.
bits : 21 - 22 (2 bit)
access : read-only
DWC_USB3_SPRAM_TYP : Synchronous static RAM type It selects the FIFO synchronous static RAM type.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : DWC_USB3_SPRAM_TYP_0
2-port RAM (2Port-RAM)
0x1 : DWC_USB3_SPRAM_TYP_1
Single-port RAM (SPRAM)
End of enumeration elements list.
DWC_USB3_EN_PWROPT : Power optimization mode It specifies the power optimization mode
bits : 24 - 25 (2 bit)
access : read-only
Enumeration:
0 : DWC_USB3_EN_PWROPT_0
No power optimization
0x1 : DWC_USB3_EN_PWROPT_1
Clock gating only
End of enumeration elements list.
DWC_USB3_MAC_PHY_CLKS_SYNC : It specifies whether the MAC clock and the PHY clock are synchronous to each other.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : DWC_USB3_MAC_PHY_CLKS_SYNC_0
No
0x1 : DWC_USB3_MAC_PHY_CLKS_SYNC_1
Yes
End of enumeration elements list.
DWC_USB3_MAC_RAM_CLKS_SYNC : It specifies whether the MAC clock and the RAM clock are synchronous to each other.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : DWC_USB3_MAC_RAM_CLKS_SYNC_0
No
0x1 : DWC_USB3_MAC_RAM_CLKS_SYNC_1
Yes
End of enumeration elements list.
DWC_USB3_RAM_BUS_CLKS_SYNC : It specifies whether the RAM clock and the Bus clock are synchronous to each other.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : DWC_USB3_RAM_BUS_CLKS_SYNC_0
No
0x1 : DWC_USB3_RAM_BUS_CLKS_SYNC_1
Yes
End of enumeration elements list.
DWC_USB3_RM_OPT_FEATURES : It specifies whether to remove optional features
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : DWC_USB3_RM_OPT_FEATURES_0
No
0x1 : DWC_USB3_RM_OPT_FEATURES_1
Yes
End of enumeration elements list.
DWC_USB3_EN_DBC : Enables xHCI debug capability
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : DWC_USB3_EN_DBC_0
No
0x1 : DWC_USB3_EN_DBC_1
Yes
End of enumeration elements list.
Global hardware parameters register 2
address_offset : 0xC148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_USERID : Global user ID (GUID) register's power-on-initialization value It specifies the global user ID (GUID) register's power-on-initialization value
bits : 0 - 31 (32 bit)
access : read-only
Global hardware parameters register 3
address_offset : 0xC14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_SSPHY_INTERFACE : It specifies the superSpeed PHY interface
bits : 0 - 1 (2 bit)
access : read-only
DWC_USB3_HSPHY_INTERFACE : It specifies the high-speed PHY interface(s). The value is set as 1 for UTMI+.
bits : 2 - 3 (2 bit)
access : read-only
DWC_USB3_HSPHY_DWIDTH : It specifies the data width of the UTMI+ PHY interface. All other settings are reserved.
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x2 : DWC_USB3_HSPHY_DWIDTH_2
8-/16-bits
End of enumeration elements list.
DWC_USB3_VENDOR_CTL_INTERFACE : The bit enables the UTMI+ PHY vendor control interface. The value is enabled and value is set as 1.
bits : 10 - 10 (1 bit)
access : read-only
DWC_USB3_NUM_EPS : Number of device mode endpoints It specifies the number of device mode single directional endpoints, including OUT and IN endpoint
bits : 12 - 17 (6 bit)
access : read-only
DWC_USB3_NUM_IN_EPS : Number of device mode active IN endpoints It specifies the maximum number of device mode IN endpoints active at any time, including control endpoint 0, which is always present
bits : 18 - 22 (5 bit)
access : read-only
DWC_USB3_CACHE_TOTAL_XFER_RESOURCES : It selects the maximum number of transfer resources in the core. The value is set as 8.
bits : 23 - 30 (8 bit)
access : read-only
Global hardware parameters register 4
address_offset : 0xC150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_CACHE_TRBS_PER_TRANSFER : Number of cached TRBs per transfer It selects the number of transfer request blocks (TRBs) per transfer that can be cached within the core
bits : 0 - 5 (6 bit)
access : read-only
DWC_USB3_NUM_SS_USB_INSTANCES : Number of SuperSpeed USB bus instances It specifies the number of SuperSpeed USB bus instances
bits : 17 - 20 (4 bit)
access : read-only
DWC_USB3_EN_ISOC_SUPT : It enables isochronous endpoint capability
bits : 23 - 23 (1 bit)
access : read-only
DWC_USB3_BMU_PTL_DEPTH : It specifies the depth of the BMU-PTL source/sink buffers. The value is set as 8.
bits : 24 - 27 (4 bit)
access : read-only
DWC_USB3_BMU_LSP_DEPTH : It specifies the depth of the BMU-LSP status buffer. The value is set as 4.
bits : 28 - 31 (4 bit)
access : read-only
Global hardware parameters register 5
address_offset : 0xC154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_BMU_BUSGM_DEPTH : It specifies the depth of the BMU-BUSGM source/sink buffers
bits : 0 - 3 (4 bit)
access : read-only
DWC_USB3_RXQ_FIFO_DEPTH : It specifies the size of the BMU Rx request queue
bits : 4 - 9 (6 bit)
access : read-only
DWC_USB3_TXQ_FIFO_DEPTH : It specifies the size of the BMU Tx request queue
bits : 10 - 15 (6 bit)
access : read-only
DWC_USB3_DWQ_FIFO_DEPTH : It specifies the size of the BMU descriptor write queue
bits : 16 - 21 (6 bit)
access : read-only
DWC_USB3_DFQ_FIFO_DEPTH : It specifies the size of the BMU descriptor fetch request queue
bits : 22 - 27 (6 bit)
access : read-only
Global hardware parameters register 6
address_offset : 0xC158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_PSQ_FIFO_DEPTH : It specifies the size of the BMU protocol status queue
bits : 0 - 5 (6 bit)
access : read-only
DWC_USB3_EN_DBG_PORTS : It is used for FPGA hardware validation of the core.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : DWC_USB3_EN_DBG_PORTS_0
No
0x1 : DWC_USB3_EN_DBG_PORTS_1
Yes
End of enumeration elements list.
DWC_USB3_EN_FPGA : Hardware validation/driver development with an FPGA platform
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : DWC_USB3_EN_FPGA_0
No
0x1 : DWC_USB3_EN_FPGA_1
Yes
End of enumeration elements list.
SRPSUPPORT : SRP support enabled The application uses this bit to determine the USB 3.0 core's SRP support.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : SRPSUPPORT_0
SRP support is not enabled
0x1 : SRPSUPPORT_1
SRP support is enabled
End of enumeration elements list.
HNPSUPPORT : HNP support enabled The application uses this bit to determine the USB 3.0 core's HNP support.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : HNPSUPPORT_0
HNP support is not enabled
0x1 : HNPSUPPORT_1
HNP support is enabled
End of enumeration elements list.
ADPSUPPORT : It enables internal ADP capability of the USB 3
bits : 12 - 12 (1 bit)
access : read-only
BUSFLTRSSUPPORT : It specifies whether to add a filter for VBUS and ID related control inputs from the PHY
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : BUSFLTRSSUPPORT_0
No
0x1 : BUSFLTRSSUPPORT_1
Yes
End of enumeration elements list.
DWC_USB3_RAM0_DEPTH : Total RAM0 depth
bits : 16 - 31 (16 bit)
access : read-only
Global hardware parameters register 7
address_offset : 0xC15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_RAM1_DEPTH : Total RAM1 depth. It specifies the depth of RAM1. The value is set as 1101.
bits : 0 - 15 (16 bit)
access : read-only
DWC_USB3_RAM2_DEPTH : Total RAM2 depth. It specifies the depth of RAM2. The value is set as 776.
bits : 16 - 31 (16 bit)
access : read-only
Global high-speed port to bus instance mapping register - low
address_offset : 0xC180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BINUM1 : HS USB instance number for port 1. The value is set as 0.
bits : 0 - 3 (4 bit)
access : read-write
Global high-speed port to bus instance mapping register - high
address_offset : 0xC184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BINUM9 : HS USB instance number for port 9.
bits : 0 - 3 (4 bit)
access : read-write
Global USB2 PHY configuration register
address_offset : 0xC200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYIF : PHY interface If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with an 8-bit or 16-bit interface
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PHYIF_0
8-bit interface
0x1 : PHYIF_1
16-bit interface
End of enumeration elements list.
SUSPENDUSB20 : Suspend USB2
bits : 6 - 6 (1 bit)
access : read-write
ENBLSLPM : Enable utmi_sleep_n and utmi_l1_suspend_n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : ENBLSLPM_0
utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferred to the external PHY
0x1 : ENBLSLPM_1
utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY
End of enumeration elements list.
LSIPD : LS inter-packet time
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : LSIPD_0
2-bit times
0x1 : LSIPD_1
2.5-bit times
0x2 : LSIPD_2
3-bit times
0x3 : LSIPD_3
3.5-bit times
0x4 : LSIPD_4
4-bit times
0x5 : LSIPD_5
4.5-bit times
0x6 : LSIPD_6
5-bit times
0x7 : LSIPD_7
5.5-bit times
End of enumeration elements list.
LSTRD : LS turnaround time
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : LSTRD_0
2-bit times
0x1 : LSTRD_1
2.5-bit times
0x2 : LSTRD_2
3-bit times
0x3 : LSTRD_3
3.5-bit times
0x4 : LSTRD_4
4-bit times
0x5 : LSTRD_5
4.5-bit times
0x6 : LSTRD_6
5-bit times
0x7 : LSTRD_7
5.5-bit times
End of enumeration elements list.
U2_FREECLK_EXISTS : Specifies USB 2.0 PHY free-running PHY clock exists. The value is set as 1.
bits : 30 - 30 (1 bit)
access : read-only
PHYSOFTRST : UTMI PHY soft reset. It causes the usb2phy_reset signal to be asserted to reset a UTMI PHY.
bits : 31 - 31 (1 bit)
access : read-write
Global USB 3.0 PIPE control register
address_offset : 0xC2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELASTIC_BUFFER_MODE : Elastic buffer mode
bits : 0 - 0 (1 bit)
access : read-write
TX_DE_EPPHASIS : Tx deemphasis The value driven to the PHY is controlled by the LTSSM during USB3 Compliance mode
bits : 1 - 2 (2 bit)
access : read-write
TX_MARGIN : Tx margin[2:0]. Refer to Table 5-3 of the PIPE3 specification.
bits : 3 - 5 (3 bit)
access : read-write
TX_SWING : Tx swing. Refer to the PIPE3 specification.
bits : 6 - 6 (1 bit)
access : read-write
DATWIDTH : PIPE data width One clock after reset, these bits receive the value.
bits : 15 - 16 (2 bit)
access : read-only
Enumeration:
0 : DATWIDTH_0
32 bits
0x1 : DATWIDTH_1
16 bits
0x2 : DATWIDTH_2
8 bits
End of enumeration elements list.
SUSPENDENABLE : Suspend USB3
bits : 17 - 17 (1 bit)
access : read-only
U1U2EXITFAIL_TO_RECOV : U1U2exitfail to recovery When set, and U1/U2 LFPS handshake fails, the LTSSM transitions from U1/U2 to recovery instead of SS inactive
bits : 25 - 25 (1 bit)
access : read-write
DISRXDETP3 : Disabled receiver detection in P3
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISRXDETP3_0
If PHY is in P3 and core needs to perform receiver detection, the core performs receiver detection in P3 (default)
0x1 : DISRXDETP3_1
If PHY is in P3 and core needs to perform receiver detection, the core changes PHY power state to P2 and then perform receiver detection. After receiver detection, the core changes PHY power state to P3
End of enumeration elements list.
U2SSINACTP3OK : P3 OK for U2/SSInactive
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : U2SSINACTP3OK_0
During link state U2/SS.Inactive, put PHY in P2 (default)
0x1 : U2SSINACTP3OK_1
During link state U2/SS.Inactive, put PHY in P3
End of enumeration elements list.
PHYSOFTRST : USB3 PHY soft reset. After setting this bit to 1, the software needs to clear this bit.
bits : 31 - 31 (1 bit)
access : read-write
Global transmit FIFO size register
address_offset : 0xC300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFDEP_N : TXFIFO depth This bit contains the depth of TXFIFOn in MDWIDTH-bit words
bits : 0 - 15 (16 bit)
access : read-write
TXFSTADDR_N : Transmit FIFOn RAM start address This bit contains the memory start address for TXFIFOn in MDWIDTH-bit words
bits : 16 - 31 (16 bit)
access : read-write
Global receive FIFO size register
address_offset : 0xC380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFDEP_N : RXFIFO depth This bits contains the depth of RXFIFOn in MDWIDTH-bit words
bits : 0 - 15 (16 bit)
access : read-write
RXFSTADDR_N : RXFIFOn RAM start address This bit contains the memory start address for RXFIFOn in MDWIDTH-bit words
bits : 16 - 31 (16 bit)
access : read-write
Global event buffer address (low) register
address_offset : 0xC400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVNTADRLO : Event buffer address Holds the lower 32 bits of start address of the external memory for the event buffer
bits : 0 - 31 (32 bit)
access : read-write
Global event buffer address (high) register
address_offset : 0xC404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVNTADRHI : Event buffer address Holds the higher 32 bits of start address of the external memory for the event buffer
bits : 0 - 31 (32 bit)
access : read-write
Global event buffer size register
address_offset : 0xC408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTSIZ : Event buffer size in bytes Holds the size of the event buffer in bytes; must be a multiple of four
bits : 0 - 15 (16 bit)
access : read-write
EVNTINTRPTMASK : Event interrupt mask When set to 1, this prevents the interrupt from being generated
bits : 31 - 31 (1 bit)
access : read-write
Global event buffer count register
address_offset : 0xC40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVNTCOUNT : Event count When read, returns the number of valid events in the event buffer (in bytes)
bits : 0 - 15 (16 bit)
access : read-write
Global hardware parameters register 8
address_offset : 0xC600 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DWC_USB3_DCACHE_DEPTH_INFO : The read-only value defines the minimum RAM0 requirement. The value of the bit is set as 2308.
bits : 0 - 31 (32 bit)
access : read-only
Global device TXFIFO DMA priority register
address_offset : 0xC610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTXFIFOPRIDEV : Device TXFIFO priority
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : GTXFIFOPRIDEV_0
Low (default)
0x1 : GTXFIFOPRIDEV_1
High
End of enumeration elements list.
Global host TXFIFO DMA priority register
address_offset : 0xC618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTXFIFOPRIHST : Host TXFIFO priority
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : GTXFIFOPRIHST_0
Low priority (default)
0x1 : GTXFIFOPRIHST_1
High priority
End of enumeration elements list.
Global host RXFIFO DMA priority register
address_offset : 0xC61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GRXFIFOPRIHST : Host RXFIFO priority
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : GRXFIFOPRIHST_0
Low priority (default)
0x1 : GRXFIFOPRIHST_1
High priority
End of enumeration elements list.
Global host FIFO DMA high-low priority ratio register
address_offset : 0xC624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTTXFIFO : Host TXFIFO DMA high-low priority ratio
bits : 0 - 4 (5 bit)
access : read-write
HSTRXFIFO : Host RXFIFO DMA high-low priority ratio
bits : 8 - 12 (5 bit)
access : read-write
Global frame length adjustment register
address_offset : 0xC630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFLADJ_30MHZ : This bit indicates the value that is used for frame length adjustment when GFLADJ_30MHZ_REG_SEL = 1
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : GFLADJ_30MHZ_0
Frame length is 59488 HS bit times
0x1 : GFLADJ_30MHZ_1
Frame length is 59504 HS bit times
0x2 : GFLADJ_30MHZ_2
Frame length is 59520 HS bit times ...
0x1F : GFLADJ_30MHZ_31
Frame length is 59984 HS bit times
0x20 : GFLADJ_30MHZ_32
Frame length is 60000 HS bit times ...
0x3E : GFLADJ_30MHZ_62
Frame length is 60480 HS bit times
0x3F : GFLADJ_30MHZ_63
Frame length is 60496 HS bit times
End of enumeration elements list.
GFLADJ_30MHZ_REG_SEL : This bit selects whether to use a hard-coded value of 20h (32 decimal) or the value in GFLADJ[GFLADJ_30MHZ] to adjust the frame length for the SOF/ITP
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : GFLADJ_30MHZ_REG_SEL_0
The controller uses the hard coded value 20h (32 decimal) . which gives a SOF cycle time of 60000.
0x1 : GFLADJ_30MHZ_REG_SEL_1
The controller uses the value in GFLADJ[GFLADJ_30MHZ].
End of enumeration elements list.
GFLADJ_REFCLK_FLADJ : This bit indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk
bits : 8 - 21 (14 bit)
access : read-write
Device configuration register
address_offset : 0xC700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEVSPD : Device speed Indicates the speed at which the application requires the core to connect, or the maximum speed the application can support
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DEVSPD_0
High-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
0x1 : DEVSPD_1
Full-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
0x4 : DEVSPD_4
SuperSpeed (USB 3.0 PHY clock is 125 MHz or 250 MHz)
End of enumeration elements list.
DEVADDR : Device address The application must perform the following: Program this bit after every SetAddress request
bits : 3 - 9 (7 bit)
access : read-write
INTRNUM : Interrupt number Indicates interrupt/EventQ number on which non-endpoint-specific device-related interrupts (see DEVT) are generated
bits : 12 - 16 (5 bit)
access : read-write
NUMP : Number of receive buffers This bit indicates the number of receive buffers to be reported in the ACK TP
bits : 17 - 21 (5 bit)
access : read-write
LPMCAP : LPM capable The application uses this bit to control the USB 3
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : LPMCAP_0
LPM capability is not enabled
0x1 : LPMCAP_1
LPM capability is enabled
End of enumeration elements list.
IGMSTRMPP : Ignore stream PP This bit only affects stream-capable bulk endpoints
bits : 23 - 23 (1 bit)
access : read-write
Device control register
address_offset : 0xC704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTCTL : Test control The settings not defined are reserved.
bits : 1 - 4 (4 bit)
access : read-write
Enumeration:
0 : TSTCTL_0
Test mode disabled
0x1 : TSTCTL_1
Test_J mode
0x2 : TSTCTL_2
Test_K mode
0x3 : TSTCTL_3
Test_SE0_NAK mode
0x4 : TSTCTL_4
Test_Packet mode
0x5 : TSTCTL_5
Test_Force_Enable
End of enumeration elements list.
ULSTCHNGREQ : USB/Link state change request Software writes this bit to issue a USB/Link state change request
bits : 5 - 8 (4 bit)
access : write-only
ACCEPTU1ENA : Accept U1 enable On USB reset, hardware clears this bit to 0
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : ACCEPTU1ENA_0
Core rejects U1 except when Force_LinkPM_Accept bit is set (default)
0x1 : ACCEPTU1ENA_1
Core accepts transition to U1 state if nothing is pending on the application side
End of enumeration elements list.
INITU1ENA : Initiate U1 enable On USB reset, hardware clears this bit to 0
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : INITU1ENA_0
May not initiate U1 (default)
0x1 : INITU1ENA_1
May initiate U1
End of enumeration elements list.
ACCEPTU2ENA : Accept U2 enable On USB reset, hardware clears this bit to 0
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ACCEPTU2ENA_0
Reject U2 except when Force_LinkPM_Accept bit is set (default)
0x1 : ACCEPTU2ENA_1
Core accepts transition to U2 state if nothing is pending on the application side
End of enumeration elements list.
INITU2ENA : Initiate U2 enable On USB reset, hardware clears this bit to 0
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : INITU2ENA_0
May not initiate U2 (default)
0x1 : INITU2ENA_1
May initiate U2
End of enumeration elements list.
CSS : Controller save state This command is similar to the USBCMD[CSS] bit in host mode and initiates the save process
bits : 16 - 16 (1 bit)
access : read-write
CRS : Controller restore state This command is similar to the USBCMD[CRS] bit in host mode and initiates the restore process
bits : 17 - 17 (1 bit)
access : read-write
LPM_NYET_THRES : When LPM errata is enabled: LPM NYET response threshold handshake response to LPM token specified by device application
bits : 20 - 23 (4 bit)
access : read-write
HIRDTHRES : HIRD threshold The core asserts output signals utmi_l1_suspend_n and utmi_sleep_n on the basis of this signal
bits : 24 - 28 (5 bit)
access : read-write
CSFTRST : Core soft reset Resets all clock domains as follows: Clears the interrupts and all the CSRs except the following registers: GCTL, GUCTL, GSTS, GUID, GUSB2PHYCFG, GUSB3PIPECTL, DCFG, DCTL, DEVTEN, DSTS All module state machines (except the SoC bus slave unit) are reset to the IDLE state, and all the TXFIFOs and the RXFIFO are flushed
bits : 30 - 30 (1 bit)
access : read-write
RUN_STOP : The software writes 1 to this bit to start the device controller operation
bits : 31 - 31 (1 bit)
access : read-write
Device event enable register
address_offset : 0xC708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISSCONNEVTEN : Disconnect detected event enable
bits : 0 - 0 (1 bit)
access : read-write
USBRSTEVTEN : USB reset enable
bits : 1 - 1 (1 bit)
access : read-write
CONNECTDONEEVTEN : Connection done enable
bits : 2 - 2 (1 bit)
access : read-write
ULSTCNGEN : USB/Link state change event enable
bits : 3 - 3 (1 bit)
access : read-write
WKUPEVTEN : Resume/Remote wakeup detected event enable
bits : 4 - 4 (1 bit)
access : read-write
U3L2L1SUSPEN : U3/L2-L1 suspend event enable
bits : 6 - 6 (1 bit)
access : read-write
SOFTEVTEN : Start of (micro)frame enable
bits : 7 - 7 (1 bit)
access : read-write
ERRTICERREVTEN : Erratic error event enable
bits : 9 - 9 (1 bit)
access : read-write
VENDEVTSTRCVDEN : Vendor device test LMP received rvent
bits : 12 - 12 (1 bit)
access : read-write
Device status register
address_offset : 0xC70C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CONNECTSPD : Connected speed Indicates the speed at which the USB 3
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : CONNECTSPD_0
High-speed (PHY clock is running at 30 MHz or 60 MHz)
0x1 : CONNECTSPD_1
Full-speed (PHY clock is running at 30 MHz or 60 MHz)
0x2 : CONNECTSPD_2
Low-speed (PHY clock is running at 6 MHz)
0x3 : CONNECTSPD_3
Full-speed (PHY clock is running at 48 MHz)
0x4 : CONNECTSPD_4
SuperSpeed (PHY clock is running at 125 MHz or 250 MHz)
End of enumeration elements list.
SOFFN : Frame/microframe number of the received SOF When the core is operating at high-speed, [16:6] indicates the frame number [5:3] indicates the microframe number When the core is operating at high-speed, [16:14] is not used
bits : 3 - 16 (14 bit)
access : read-only
RXFIFOEMPTY : RXFIFO empty
bits : 17 - 17 (1 bit)
access : read-only
USBLNKST : USB/Link state In SS mode: LTSSM State 4'h0 U0 4'h1 U1 4'h2 U2 4'h3 U3 4'h4 SS_DIS 4'h5 RX_DET 4'h6 SS_INACT 4'h7 POLL 4'h8 RECOV 4'h9 HRESET 4'hA CMPLY 4'hB LPBK 4'hF Resume/Reset In HS/FS/LS mode
bits : 18 - 21 (4 bit)
access : read-only
DEVCTRLHLT : Device controller halted This bit is set to 0 when the DCTL[RUN_STOP] bit is set to 1
bits : 22 - 22 (1 bit)
access : read-only
COREIDLE : Core idle The bit indicates that the core finished transferring all RXFIFO data to system memory, writing out all completed descriptors, and all event counts are zero
bits : 23 - 23 (1 bit)
access : read-only
SSS : Save state status This bit is similar to the USBSTS[SSS] in host mode
bits : 24 - 24 (1 bit)
access : read-only
RSS : Restore state status This bit is similar to the USBSTS[RSS] in host mode
bits : 25 - 25 (1 bit)
access : read-only
Device generic command parameter register
address_offset : 0xC710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter for device command
bits : 0 - 31 (32 bit)
access : read-write
Device generic command register
address_offset : 0xC714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform
bits : 0 - 7 (8 bit)
access : read-write
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic command completion event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active The software sets this bit to 1 to enable the device controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
CMDSTATUS : Command status
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : CMDSTATUS_0
Indicates command success
0x1 : CMDSTATUS_1
CmdErr, indicates that the device controller encountered an error while processing the command
End of enumeration elements list.
Device active USB endpoint enable register
address_offset : 0xC720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBACTEP : USB active endpoints This bit indicates if a USB endpoint is active in the current configuration and interface
bits : 0 - 7 (8 bit)
access : read-write
Device physical endpoint-n command parameter 2 register
address_offset : 0xC800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 2
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 1 register
address_offset : 0xC804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 1
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 0 register
address_offset : 0xC808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 0
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command register
address_offset : 0xC80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : CMDTYP_1
Set endpoint configuration: 64-bit or 96-bit parameter
0x2 : CMDTYP_2
Set endpoint transfer resource configuration: 32-bit parameter
0x3 : CMDTYP_3
Get endpoint state: no parameter needed
0x4 : CMDTYP_4
Set stall: no parameter needed
0x5 : CMDTYP_5
Clear stall (see set stall): no parameter needed
0x6 : CMDTYP_6
Start transfer: 64-bit parameter
0x7 : CMDTYP_7
Update transfer: no parameter needed
0x8 : CMDTYP_8
End transfer: no parameter needed
0x9 : CMDTYP_9
Start new configuration: no parameter needed
End of enumeration elements list.
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic endpoint command complete event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active Software sets this bit to 1 to enable the device endpoint controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
HIPRI_FORCERM : HighPriority/ForceRM HighPriority: Only valid for start transfer command ForceRM: Only valid for end transfer command ClearPendIN: Only valid for clear stall command; software sets this bit to clear any pending IN transaction (on that endpoint) stuck at the lower layers when a clear stall command is issued
bits : 11 - 11 (1 bit)
access : read-write
CMDSTATUS : Command completion status Additional information about the completion of this command is available in this bit
bits : 12 - 15 (4 bit)
access : read-write
COMMANDPARAM : Command parameters
bits : 16 - 31 (16 bit)
access : read-write
Device physical endpoint-n command parameter 2 register
address_offset : 0xC810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 2
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 1 register
address_offset : 0xC814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 1
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 0 register
address_offset : 0xC818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 0
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command register
address_offset : 0xC81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : CMDTYP_1
Set endpoint configuration: 64-bit or 96-bit parameter
0x2 : CMDTYP_2
Set endpoint transfer resource configuration: 32-bit parameter
0x3 : CMDTYP_3
Get endpoint state: no parameter needed
0x4 : CMDTYP_4
Set stall: no parameter needed
0x5 : CMDTYP_5
Clear stall (see set stall): no parameter needed
0x6 : CMDTYP_6
Start transfer: 64-bit parameter
0x7 : CMDTYP_7
Update transfer: no parameter needed
0x8 : CMDTYP_8
End transfer: no parameter needed
0x9 : CMDTYP_9
Start new configuration: no parameter needed
End of enumeration elements list.
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic endpoint command complete event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active Software sets this bit to 1 to enable the device endpoint controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
HIPRI_FORCERM : HighPriority/ForceRM HighPriority: Only valid for start transfer command ForceRM: Only valid for end transfer command ClearPendIN: Only valid for clear stall command; software sets this bit to clear any pending IN transaction (on that endpoint) stuck at the lower layers when a clear stall command is issued
bits : 11 - 11 (1 bit)
access : read-write
CMDSTATUS : Command completion status Additional information about the completion of this command is available in this bit
bits : 12 - 15 (4 bit)
access : read-write
COMMANDPARAM : Command parameters
bits : 16 - 31 (16 bit)
access : read-write
Device physical endpoint-n command parameter 2 register
address_offset : 0xC820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 2
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 1 register
address_offset : 0xC824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 1
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 0 register
address_offset : 0xC828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 0
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command register
address_offset : 0xC82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : CMDTYP_1
Set endpoint configuration: 64-bit or 96-bit parameter
0x2 : CMDTYP_2
Set endpoint transfer resource configuration: 32-bit parameter
0x3 : CMDTYP_3
Get endpoint state: no parameter needed
0x4 : CMDTYP_4
Set stall: no parameter needed
0x5 : CMDTYP_5
Clear stall (see set stall): no parameter needed
0x6 : CMDTYP_6
Start transfer: 64-bit parameter
0x7 : CMDTYP_7
Update transfer: no parameter needed
0x8 : CMDTYP_8
End transfer: no parameter needed
0x9 : CMDTYP_9
Start new configuration: no parameter needed
End of enumeration elements list.
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic endpoint command complete event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active Software sets this bit to 1 to enable the device endpoint controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
HIPRI_FORCERM : HighPriority/ForceRM HighPriority: Only valid for start transfer command ForceRM: Only valid for end transfer command ClearPendIN: Only valid for clear stall command; software sets this bit to clear any pending IN transaction (on that endpoint) stuck at the lower layers when a clear stall command is issued
bits : 11 - 11 (1 bit)
access : read-write
CMDSTATUS : Command completion status Additional information about the completion of this command is available in this bit
bits : 12 - 15 (4 bit)
access : read-write
COMMANDPARAM : Command parameters
bits : 16 - 31 (16 bit)
access : read-write
Device physical endpoint-n command parameter 2 register
address_offset : 0xC830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 2
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 1 register
address_offset : 0xC834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 1
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 0 register
address_offset : 0xC838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 0
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command register
address_offset : 0xC83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : CMDTYP_1
Set endpoint configuration: 64-bit or 96-bit parameter
0x2 : CMDTYP_2
Set endpoint transfer resource configuration: 32-bit parameter
0x3 : CMDTYP_3
Get endpoint state: no parameter needed
0x4 : CMDTYP_4
Set stall: no parameter needed
0x5 : CMDTYP_5
Clear stall (see set stall): no parameter needed
0x6 : CMDTYP_6
Start transfer: 64-bit parameter
0x7 : CMDTYP_7
Update transfer: no parameter needed
0x8 : CMDTYP_8
End transfer: no parameter needed
0x9 : CMDTYP_9
Start new configuration: no parameter needed
End of enumeration elements list.
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic endpoint command complete event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active Software sets this bit to 1 to enable the device endpoint controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
HIPRI_FORCERM : HighPriority/ForceRM HighPriority: Only valid for start transfer command ForceRM: Only valid for end transfer command ClearPendIN: Only valid for clear stall command; software sets this bit to clear any pending IN transaction (on that endpoint) stuck at the lower layers when a clear stall command is issued
bits : 11 - 11 (1 bit)
access : read-write
CMDSTATUS : Command completion status Additional information about the completion of this command is available in this bit
bits : 12 - 15 (4 bit)
access : read-write
COMMANDPARAM : Command parameters
bits : 16 - 31 (16 bit)
access : read-write
Device physical endpoint-n command parameter 2 register
address_offset : 0xC840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 2
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 1 register
address_offset : 0xC844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 1
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 0 register
address_offset : 0xC848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 0
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command register
address_offset : 0xC84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : CMDTYP_1
Set endpoint configuration: 64-bit or 96-bit parameter
0x2 : CMDTYP_2
Set endpoint transfer resource configuration: 32-bit parameter
0x3 : CMDTYP_3
Get endpoint state: no parameter needed
0x4 : CMDTYP_4
Set stall: no parameter needed
0x5 : CMDTYP_5
Clear stall (see set stall): no parameter needed
0x6 : CMDTYP_6
Start transfer: 64-bit parameter
0x7 : CMDTYP_7
Update transfer: no parameter needed
0x8 : CMDTYP_8
End transfer: no parameter needed
0x9 : CMDTYP_9
Start new configuration: no parameter needed
End of enumeration elements list.
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic endpoint command complete event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active Software sets this bit to 1 to enable the device endpoint controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
HIPRI_FORCERM : HighPriority/ForceRM HighPriority: Only valid for start transfer command ForceRM: Only valid for end transfer command ClearPendIN: Only valid for clear stall command; software sets this bit to clear any pending IN transaction (on that endpoint) stuck at the lower layers when a clear stall command is issued
bits : 11 - 11 (1 bit)
access : read-write
CMDSTATUS : Command completion status Additional information about the completion of this command is available in this bit
bits : 12 - 15 (4 bit)
access : read-write
COMMANDPARAM : Command parameters
bits : 16 - 31 (16 bit)
access : read-write
Device physical endpoint-n command parameter 2 register
address_offset : 0xC850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 2
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 1 register
address_offset : 0xC854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 1
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 0 register
address_offset : 0xC858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 0
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command register
address_offset : 0xC85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : CMDTYP_1
Set endpoint configuration: 64-bit or 96-bit parameter
0x2 : CMDTYP_2
Set endpoint transfer resource configuration: 32-bit parameter
0x3 : CMDTYP_3
Get endpoint state: no parameter needed
0x4 : CMDTYP_4
Set stall: no parameter needed
0x5 : CMDTYP_5
Clear stall (see set stall): no parameter needed
0x6 : CMDTYP_6
Start transfer: 64-bit parameter
0x7 : CMDTYP_7
Update transfer: no parameter needed
0x8 : CMDTYP_8
End transfer: no parameter needed
0x9 : CMDTYP_9
Start new configuration: no parameter needed
End of enumeration elements list.
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic endpoint command complete event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active Software sets this bit to 1 to enable the device endpoint controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
HIPRI_FORCERM : HighPriority/ForceRM HighPriority: Only valid for start transfer command ForceRM: Only valid for end transfer command ClearPendIN: Only valid for clear stall command; software sets this bit to clear any pending IN transaction (on that endpoint) stuck at the lower layers when a clear stall command is issued
bits : 11 - 11 (1 bit)
access : read-write
CMDSTATUS : Command completion status Additional information about the completion of this command is available in this bit
bits : 12 - 15 (4 bit)
access : read-write
COMMANDPARAM : Command parameters
bits : 16 - 31 (16 bit)
access : read-write
Device physical endpoint-n command parameter 2 register
address_offset : 0xC860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 2
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 1 register
address_offset : 0xC864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 1
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 0 register
address_offset : 0xC868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 0
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command register
address_offset : 0xC86C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : CMDTYP_1
Set endpoint configuration: 64-bit or 96-bit parameter
0x2 : CMDTYP_2
Set endpoint transfer resource configuration: 32-bit parameter
0x3 : CMDTYP_3
Get endpoint state: no parameter needed
0x4 : CMDTYP_4
Set stall: no parameter needed
0x5 : CMDTYP_5
Clear stall (see set stall): no parameter needed
0x6 : CMDTYP_6
Start transfer: 64-bit parameter
0x7 : CMDTYP_7
Update transfer: no parameter needed
0x8 : CMDTYP_8
End transfer: no parameter needed
0x9 : CMDTYP_9
Start new configuration: no parameter needed
End of enumeration elements list.
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic endpoint command complete event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active Software sets this bit to 1 to enable the device endpoint controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
HIPRI_FORCERM : HighPriority/ForceRM HighPriority: Only valid for start transfer command ForceRM: Only valid for end transfer command ClearPendIN: Only valid for clear stall command; software sets this bit to clear any pending IN transaction (on that endpoint) stuck at the lower layers when a clear stall command is issued
bits : 11 - 11 (1 bit)
access : read-write
CMDSTATUS : Command completion status Additional information about the completion of this command is available in this bit
bits : 12 - 15 (4 bit)
access : read-write
COMMANDPARAM : Command parameters
bits : 16 - 31 (16 bit)
access : read-write
Device physical endpoint-n command parameter 2 register
address_offset : 0xC870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 2
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 1 register
address_offset : 0xC874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 1
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command parameter 0 register
address_offset : 0xC878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : Parameter 0
bits : 0 - 31 (32 bit)
access : read-write
Device physical endpoint-n command register
address_offset : 0xC87C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDTYP : Command type Specifies the type of command the software driver is requesting the core to perform.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : CMDTYP_1
Set endpoint configuration: 64-bit or 96-bit parameter
0x2 : CMDTYP_2
Set endpoint transfer resource configuration: 32-bit parameter
0x3 : CMDTYP_3
Get endpoint state: no parameter needed
0x4 : CMDTYP_4
Set stall: no parameter needed
0x5 : CMDTYP_5
Clear stall (see set stall): no parameter needed
0x6 : CMDTYP_6
Start transfer: 64-bit parameter
0x7 : CMDTYP_7
Update transfer: no parameter needed
0x8 : CMDTYP_8
End transfer: no parameter needed
0x9 : CMDTYP_9
Start new configuration: no parameter needed
End of enumeration elements list.
CMDIOC : Command interrupt on complete When this bit is set, the device controller issues a generic endpoint command complete event after executing the command
bits : 8 - 8 (1 bit)
access : read-write
CMDACT : Command active Software sets this bit to 1 to enable the device endpoint controller to execute the generic command
bits : 10 - 10 (1 bit)
access : read-write
HIPRI_FORCERM : HighPriority/ForceRM HighPriority: Only valid for start transfer command ForceRM: Only valid for end transfer command ClearPendIN: Only valid for clear stall command; software sets this bit to clear any pending IN transaction (on that endpoint) stuck at the lower layers when a clear stall command is issued
bits : 11 - 11 (1 bit)
access : read-write
CMDSTATUS : Command completion status Additional information about the completion of this command is available in this bit
bits : 12 - 15 (4 bit)
access : read-write
COMMANDPARAM : Command parameters
bits : 16 - 31 (16 bit)
access : read-write
OTG configuration register
address_offset : 0xCC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRPCAP : SRP capability The application uses this bit to control the USB 3
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRPCAP_0
SRP capability is not enabled
0x1 : SRPCAP_1
SRP capability is enabled
End of enumeration elements list.
HNPCAP : HNP capability The application uses this bit to control the USB 3.0 core's HNP capabilities.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HNPCAP_0
HNP capability is not enabled
0x1 : HNPCAP_1
HNP capability is enabled
End of enumeration elements list.
OTGSFTRSTMSK : OTG soft reset mask This bit is used to mask specific soft resets from affecting the OTG functionality of the core
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : OTGSFTRSTMSK_0
The xHCI-based USBCMD[HCRST] and DCTL[CSFTRST] resets the OTG logic of the core
0x1 : OTGSFTRSTMSK_1
The xHCI-based USBCMD[HCRST] and DCTL[CSFTRST] are masked from the OTG logic of the core
End of enumeration elements list.
DISPRTPWRCUTOFF : OTG disable port power cut off
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISPRTPWRCUTOFF_0
The core automatically switches-off the VBUS by clearing the OCTL[PRTPWRCTL] after A_WAIT_BCON timeout whenever the port is disconnected in disconnected state.
0x1 : DISPRTPWRCUTOFF_1
The core maintains VBUS ON even after A_WAIT_BCON timeout when port is in disconnected state. The core remains in A_WAIT_BCON state continuously waiting for a Connect.
End of enumeration elements list.
OTG control register
address_offset : 0xCC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTSETHNPEN : Host set HNP enable The application sets this bit in HS/FS mode, when it has successfully enabled HNP (using the SetFeature
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HSTSETHNPEN_0
Host set HNP is not enabled
0x1 : HSTSETHNPEN_1
Host set HNP is enabled
End of enumeration elements list.
DEVSETHNPEN : Device set HNP enable 0: HNP is not enabled in the application 1: HNP is enabled in the application The application sets this bit in HS/FS mode, when it successfully receives a SetFeature
bits : 1 - 1 (1 bit)
access : read-write
TERMSELDLPULSE : TermSel DLine pulsing selection This bit selects utmi_termselect to drive data line pulse during SRP
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TERMSELDLPULSE_0
Data line pulsing using utmi_txvalid (default)
0x1 : TERMSELDLPULSE_1
Data line pulsing using utmi_termsel
End of enumeration elements list.
SESREQ : Session request The application sets this bit to initiate a session request on the USB
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
0 : SESREQ_0
No session request
0x1 : SESREQ_1
Session request
End of enumeration elements list.
HNPREQ : HNP request The application sets this bit to initiate a HNP request to the connected USB host
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : HNPREQ_0
No HNP request
0x1 : HNPREQ_1
HNP request
End of enumeration elements list.
PRTPWRCTL : Port power control Application sets this bit to initiate VBUS drive when it is an A- device
bits : 5 - 5 (1 bit)
access : read-write
PERIMODE : Peripheral mode Application uses this bit to program the core to work as a peripheral or as a host.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : PERIMODE_0
The OTG device acts as a host
0x1 : PERIMODE_1
The OTG device acts as a peripheral
End of enumeration elements list.
OTG events register
address_offset : 0xCC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OEVTERROR : OTG event error There are no errors currently defined.
bits : 0 - 0 (1 bit)
access : read-write
SESREQSTS : Session request status Ignore this bit.
bits : 1 - 1 (1 bit)
access : read-only
HSTNEGSTS : Host negotiation status The core updates this bit when any of the following bits is set: OEVTEN[OTGADEVHNPCHNGEVNT] OEVTEN[OTGBDEVHNPCHNGEVNT] This bit indicates host negotiation success or failure
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : HSTNEGSTS_0
Host negotiation failure. In A-device, for HS/FS, this indicates an imminent end of session indication from the core. In B-device, for HS/LS, it indicates that the timer used to wait for an A-device to signal a connection (b_ase0_brst_tmout in OTG 2.0) timed out resulting in B-device staying as B-peripheral.
0x1 : HSTNEGSTS_1
Host negotiation success. This indicates that the host negotiation was successful.
End of enumeration elements list.
BSESVLD : B-Session valid Indicates the device mode transceiver status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : BSESVLD_0
B-session is not valid
0x1 : BSESVLD_1
B-session is valid
End of enumeration elements list.
OTGBDEVVBUSCHNGEVNT : VBUS change event Set in B-device mode only
bits : 8 - 8 (1 bit)
access : read-write
OTGBDEVSESSVLDDETEVNT : Session valid detected event Set in B-device mode only
bits : 9 - 9 (1 bit)
access : read-write
OTGBDEVHNPCHNGEVNT : B-device HNP change event Set in B-device mode only
bits : 10 - 10 (1 bit)
access : read-write
OTGBDEVBHOSTENDEVNT : B-Device B-Host end event Set in B-device mode only
bits : 11 - 11 (1 bit)
access : read-write
OTGADEVSESSENDDETEVNT : Session end detected event Set in A-device mode only
bits : 16 - 16 (1 bit)
access : read-write
OTGADEVSRPDETEVNT : SRP detect event Set in A-device mode only
bits : 17 - 17 (1 bit)
access : read-write
OTGADEVHNPCHNGEVNT : A-Dev HNP change event Set in A-device mode only
bits : 18 - 18 (1 bit)
access : read-write
OTGADEVHOSTEVNT : A-device host event Set in A-device mode only
bits : 19 - 19 (1 bit)
access : read-write
OTGADEVBHOSTENDEVNT : A-device B-Host end event Set in A-device mode only
bits : 20 - 20 (1 bit)
access : read-write
OTGADEVIDLEEVNT : A-device A-IDLE event Set in A-device mode only
bits : 21 - 21 (1 bit)
access : read-write
OTGCONIDSTSCHNGEVNT : Connector ID status change event Set in both A-device/B-device mode
bits : 24 - 24 (1 bit)
access : read-write
OTGDEVRUNSTPSETEVNT : OTG device run stop set event This event is set when the device driver programs the DCTL[RUN_STOP] to 1
bits : 26 - 26 (1 bit)
access : read-write
OTGXHCIRUNSTPSETEVNT : OTG host run stop set event This event is set when the host driver programs the USBCMD[R/S] bit to 1
bits : 27 - 27 (1 bit)
access : read-write
DEVICEMODE : Device mode Indicates whether the device is in A-device or B-device mode based on utmiotg_iddig The rest of the OTG event information bits (OTGxxxxEVTINFO) in OEVT register are based on the contents of this bit
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : DEVICEMODE_0
A-device mode
0x1 : DEVICEMODE_1
B-device mode
End of enumeration elements list.
OTG events enable register
address_offset : 0xCC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTGBDEVVBUSCHNGEVNTEN : OTGBDEVEVTINFOEN[0] VBUS change event enable (OTGBDEVVBUSCHNGEVNTEN) When this bit is set, OEVT[OTGBDEVVBUSCHNGEVNT] is enabled
bits : 8 - 8 (1 bit)
access : read-write
OTGBDEVSESSVLDDETEVNTEN : OTGBDEVEVTINFOEN[1] Session valid detected event enable (OTGBDEVSESSVLDDETEVNTEN) Set in B-device mode only
bits : 9 - 9 (1 bit)
access : read-write
OTGBDEVHNPCHNGEVNTEN : OTGBDEVEVTINFOEN[2] B-device HNP change event enable (OTGBDEVHNPCHNGEVNTEN) When this bit is set, OEVT[OTGBDEVHNPCHNGEVNT] is enabled
bits : 10 - 10 (1 bit)
access : read-write
OTGBDEVBHOSTENDEVNTEN : OTGBDEVEVTINFOEN[3] B-device B-host end event enable (OTGBDEVBHOSTENDEVNTEN) When this bit is set, OEVT[OTGBDEVHOSTENDEVNT] is enabled
bits : 11 - 11 (1 bit)
access : read-write
OTGADEVSESSENDDETEVNTEN : OTGADEVEVTINFOEN[0] Session end detected event enable (OTGADEVSESSENDDETEVNTEN) When this bit is set, OEVT[OTGADEVSESSENDEVNT] is enabled
bits : 16 - 16 (1 bit)
access : read-write
OTGADEVSRPDETEVNTEN : OTGADEVEVTINFOEN[1] SRP detect event enable (OTGADEVSRPDETEVNTEN)
bits : 17 - 17 (1 bit)
access : read-write
OTGADEVHNPCHNGEVNTEN : OTGADEVEVTINFOEN[2] A-Device HNP change event enable (OTGADEVHNPCHNGEVNTEN) When this bit is set, OEVT[OTGADEVHNPCHNGEVNT] is enabled
bits : 18 - 18 (1 bit)
access : read-write
OTGADEVHOSTEVNTEN : OTGADEVEVTINFOEN[3] A-device host event (OTGADEVHOSTEVNTEN) When this bit is set, OEVT[OTGADEVHOSTEVNT] is enabled
bits : 19 - 19 (1 bit)
access : read-write
OTGADEVBHOSTENDEVNTEN : OTGADEVEVTINFOEN[4] A-device B-host end event enable (OTGADEVBHOSTENDEVNTEN) When this bit is set, OEVT[OTGADEVBHOSTENDEVNT] is enabled
bits : 20 - 20 (1 bit)
access : read-write
OTGADEVIDLEEVNTEN : OTGADEVEVTINFOEN[5] A-device A-IDLE event (OTGADEVIDLEEVNTEN) When this bit is set, OEVT[OTGADEVIDLEEVNT] is enabled
bits : 21 - 21 (1 bit)
access : read-write
HRRINITNOTIFEVNTEN : OTGCOMMONEVTINFOEN[1] HRRINITNOTIF event enable (HRRINITNOTIFEVNTEN)
bits : 22 - 22 (1 bit)
access : read-write
HRRCONFNOTIFEVNTEN : OTGCOMMONEVTINFOEN[2] HRRCONFNOTIF event enable (HRRCONFNOTIFEVNTEN)
bits : 23 - 23 (1 bit)
access : read-write
OTGCONIDSTSCHNGEVNTEN : OTGCOMMONEVTINFOEN[0] Connector ID status change event enable (OTGCONIDSTSCHNGEVNTEN)
bits : 24 - 24 (1 bit)
access : read-write
OTGDEVRUNSTPSETEVNTEN : OTG device run stop set event enable When this bit is set, OEVT[DEVRUNSTPSET] event is enabled
bits : 26 - 26 (1 bit)
access : read-write
OTGXHCIRUNSTPSETEVNTEN : OTG host run stop set event enable When this bit is set, OEVT[XHCIRUNSTPSET] event is enabled
bits : 27 - 27 (1 bit)
access : read-write
OTG status register
address_offset : 0xCC10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CONIDSTS : Connector ID status The reset value of this bit depends on the power-on value of the IDDIG signal from the PHY
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : CONIDSTS_0
The USB 3.0 core is in A-device mode
0x1 : CONIDSTS_1
The USB 3.0 core is in B-device mode
End of enumeration elements list.
ASESVLD : VBUS valid Indicates the host mode transceiver status.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : ASESVLD_0
A-session is not valid
0x1 : ASESVLD_1
A-session is valid
End of enumeration elements list.
BSESVLD : B-session valid Indicates the device mode transceiver status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : BSESVLD_0
B-session is not valid
0x1 : BSESVLD_1
B-session is valid
End of enumeration elements list.
XHCIPRTPOWER : This bit reflects the PORTSC[PP] bit in the xHCI register.
bits : 3 - 3 (1 bit)
access : read-only
PERIPHERALSTATE : Indicates whether the core is acting as a peripheral or host.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : PERIPHERALSTATE_0
Host
0x1 : PERIPHERALSTATE_1
Peripheral
End of enumeration elements list.
XHCIRUNSTP : OTG host run stop set event This event is set when the host driver programs the [USBCMD[R/S]] to 1'b1
bits : 12 - 12 (1 bit)
access : read-only
DEVRUNSTP : This bit reflects the status of the DCTL[RUN_STOP] bit.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : DEVRUNSTP_0
Device Run/Stop is set to 0
0x1 : DEVRUNSTP_1
Device Run/Stop is set to 1
End of enumeration elements list.
ADP configuration register
address_offset : 0xCC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRBDSCHG : Probe discharge These bits set the time for TADP_DSCHG
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : PRBDSCHG_0
4 ms
0x1 : PRBDSCHG_1
8 ms
0x2 : PRBDSCHG_2
16 ms
0x3 : PRBDSCHG_3
32 ms
End of enumeration elements list.
PRBDELTA : Probe delta These bits set the resolution for RTIM value
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : PRBDELTA_0
1 cycle
0x1 : PRBDELTA_1
2 cycles
0x2 : PRBDELTA_2
3 cycles
0x3 : PRBDELTA_3
4 cycles
End of enumeration elements list.
PRBPER : Probe period This bit sets the value of T_ADP_PRB
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : PRBPER_0
0.775 sec
0x1 : PRBPER_1
1.55 sec
0x2 : PRBPER_2
2.275 sec
End of enumeration elements list.
ADP control register
address_offset : 0xCC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WB : Write busy The application can read or write ADPCFG and ADPCTL registers only if this bit is cleared
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : WB_0
Write completed
0x1 : WB_1
Write in progress
End of enumeration elements list.
ADPRES : ADP reset When set to 1, the ADP controller is reset
bits : 25 - 25 (1 bit)
access : read-write
ADPEN : ADP enable When set to 1, the core performs either ADP probing or sensing based on ENAPRB and ENASNS
bits : 26 - 26 (1 bit)
access : read-write
ENASNS : Enable sense When set to 1 along with ADPEN, the core performs a sense operation.
bits : 27 - 27 (1 bit)
access : read-write
ENAPRB : Enable probe When set to 1 along with ADPEN, the core performs a probe operation.
bits : 28 - 28 (1 bit)
access : read-write
ADP event register
address_offset : 0xCC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTIM : Ramp time These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : RTIM_0
1 cycle
0x1 : RTIM_1
2 cycles
0x2 : RTIM_2
3 cycles ....
0xFFFF : RTIM_65535
65536 cycles
End of enumeration elements list.
ADPRSTCMPLTEVNT : ADP reset complete event This event when set, indicates that the ADP reset command is successful.
bits : 25 - 25 (1 bit)
access : read-write
ADPTMOUTEVNT : ADP timeout event This event is relevant when ADP probe command is executed
bits : 26 - 26 (1 bit)
access : read-write
ADPSNSEVNT : ADPEVTINFO[3] ADP sense event (ADPSNSEVNT) When this event is set, it means that the VBUS voltage is greater than VADPSNS or VADPSNS is reached
bits : 27 - 27 (1 bit)
access : read-write
ADPPRBEVNT : ADPEVTINFO[4] ADP probe event (ADPPRBEVNT) When this event is set, it means that the VBUS voltage is greater than VADPPRB or VADPPRB is reached
bits : 28 - 28 (1 bit)
access : read-write
ADP event enable register
address_offset : 0xCC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADPRSTCMPLTEVNTEN : ADP reset complete event enable When this bit is set, the ADPEVT[ADPRSTCMPLTEVNT] bit is enabled.
bits : 25 - 25 (1 bit)
access : read-write
ADPTMOUTEVNTEN : ADP timeout event enable When this bit is set, the ADPEVT[ADPTMOUTEVNT] bit is enabled.
bits : 26 - 26 (1 bit)
access : read-write
ADPSNSEVNTEN : ADP sense event enable When this bit is set, the ADPEVT[ADPSNSEVNT] bit is enabled.
bits : 27 - 27 (1 bit)
access : read-write
ADPPRBEVNTEN : ADP probe event enable When this bit is set, the ADPEVT[ADPPRBEVNT] bit is enabled.
bits : 28 - 28 (1 bit)
access : read-write
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