Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected
Cache control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENCACHE : Cache enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENCACHE_0
Cache disabled
0x1 : ENCACHE_1
Cache enabled
End of enumeration elements list.
ENWRBUF : Enable Write Buffer
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ENWRBUF_0
Write buffer disabled
0x1 : ENWRBUF_1
Write buffer enabled
End of enumeration elements list.
PCCR2 : Forces all cacheable spaces to write through
bits : 2 - 2 (1 bit)
access : read-write
PCCR3 : Forces no allocation on cache misses (must also have ACCR2 asserted)
bits : 3 - 3 (1 bit)
access : read-write
INVW0 : Invalidate Way 0
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : INVW0_0
No operation
0x1 : INVW0_1
When setting the GO bit, invalidate all lines in way 0.
End of enumeration elements list.
PUSHW0 : Push Way 0
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : PUSHW0_0
No operation
0x1 : PUSHW0_1
When setting the GO bit, push all modified lines in way 0
End of enumeration elements list.
INVW1 : Invalidate Way 1
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : INVW1_0
No operation
0x1 : INVW1_1
When setting the GO bit, invalidate all lines in way 1
End of enumeration elements list.
PUSHW1 : Push Way 1
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : PUSHW1_0
No operation
0x1 : PUSHW1_1
When setting the GO bit, push all modified lines in way 1
End of enumeration elements list.
GO : Initiate Cache Command
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : GO_0
Write: no effect. Read: no cache command active.
0x1 : GO_1
Write: initiate command indicated by bits 27-24. Read: cache command active.
End of enumeration elements list.
Cache line control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGO : Initiate Cache Line Command
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LGO_0
Write: no effect. Read: no line command active.
0x1 : LGO_1
Write: initiate line command indicated by bits 27-24. Read: line command active.
End of enumeration elements list.
CACHEADDR : Cache address
bits : 2 - 12 (11 bit)
access : read-write
WSEL : Way select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : WSEL_0
Way 0
0x1 : WSEL_1
Way 1
End of enumeration elements list.
TDSEL : Tag/Data Select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TDSEL_0
Data
0x1 : TDSEL_1
Tag
End of enumeration elements list.
LCIVB : Line Command Initial Valid Bit
bits : 20 - 20 (1 bit)
access : read-only
LCIMB : Line Command Initial Modified Bit
bits : 21 - 21 (1 bit)
access : read-only
LCWAY : Line Command Way
bits : 22 - 22 (1 bit)
access : read-only
LCMD : Line Command
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : LCMD_0
Search and read or write
0x1 : LCMD_1
Invalidate
0x2 : LCMD_2
Push
0x3 : LCMD_3
Clear
End of enumeration elements list.
LADSEL : Line Address Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : LADSEL_0
Cache address
0x1 : LADSEL_1
Physical address
End of enumeration elements list.
LACC : Line access type
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : LACC_0
Read
0x1 : LACC_1
Write
End of enumeration elements list.
Cache search address register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGO : Initiate Cache Line Command
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LGO_0
Write: no effect. Read: no line command active.
0x1 : LGO_1
Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
End of enumeration elements list.
PHYADDR : Physical Address
bits : 2 - 31 (30 bit)
access : read-write
Cache control register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENCACHE : Cache enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENCACHE_0
Cache disabled
0x1 : ENCACHE_1
Cache enabled
End of enumeration elements list.
ENWRBUF : Enable Write Buffer
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ENWRBUF_0
Write buffer disabled
0x1 : ENWRBUF_1
Write buffer enabled
End of enumeration elements list.
INVW0 : Invalidate Way 0
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : INVW0_0
No operation
0x1 : INVW0_1
When setting the GO bit, invalidate all lines in way 0.
End of enumeration elements list.
PUSHW0 : Push Way 0
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : PUSHW0_0
No operation
0x1 : PUSHW0_1
When setting the GO bit, push all modified lines in way 0
End of enumeration elements list.
INVW1 : Invalidate Way 1
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : INVW1_0
No operation
0x1 : INVW1_1
When setting the GO bit, invalidate all lines in way 1
End of enumeration elements list.
PUSHW1 : Push Way 1
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : PUSHW1_0
No operation
0x1 : PUSHW1_1
When setting the GO bit, push all modified lines in way 1
End of enumeration elements list.
GO : Initiate Cache Command
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : GO_0
Write: no effect. Read: no cache command active.
0x1 : GO_1
Write: initiate command indicated by bits 27-24. Read: cache command active.
End of enumeration elements list.
Cache line control register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGO : Initiate Cache Line Command
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LGO_0
Write: no effect. Read: no line command active.
0x1 : LGO_1
Write: initiate line command indicated by bits 27-24. Read: line command active.
End of enumeration elements list.
CACHEADDR : Cache address
bits : 2 - 12 (11 bit)
access : read-write
WSEL : Way select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : WSEL_0
Way 0
0x1 : WSEL_1
Way 1
End of enumeration elements list.
TDSEL : Tag/Data Select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TDSEL_0
Data
0x1 : TDSEL_1
Tag
End of enumeration elements list.
LCIVB : Line Command Initial Valid Bit
bits : 20 - 20 (1 bit)
access : read-only
LCIMB : Line Command Initial Modified Bit
bits : 21 - 21 (1 bit)
access : read-only
LCWAY : Line Command Way
bits : 22 - 22 (1 bit)
access : read-only
LCMD : Line Command
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : LCMD_0
Search and read or write
0x1 : LCMD_1
Invalidate
0x2 : LCMD_2
Push
0x3 : LCMD_3
Clear
End of enumeration elements list.
LADSEL : Line Address Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : LADSEL_0
Cache address
0x1 : LADSEL_1
Physical address
End of enumeration elements list.
LACC : Line access type
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : LACC_0
Read
0x1 : LACC_1
Write
End of enumeration elements list.
Cache search address register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGO : Initiate Cache Line Command
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LGO_0
Write: no effect. Read: no line command active.
0x1 : LGO_1
Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
End of enumeration elements list.
PHYADDR : Physical Address
bits : 2 - 31 (30 bit)
access : read-write
Cache read/write value register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Cache read/write Data
bits : 0 - 31 (32 bit)
access : read-write
Cache read/write value register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Cache read/write Data
bits : 0 - 31 (32 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.