Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x534 byte (0x0)
mem_usage : registers
protection : not protected
SW_MUX_CTL_PAD_NAND_CE2_B SW MUX Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_CE2_B
Select mux mode: ALT0 mux port: CE2_B of instance: RAWNAND
0x1 : ALT1_QSPI_B_SS0_B
Select mux mode: ALT1 mux port: B_SS0_B of instance: QSPI
0x5 : ALT5_GPIO3_IO03
Select mux mode: ALT5 mux port: IO03 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_CE2_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_CE2_B
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_CE3_B SW MUX Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_CE3_B
Select mux mode: ALT0 mux port: CE3_B of instance: RAWNAND
0x1 : ALT1_QSPI_B_SS1_B
Select mux mode: ALT1 mux port: B_SS1_B of instance: QSPI
0x5 : ALT5_GPIO3_IO04
Select mux mode: ALT5 mux port: IO04 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_CE3_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_CE3_B
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_CLE SW MUX Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_CLE
Select mux mode: ALT0 mux port: CLE of instance: RAWNAND
0x1 : ALT1_QSPI_B_SCLK
Select mux mode: ALT1 mux port: B_SCLK of instance: QSPI
0x5 : ALT5_GPIO3_IO05
Select mux mode: ALT5 mux port: IO05 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_CLE is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_CLE
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DATA00 SW MUX Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DATA00
Select mux mode: ALT0 mux port: DATA00 of instance: RAWNAND
0x1 : ALT1_QSPI_A_DATA0
Select mux mode: ALT1 mux port: A_DATA0 of instance: QSPI
0x5 : ALT5_GPIO3_IO06
Select mux mode: ALT5 mux port: IO06 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DATA00 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DATA00
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DATA01
Select mux mode: ALT0 mux port: DATA01 of instance: RAWNAND
0x1 : ALT1_QSPI_A_DATA1
Select mux mode: ALT1 mux port: A_DATA1 of instance: QSPI
0x5 : ALT5_GPIO3_IO07
Select mux mode: ALT5 mux port: IO07 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DATA01 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DATA01
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DATA02 SW MUX Control Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DATA02
Select mux mode: ALT0 mux port: DATA02 of instance: RAWNAND
0x1 : ALT1_QSPI_A_DATA2
Select mux mode: ALT1 mux port: A_DATA2 of instance: QSPI
0x5 : ALT5_GPIO3_IO08
Select mux mode: ALT5 mux port: IO08 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DATA02 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DATA02
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DATA03 SW MUX Control Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DATA03
Select mux mode: ALT0 mux port: DATA03 of instance: RAWNAND
0x1 : ALT1_QSPI_A_DATA3
Select mux mode: ALT1 mux port: A_DATA3 of instance: QSPI
0x5 : ALT5_GPIO3_IO09
Select mux mode: ALT5 mux port: IO09 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DATA03 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DATA03
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DATA04 SW MUX Control Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DATA04
Select mux mode: ALT0 mux port: DATA04 of instance: RAWNAND
0x1 : ALT1_QSPI_B_DATA0
Select mux mode: ALT1 mux port: B_DATA0 of instance: QSPI
0x5 : ALT5_GPIO3_IO10
Select mux mode: ALT5 mux port: IO10 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DATA04 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DATA04
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DATA05 SW MUX Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DATA05
Select mux mode: ALT0 mux port: DATA05 of instance: RAWNAND
0x1 : ALT1_QSPI_B_DATA1
Select mux mode: ALT1 mux port: B_DATA1 of instance: QSPI
0x5 : ALT5_GPIO3_IO11
Select mux mode: ALT5 mux port: IO11 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DATA05 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DATA05
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DATA06 SW MUX Control Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DATA06
Select mux mode: ALT0 mux port: DATA06 of instance: RAWNAND
0x1 : ALT1_QSPI_B_DATA2
Select mux mode: ALT1 mux port: B_DATA2 of instance: QSPI
0x5 : ALT5_GPIO3_IO12
Select mux mode: ALT5 mux port: IO12 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DATA06 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DATA06
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DATA07 SW MUX Control Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DATA07
Select mux mode: ALT0 mux port: DATA07 of instance: RAWNAND
0x1 : ALT1_QSPI_B_DATA3
Select mux mode: ALT1 mux port: B_DATA3 of instance: QSPI
0x5 : ALT5_GPIO3_IO13
Select mux mode: ALT5 mux port: IO13 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DATA07 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DATA07
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_DQS SW MUX Control Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_DQS
Select mux mode: ALT0 mux port: DQS of instance: RAWNAND
0x1 : ALT1_QSPI_A_DQS
Select mux mode: ALT1 mux port: A_DQS of instance: QSPI
0x5 : ALT5_GPIO3_IO14
Select mux mode: ALT5 mux port: IO14 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_DQS is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_DQS
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_RE_B
Select mux mode: ALT0 mux port: RE_B of instance: RAWNAND
0x1 : ALT1_QSPI_B_DQS
Select mux mode: ALT1 mux port: B_DQS of instance: QSPI
0x5 : ALT5_GPIO3_IO15
Select mux mode: ALT5 mux port: IO15 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_RE_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_RE_B
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_READY_B
Select mux mode: ALT0 mux port: READY_B of instance: RAWNAND
0x5 : ALT5_GPIO3_IO16
Select mux mode: ALT5 mux port: IO16 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_READY_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_READY_B
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_WE_B
Select mux mode: ALT0 mux port: WE_B of instance: RAWNAND
0x5 : ALT5_GPIO3_IO17
Select mux mode: ALT5 mux port: IO17 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_WE_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_WE_B
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_WP_B SW MUX Control Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_WP_B
Select mux mode: ALT0 mux port: WP_B of instance: RAWNAND
0x5 : ALT5_GPIO3_IO18
Select mux mode: ALT5 mux port: IO18 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_WP_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_WP_B
End of enumeration elements list.
SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SION : Software Input On Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad PMIC_STBY_REQ is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad PMIC_STBY_REQ
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI5_RXFS SW MUX Control Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI5_RX_SYNC
Select mux mode: ALT0 mux port: RX_SYNC of instance: SAI5
0x1 : ALT1_SAI1_TX_DATA0
Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI1
0x5 : ALT5_GPIO3_IO19
Select mux mode: ALT5 mux port: IO19 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI5_RXFS is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI5_RXFS
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI5_RXC SW MUX Control Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI5_RX_BCLK
Select mux mode: ALT0 mux port: RX_BCLK of instance: SAI5
0x1 : ALT1_SAI1_TX_DATA1
Select mux mode: ALT1 mux port: TX_DATA1 of instance: SAI1
0x5 : ALT5_GPIO3_IO20
Select mux mode: ALT5 mux port: IO20 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI5_RXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI5_RXC
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI5_RXD0 SW MUX Control Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI5_RX_DATA0
Select mux mode: ALT0 mux port: RX_DATA0 of instance: SAI5
0x1 : ALT1_SAI1_TX_DATA2
Select mux mode: ALT1 mux port: TX_DATA2 of instance: SAI1
0x5 : ALT5_GPIO3_IO21
Select mux mode: ALT5 mux port: IO21 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI5_RXD0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI5_RXD0
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI5_RXD1 SW MUX Control Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI5_RX_DATA1
Select mux mode: ALT0 mux port: RX_DATA1 of instance: SAI5
0x1 : ALT1_SAI1_TX_DATA3
Select mux mode: ALT1 mux port: TX_DATA3 of instance: SAI1
0x2 : ALT2_SAI1_TX_SYNC
Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI1
0x3 : ALT3_SAI5_TX_SYNC
Select mux mode: ALT3 mux port: TX_SYNC of instance: SAI5
0x5 : ALT5_GPIO3_IO22
Select mux mode: ALT5 mux port: IO22 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI5_RXD1 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI5_RXD1
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI5_RXD2 SW MUX Control Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI5_RX_DATA2
Select mux mode: ALT0 mux port: RX_DATA2 of instance: SAI5
0x1 : ALT1_SAI1_TX_DATA4
Select mux mode: ALT1 mux port: TX_DATA4 of instance: SAI1
0x2 : ALT2_SAI1_TX_SYNC
Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI1
0x3 : ALT3_SAI5_TX_BCLK
Select mux mode: ALT3 mux port: TX_BCLK of instance: SAI5
0x5 : ALT5_GPIO3_IO23
Select mux mode: ALT5 mux port: IO23 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI5_RXD2 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI5_RXD2
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI5_RXD3 SW MUX Control Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI5_RX_DATA3
Select mux mode: ALT0 mux port: RX_DATA3 of instance: SAI5
0x1 : ALT1_SAI1_TX_DATA5
Select mux mode: ALT1 mux port: TX_DATA5 of instance: SAI1
0x2 : ALT2_SAI1_TX_SYNC
Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI1
0x3 : ALT3_SAI5_TX_DATA0
Select mux mode: ALT3 mux port: TX_DATA0 of instance: SAI5
0x5 : ALT5_GPIO3_IO24
Select mux mode: ALT5 mux port: IO24 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI5_RXD3 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI5_RXD3
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI5_MCLK SW MUX Control Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI5_MCLK
Select mux mode: ALT0 mux port: MCLK of instance: SAI5
0x1 : ALT1_SAI1_TX_BCLK
Select mux mode: ALT1 mux port: TX_BCLK of instance: SAI1
0x2 : ALT2_SAI4_MCLK
Select mux mode: ALT2 mux port: MCLK of instance: SAI4
0x5 : ALT5_GPIO3_IO25
Select mux mode: ALT5 mux port: IO25 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI5_MCLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI5_MCLK
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXFS SW MUX Control Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_SYNC
Select mux mode: ALT0 mux port: RX_SYNC of instance: SAI1
0x1 : ALT1_SAI5_RX_SYNC
Select mux mode: ALT1 mux port: RX_SYNC of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE_CLK
Select mux mode: ALT4 mux port: TRACE_CLK of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO00
Select mux mode: ALT5 mux port: IO00 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXFS is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXFS
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXC SW MUX Control Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_BCLK
Select mux mode: ALT0 mux port: RX_BCLK of instance: SAI1
0x1 : ALT1_SAI5_RX_BCLK
Select mux mode: ALT1 mux port: RX_BCLK of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE_CTL
Select mux mode: ALT4 mux port: TRACE_CTL of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO01
Select mux mode: ALT5 mux port: IO01 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXC
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXD0 SW MUX Control Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_DATA0
Select mux mode: ALT0 mux port: RX_DATA0 of instance: SAI1
0x1 : ALT1_SAI5_RX_DATA0
Select mux mode: ALT1 mux port: RX_DATA0 of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE0
Select mux mode: ALT4 mux port: TRACE0 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO02
Select mux mode: ALT5 mux port: IO02 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG0
Select mux mode: ALT6 mux port: BOOT_CFG0 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXD0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXD0
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXD1 SW MUX Control Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_DATA1
Select mux mode: ALT0 mux port: RX_DATA1 of instance: SAI1
0x1 : ALT1_SAI5_RX_DATA1
Select mux mode: ALT1 mux port: RX_DATA1 of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE1
Select mux mode: ALT4 mux port: TRACE1 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO03
Select mux mode: ALT5 mux port: IO03 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG1
Select mux mode: ALT6 mux port: BOOT_CFG1 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXD1 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXD1
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_DATA2
Select mux mode: ALT0 mux port: RX_DATA2 of instance: SAI1
0x1 : ALT1_SAI5_RX_DATA2
Select mux mode: ALT1 mux port: RX_DATA2 of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE2
Select mux mode: ALT4 mux port: TRACE2 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO04
Select mux mode: ALT5 mux port: IO04 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG2
Select mux mode: ALT6 mux port: BOOT_CFG2 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXD2 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXD2
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXD3 SW MUX Control Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_DATA3
Select mux mode: ALT0 mux port: RX_DATA3 of instance: SAI1
0x1 : ALT1_SAI5_RX_DATA3
Select mux mode: ALT1 mux port: RX_DATA3 of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE3
Select mux mode: ALT4 mux port: TRACE3 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO05
Select mux mode: ALT5 mux port: IO05 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG3
Select mux mode: ALT6 mux port: BOOT_CFG3 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXD3 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXD3
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXD4 SW MUX Control Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_DATA4
Select mux mode: ALT0 mux port: RX_DATA4 of instance: SAI1
0x1 : ALT1_SAI6_TX_BCLK
Select mux mode: ALT1 mux port: TX_BCLK of instance: SAI6
0x2 : ALT2_SAI6_RX_BCLK
Select mux mode: ALT2 mux port: RX_BCLK of instance: SAI6
0x4 : ALT4_CORESIGHT_TRACE4
Select mux mode: ALT4 mux port: TRACE4 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO06
Select mux mode: ALT5 mux port: IO06 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG4
Select mux mode: ALT6 mux port: BOOT_CFG4 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXD4 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXD4
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXD5 SW MUX Control Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_DATA5
Select mux mode: ALT0 mux port: RX_DATA5 of instance: SAI1
0x1 : ALT1_SAI6_TX_DATA0
Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI6
0x2 : ALT2_SAI6_RX_DATA0
Select mux mode: ALT2 mux port: RX_DATA0 of instance: SAI6
0x3 : ALT3_SAI1_RX_SYNC
Select mux mode: ALT3 mux port: RX_SYNC of instance: SAI1
0x4 : ALT4_CORESIGHT_TRACE5
Select mux mode: ALT4 mux port: TRACE5 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO07
Select mux mode: ALT5 mux port: IO07 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG5
Select mux mode: ALT6 mux port: BOOT_CFG5 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXD5 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXD5
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXD6 SW MUX Control Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_DATA6
Select mux mode: ALT0 mux port: RX_DATA6 of instance: SAI1
0x1 : ALT1_SAI6_TX_SYNC
Select mux mode: ALT1 mux port: TX_SYNC of instance: SAI6
0x2 : ALT2_SAI6_RX_SYNC
Select mux mode: ALT2 mux port: RX_SYNC of instance: SAI6
0x4 : ALT4_CORESIGHT_TRACE6
Select mux mode: ALT4 mux port: TRACE6 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO08
Select mux mode: ALT5 mux port: IO08 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG6
Select mux mode: ALT6 mux port: BOOT_CFG6 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXD6 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXD6
End of enumeration elements list.
SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SION : Software Input On Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad PMIC_ON_REQ is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad PMIC_ON_REQ
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_RXD7 SW MUX Control Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_RX_DATA7
Select mux mode: ALT0 mux port: RX_DATA7 of instance: SAI1
0x1 : ALT1_SAI6_MCLK
Select mux mode: ALT1 mux port: MCLK of instance: SAI6
0x2 : ALT2_SAI1_TX_SYNC
Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI1
0x3 : ALT3_SAI1_TX_DATA4
Select mux mode: ALT3 mux port: TX_DATA4 of instance: SAI1
0x4 : ALT4_CORESIGHT_TRACE7
Select mux mode: ALT4 mux port: TRACE7 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO09
Select mux mode: ALT5 mux port: IO09 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG7
Select mux mode: ALT6 mux port: BOOT_CFG7 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_RXD7 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_RXD7
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXFS SW MUX Control Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_SYNC
Select mux mode: ALT0 mux port: TX_SYNC of instance: SAI1
0x1 : ALT1_SAI5_TX_SYNC
Select mux mode: ALT1 mux port: TX_SYNC of instance: SAI5
0x4 : ALT4_CORESIGHT_EVENTO
Select mux mode: ALT4 mux port: EVENTO of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO10
Select mux mode: ALT5 mux port: IO10 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXFS is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXFS
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXC SW MUX Control Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_BCLK
Select mux mode: ALT0 mux port: TX_BCLK of instance: SAI1
0x1 : ALT1_SAI5_TX_BCLK
Select mux mode: ALT1 mux port: TX_BCLK of instance: SAI5
0x4 : ALT4_CORESIGHT_EVENTI
Select mux mode: ALT4 mux port: EVENTI of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO11
Select mux mode: ALT5 mux port: IO11 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXC
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXD0 SW MUX Control Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_DATA0
Select mux mode: ALT0 mux port: TX_DATA0 of instance: SAI1
0x1 : ALT1_SAI5_TX_DATA0
Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE8
Select mux mode: ALT4 mux port: TRACE8 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO12
Select mux mode: ALT5 mux port: IO12 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG8
Select mux mode: ALT6 mux port: BOOT_CFG8 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXD0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXD0
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXD1 SW MUX Control Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_DATA1
Select mux mode: ALT0 mux port: TX_DATA1 of instance: SAI1
0x1 : ALT1_SAI5_TX_DATA1
Select mux mode: ALT1 mux port: TX_DATA1 of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE9
Select mux mode: ALT4 mux port: TRACE9 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO13
Select mux mode: ALT5 mux port: IO13 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG9
Select mux mode: ALT6 mux port: BOOT_CFG9 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXD1 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXD1
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXD2 SW MUX Control Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_DATA2
Select mux mode: ALT0 mux port: TX_DATA2 of instance: SAI1
0x1 : ALT1_SAI5_TX_DATA2
Select mux mode: ALT1 mux port: TX_DATA2 of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE10
Select mux mode: ALT4 mux port: TRACE10 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO14
Select mux mode: ALT5 mux port: IO14 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG10
Select mux mode: ALT6 mux port: BOOT_CFG10 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXD2 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXD2
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXD3 SW MUX Control Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_DATA3
Select mux mode: ALT0 mux port: TX_DATA3 of instance: SAI1
0x1 : ALT1_SAI5_TX_DATA3
Select mux mode: ALT1 mux port: TX_DATA3 of instance: SAI5
0x4 : ALT4_CORESIGHT_TRACE11
Select mux mode: ALT4 mux port: TRACE11 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO15
Select mux mode: ALT5 mux port: IO15 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG11
Select mux mode: ALT6 mux port: BOOT_CFG11 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXD3 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXD3
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXD4 SW MUX Control Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_DATA4
Select mux mode: ALT0 mux port: TX_DATA4 of instance: SAI1
0x1 : ALT1_SAI6_RX_BCLK
Select mux mode: ALT1 mux port: RX_BCLK of instance: SAI6
0x2 : ALT2_SAI6_TX_BCLK
Select mux mode: ALT2 mux port: TX_BCLK of instance: SAI6
0x4 : ALT4_CORESIGHT_TRACE12
Select mux mode: ALT4 mux port: TRACE12 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO16
Select mux mode: ALT5 mux port: IO16 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG12
Select mux mode: ALT6 mux port: BOOT_CFG12 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXD4 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXD4
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXD5 SW MUX Control Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_DATA5
Select mux mode: ALT0 mux port: TX_DATA5 of instance: SAI1
0x1 : ALT1_SAI6_RX_DATA0
Select mux mode: ALT1 mux port: RX_DATA0 of instance: SAI6
0x2 : ALT2_SAI6_TX_DATA0
Select mux mode: ALT2 mux port: TX_DATA0 of instance: SAI6
0x4 : ALT4_CORESIGHT_TRACE13
Select mux mode: ALT4 mux port: TRACE13 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO17
Select mux mode: ALT5 mux port: IO17 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG13
Select mux mode: ALT6 mux port: BOOT_CFG13 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXD5 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXD5
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXD6 SW MUX Control Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_DATA6
Select mux mode: ALT0 mux port: TX_DATA6 of instance: SAI1
0x1 : ALT1_SAI6_RX_SYNC
Select mux mode: ALT1 mux port: RX_SYNC of instance: SAI6
0x2 : ALT2_SAI6_TX_SYNC
Select mux mode: ALT2 mux port: TX_SYNC of instance: SAI6
0x4 : ALT4_CORESIGHT_TRACE14
Select mux mode: ALT4 mux port: TRACE14 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO18
Select mux mode: ALT5 mux port: IO18 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG14
Select mux mode: ALT6 mux port: BOOT_CFG14 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXD6 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXD6
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_TXD7 SW MUX Control Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_TX_DATA7
Select mux mode: ALT0 mux port: TX_DATA7 of instance: SAI1
0x1 : ALT1_SAI6_MCLK
Select mux mode: ALT1 mux port: MCLK of instance: SAI6
0x4 : ALT4_CORESIGHT_TRACE15
Select mux mode: ALT4 mux port: TRACE15 of instance: CORESIGHT
0x5 : ALT5_GPIO4_IO19
Select mux mode: ALT5 mux port: IO19 of instance: GPIO4
0x6 : ALT6_SRC_BOOT_CFG15
Select mux mode: ALT6 mux port: BOOT_CFG15 of instance: SRC
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_TXD7 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_TXD7
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI1_MCLK
Select mux mode: ALT0 mux port: MCLK of instance: SAI1
0x1 : ALT1_SAI5_MCLK
Select mux mode: ALT1 mux port: MCLK of instance: SAI5
0x2 : ALT2_SAI1_TX_BCLK
Select mux mode: ALT2 mux port: TX_BCLK of instance: SAI1
0x5 : ALT5_GPIO4_IO20
Select mux mode: ALT5 mux port: IO20 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI1_MCLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI1_MCLK
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI2_RXFS SW MUX Control Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI2_RX_SYNC
Select mux mode: ALT0 mux port: RX_SYNC of instance: SAI2
0x1 : ALT1_SAI5_TX_SYNC
Select mux mode: ALT1 mux port: TX_SYNC of instance: SAI5
0x5 : ALT5_GPIO4_IO21
Select mux mode: ALT5 mux port: IO21 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI2_RXFS is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI2_RXFS
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI2_RXC SW MUX Control Register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI2_RX_BCLK
Select mux mode: ALT0 mux port: RX_BCLK of instance: SAI2
0x1 : ALT1_SAI5_TX_BCLK
Select mux mode: ALT1 mux port: TX_BCLK of instance: SAI5
0x5 : ALT5_GPIO4_IO22
Select mux mode: ALT5 mux port: IO22 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI2_RXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI2_RXC
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI2_RXD0 SW MUX Control Register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI2_RX_DATA0
Select mux mode: ALT0 mux port: RX_DATA0 of instance: SAI2
0x1 : ALT1_SAI5_TX_DATA0
Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI5
0x5 : ALT5_GPIO4_IO23
Select mux mode: ALT5 mux port: IO23 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI2_RXD0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI2_RXD0
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI2_TXFS SW MUX Control Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI2_TX_SYNC
Select mux mode: ALT0 mux port: TX_SYNC of instance: SAI2
0x1 : ALT1_SAI5_TX_DATA1
Select mux mode: ALT1 mux port: TX_DATA1 of instance: SAI5
0x5 : ALT5_GPIO4_IO24
Select mux mode: ALT5 mux port: IO24 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI2_TXFS is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI2_TXFS
End of enumeration elements list.
SW_MUX_CTL_PAD_ONOFF SW MUX Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SION : Software Input On Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ONOFF is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ONOFF
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI2_TXC SW MUX Control Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI2_TX_BCLK
Select mux mode: ALT0 mux port: TX_BCLK of instance: SAI2
0x1 : ALT1_SAI5_TX_DATA2
Select mux mode: ALT1 mux port: TX_DATA2 of instance: SAI5
0x5 : ALT5_GPIO4_IO25
Select mux mode: ALT5 mux port: IO25 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI2_TXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI2_TXC
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI2_TXD0 SW MUX Control Register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI2_TX_DATA0
Select mux mode: ALT0 mux port: TX_DATA0 of instance: SAI2
0x1 : ALT1_SAI5_TX_DATA3
Select mux mode: ALT1 mux port: TX_DATA3 of instance: SAI5
0x5 : ALT5_GPIO4_IO26
Select mux mode: ALT5 mux port: IO26 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI2_TXD0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI2_TXD0
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI2_MCLK SW MUX Control Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI2_MCLK
Select mux mode: ALT0 mux port: MCLK of instance: SAI2
0x1 : ALT1_SAI5_MCLK
Select mux mode: ALT1 mux port: MCLK of instance: SAI5
0x5 : ALT5_GPIO4_IO27
Select mux mode: ALT5 mux port: IO27 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI2_MCLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI2_MCLK
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI3_RXFS SW MUX Control Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI3_RX_SYNC
Select mux mode: ALT0 mux port: RX_SYNC of instance: SAI3
0x1 : ALT1_GPT1_CAPTURE1
Select mux mode: ALT1 mux port: CAPTURE1 of instance: GPT1
0x2 : ALT2_SAI5_RX_SYNC
Select mux mode: ALT2 mux port: RX_SYNC of instance: SAI5
0x5 : ALT5_GPIO4_IO28
Select mux mode: ALT5 mux port: IO28 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI3_RXFS is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI3_RXFS
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI3_RXC SW MUX Control Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI3_RX_BCLK
Select mux mode: ALT0 mux port: RX_BCLK of instance: SAI3
0x1 : ALT1_GPT1_CAPTURE2
Select mux mode: ALT1 mux port: CAPTURE2 of instance: GPT1
0x2 : ALT2_SAI5_RX_BCLK
Select mux mode: ALT2 mux port: RX_BCLK of instance: SAI5
0x5 : ALT5_GPIO4_IO29
Select mux mode: ALT5 mux port: IO29 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI3_RXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI3_RXC
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI3_RXD SW MUX Control Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI3_RX_DATA0
Select mux mode: ALT0 mux port: RX_DATA0 of instance: SAI3
0x1 : ALT1_GPT1_COMPARE1
Select mux mode: ALT1 mux port: COMPARE1 of instance: GPT1
0x2 : ALT2_SAI5_RX_DATA0
Select mux mode: ALT2 mux port: RX_DATA0 of instance: SAI5
0x5 : ALT5_GPIO4_IO30
Select mux mode: ALT5 mux port: IO30 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI3_RXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI3_RXD
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI3_TXFS SW MUX Control Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI3_TX_SYNC
Select mux mode: ALT0 mux port: TX_SYNC of instance: SAI3
0x1 : ALT1_GPT1_CLK
Select mux mode: ALT1 mux port: CLK of instance: GPT1
0x2 : ALT2_SAI5_RX_DATA1
Select mux mode: ALT2 mux port: RX_DATA1 of instance: SAI5
0x5 : ALT5_GPIO4_IO31
Select mux mode: ALT5 mux port: IO31 of instance: GPIO4
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI3_TXFS is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI3_TXFS
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI3_TXC SW MUX Control Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI3_TX_BCLK
Select mux mode: ALT0 mux port: TX_BCLK of instance: SAI3
0x1 : ALT1_GPT1_COMPARE2
Select mux mode: ALT1 mux port: COMPARE2 of instance: GPT1
0x2 : ALT2_SAI5_RX_DATA2
Select mux mode: ALT2 mux port: RX_DATA2 of instance: SAI5
0x5 : ALT5_GPIO5_IO00
Select mux mode: ALT5 mux port: IO00 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI3_TXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI3_TXC
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI3_TXD SW MUX Control Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI3_TX_DATA0
Select mux mode: ALT0 mux port: TX_DATA0 of instance: SAI3
0x1 : ALT1_GPT1_COMPARE3
Select mux mode: ALT1 mux port: COMPARE3 of instance: GPT1
0x2 : ALT2_SAI5_RX_DATA3
Select mux mode: ALT2 mux port: RX_DATA3 of instance: SAI5
0x5 : ALT5_GPIO5_IO01
Select mux mode: ALT5 mux port: IO01 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI3_TXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI3_TXD
End of enumeration elements list.
SW_MUX_CTL_PAD_SAI3_MCLK SW MUX Control Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SAI3_MCLK
Select mux mode: ALT0 mux port: MCLK of instance: SAI3
0x1 : ALT1_PWM4_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM4
0x2 : ALT2_SAI5_MCLK
Select mux mode: ALT2 mux port: MCLK of instance: SAI5
0x5 : ALT5_GPIO5_IO02
Select mux mode: ALT5 mux port: IO02 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SAI3_MCLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SAI3_MCLK
End of enumeration elements list.
SW_MUX_CTL_PAD_SPDIF_TX SW MUX Control Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SPDIF1_OUT
Select mux mode: ALT0 mux port: OUT of instance: SPDIF1
0x1 : ALT1_PWM3_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM3
0x5 : ALT5_GPIO5_IO03
Select mux mode: ALT5 mux port: IO03 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SPDIF_TX is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SPDIF_TX
End of enumeration elements list.
SW_MUX_CTL_PAD_SPDIF_RX SW MUX Control Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SPDIF1_IN
Select mux mode: ALT0 mux port: IN of instance: SPDIF1
0x1 : ALT1_PWM2_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM2
0x5 : ALT5_GPIO5_IO04
Select mux mode: ALT5 mux port: IO04 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SPDIF_RX is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SPDIF_RX
End of enumeration elements list.
SW_MUX_CTL_PAD_SPDIF_EXT_CLK SW MUX Control Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_SPDIF1_EXT_CLK
Select mux mode: ALT0 mux port: EXT_CLK of instance: SPDIF1
0x1 : ALT1_PWM1_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM1
0x5 : ALT5_GPIO5_IO05
Select mux mode: ALT5 mux port: IO05 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SPDIF_EXT_CLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SPDIF_EXT_CLK
End of enumeration elements list.
SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ECSPI1_SCLK
Select mux mode: ALT0 mux port: SCLK of instance: ECSPI1
0x1 : ALT1_UART3_RX
Select mux mode: ALT1 mux port: RX of instance: UART3
0x5 : ALT5_GPIO5_IO06
Select mux mode: ALT5 mux port: IO06 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ECSPI1_SCLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ECSPI1_SCLK
End of enumeration elements list.
SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ECSPI1_MOSI
Select mux mode: ALT0 mux port: MOSI of instance: ECSPI1
0x1 : ALT1_UART3_TX
Select mux mode: ALT1 mux port: TX of instance: UART3
0x5 : ALT5_GPIO5_IO07
Select mux mode: ALT5 mux port: IO07 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ECSPI1_MOSI is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ECSPI1_MOSI
End of enumeration elements list.
SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ECSPI1_MISO
Select mux mode: ALT0 mux port: MISO of instance: ECSPI1
0x1 : ALT1_UART3_CTS_B
Select mux mode: ALT1 mux port: CTS_B of instance: UART3
0x5 : ALT5_GPIO5_IO08
Select mux mode: ALT5 mux port: IO08 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ECSPI1_MISO is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ECSPI1_MISO
End of enumeration elements list.
SW_MUX_CTL_PAD_POR_B SW MUX Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SION : Software Input On Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad POR_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad POR_B
End of enumeration elements list.
SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ECSPI1_SS0
Select mux mode: ALT0 mux port: SS0 of instance: ECSPI1
0x1 : ALT1_UART3_RTS_B
Select mux mode: ALT1 mux port: RTS_B of instance: UART3
0x5 : ALT5_GPIO5_IO09
Select mux mode: ALT5 mux port: IO09 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ECSPI1_SS0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ECSPI1_SS0
End of enumeration elements list.
SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ECSPI2_SCLK
Select mux mode: ALT0 mux port: SCLK of instance: ECSPI2
0x1 : ALT1_UART4_RX
Select mux mode: ALT1 mux port: RX of instance: UART4
0x5 : ALT5_GPIO5_IO10
Select mux mode: ALT5 mux port: IO10 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ECSPI2_SCLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ECSPI2_SCLK
End of enumeration elements list.
SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ECSPI2_MOSI
Select mux mode: ALT0 mux port: MOSI of instance: ECSPI2
0x1 : ALT1_UART4_TX
Select mux mode: ALT1 mux port: TX of instance: UART4
0x5 : ALT5_GPIO5_IO11
Select mux mode: ALT5 mux port: IO11 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ECSPI2_MOSI is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ECSPI2_MOSI
End of enumeration elements list.
SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ECSPI2_MISO
Select mux mode: ALT0 mux port: MISO of instance: ECSPI2
0x1 : ALT1_UART4_CTS_B
Select mux mode: ALT1 mux port: CTS_B of instance: UART4
0x5 : ALT5_GPIO5_IO12
Select mux mode: ALT5 mux port: IO12 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ECSPI2_MISO is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ECSPI2_MISO
End of enumeration elements list.
SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ECSPI2_SS0
Select mux mode: ALT0 mux port: SS0 of instance: ECSPI2
0x1 : ALT1_UART4_RTS_B
Select mux mode: ALT1 mux port: RTS_B of instance: UART4
0x5 : ALT5_GPIO5_IO13
Select mux mode: ALT5 mux port: IO13 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ECSPI2_SS0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ECSPI2_SS0
End of enumeration elements list.
SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_I2C1_SCL
Select mux mode: ALT0 mux port: SCL of instance: I2C1
0x1 : ALT1_ENET1_MDC
Select mux mode: ALT1 mux port: MDC of instance: ENET1
0x5 : ALT5_GPIO5_IO14
Select mux mode: ALT5 mux port: IO14 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad I2C1_SCL is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad I2C1_SCL
End of enumeration elements list.
SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_I2C1_SDA
Select mux mode: ALT0 mux port: SDA of instance: I2C1
0x1 : ALT1_ENET1_MDIO
Select mux mode: ALT1 mux port: MDIO of instance: ENET1
0x5 : ALT5_GPIO5_IO15
Select mux mode: ALT5 mux port: IO15 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad I2C1_SDA is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad I2C1_SDA
End of enumeration elements list.
SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_I2C2_SCL
Select mux mode: ALT0 mux port: SCL of instance: I2C2
0x1 : ALT1_ENET1_1588_EVENT1_IN
Select mux mode: ALT1 mux port: 1588_EVENT1_IN of instance: ENET1
0x5 : ALT5_GPIO5_IO16
Select mux mode: ALT5 mux port: IO16 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad I2C2_SCL is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad I2C2_SCL
End of enumeration elements list.
SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_I2C2_SDA
Select mux mode: ALT0 mux port: SDA of instance: I2C2
0x1 : ALT1_ENET1_1588_EVENT1_OUT
Select mux mode: ALT1 mux port: 1588_EVENT1_OUT of instance: ENET1
0x5 : ALT5_GPIO5_IO17
Select mux mode: ALT5 mux port: IO17 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad I2C2_SDA is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad I2C2_SDA
End of enumeration elements list.
SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_I2C3_SCL
Select mux mode: ALT0 mux port: SCL of instance: I2C3
0x1 : ALT1_PWM4_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM4
0x2 : ALT2_GPT2_CLK
Select mux mode: ALT2 mux port: CLK of instance: GPT2
0x5 : ALT5_GPIO5_IO18
Select mux mode: ALT5 mux port: IO18 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad I2C3_SCL is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad I2C3_SCL
End of enumeration elements list.
SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_I2C3_SDA
Select mux mode: ALT0 mux port: SDA of instance: I2C3
0x1 : ALT1_PWM3_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM3
0x2 : ALT2_GPT3_CLK
Select mux mode: ALT2 mux port: CLK of instance: GPT3
0x5 : ALT5_GPIO5_IO19
Select mux mode: ALT5 mux port: IO19 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad I2C3_SDA is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad I2C3_SDA
End of enumeration elements list.
SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_I2C4_SCL
Select mux mode: ALT0 mux port: SCL of instance: I2C4
0x1 : ALT1_PWM2_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM2
0x2 : ALT2_PCIE1_CLKREQ_B
Select mux mode: ALT2 mux port: CLKREQ_B of instance: PCIE1
0x5 : ALT5_GPIO5_IO20
Select mux mode: ALT5 mux port: IO20 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad I2C4_SCL is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad I2C4_SCL
End of enumeration elements list.
SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_I2C4_SDA
Select mux mode: ALT0 mux port: SDA of instance: I2C4
0x1 : ALT1_PWM1_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM1
0x2 : ALT2_PCIE2_CLKREQ_B
Select mux mode: ALT2 mux port: CLKREQ_B of instance: PCIE2
0x5 : ALT5_GPIO5_IO21
Select mux mode: ALT5 mux port: IO21 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad I2C4_SDA is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad I2C4_SDA
End of enumeration elements list.
SW_MUX_CTL_PAD_UART1_RXD SW MUX Control Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_UART1_RX
Select mux mode: ALT0 mux port: RX of instance: UART1
0x1 : ALT1_ECSPI3_SCLK
Select mux mode: ALT1 mux port: SCLK of instance: ECSPI3
0x5 : ALT5_GPIO5_IO22
Select mux mode: ALT5 mux port: IO22 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad UART1_RXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad UART1_RXD
End of enumeration elements list.
SW_MUX_CTL_PAD_UART1_TXD SW MUX Control Register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_UART1_TX
Select mux mode: ALT0 mux port: TX of instance: UART1
0x1 : ALT1_ECSPI3_MOSI
Select mux mode: ALT1 mux port: MOSI of instance: ECSPI3
0x5 : ALT5_GPIO5_IO23
Select mux mode: ALT5 mux port: IO23 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad UART1_TXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad UART1_TXD
End of enumeration elements list.
SW_MUX_CTL_PAD_UART2_RXD SW MUX Control Register
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_UART2_RX
Select mux mode: ALT0 mux port: RX of instance: UART2
0x1 : ALT1_ECSPI3_MISO
Select mux mode: ALT1 mux port: MISO of instance: ECSPI3
0x5 : ALT5_GPIO5_IO24
Select mux mode: ALT5 mux port: IO24 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad UART2_RXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad UART2_RXD
End of enumeration elements list.
SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SION : Software Input On Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad RTC_RESET_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad RTC_RESET_B
End of enumeration elements list.
SW_MUX_CTL_PAD_UART2_TXD SW MUX Control Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_UART2_TX
Select mux mode: ALT0 mux port: TX of instance: UART2
0x1 : ALT1_ECSPI3_SS0
Select mux mode: ALT1 mux port: SS0 of instance: ECSPI3
0x5 : ALT5_GPIO5_IO25
Select mux mode: ALT5 mux port: IO25 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad UART2_TXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad UART2_TXD
End of enumeration elements list.
SW_MUX_CTL_PAD_UART3_RXD SW MUX Control Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_UART3_RX
Select mux mode: ALT0 mux port: RX of instance: UART3
0x1 : ALT1_UART1_CTS_B
Select mux mode: ALT1 mux port: CTS_B of instance: UART1
0x5 : ALT5_GPIO5_IO26
Select mux mode: ALT5 mux port: IO26 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad UART3_RXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad UART3_RXD
End of enumeration elements list.
SW_MUX_CTL_PAD_UART3_TXD SW MUX Control Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_UART3_TX
Select mux mode: ALT0 mux port: TX of instance: UART3
0x1 : ALT1_UART1_RTS_B
Select mux mode: ALT1 mux port: RTS_B of instance: UART1
0x5 : ALT5_GPIO5_IO27
Select mux mode: ALT5 mux port: IO27 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad UART3_TXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad UART3_TXD
End of enumeration elements list.
SW_MUX_CTL_PAD_UART4_RXD SW MUX Control Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_UART4_RX
Select mux mode: ALT0 mux port: RX of instance: UART4
0x1 : ALT1_UART2_CTS_B
Select mux mode: ALT1 mux port: CTS_B of instance: UART2
0x2 : ALT2_PCIE1_CLKREQ_B
Select mux mode: ALT2 mux port: CLKREQ_B of instance: PCIE1
0x5 : ALT5_GPIO5_IO28
Select mux mode: ALT5 mux port: IO28 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad UART4_RXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad UART4_RXD
End of enumeration elements list.
SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_UART4_TX
Select mux mode: ALT0 mux port: TX of instance: UART4
0x1 : ALT1_UART2_RTS_B
Select mux mode: ALT1 mux port: RTS_B of instance: UART2
0x2 : ALT2_PCIE2_CLKREQ_B
Select mux mode: ALT2 mux port: CLKREQ_B of instance: PCIE2
0x5 : ALT5_GPIO5_IO29
Select mux mode: ALT5 mux port: IO29 of instance: GPIO5
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad UART4_TXD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad UART4_TXD
End of enumeration elements list.
SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_JTAG_TRST_B SW PAD Control Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_RTC SW PAD Control Register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO00
Select mux mode: ALT0 mux port: IO00 of instance: GPIO1
0x1 : ALT1_CCM_ENET_PHY_REF_CLK_ROOT
Select mux mode: ALT1 mux port: ENET_PHY_REF_CLK_ROOT of instance: CCM
0x5 : ALT5_ANAMIX_REF_CLK_32K
Select mux mode: ALT5 mux port: REF_CLK_32K of instance: ANAMIX
0x6 : ALT6_CCM_EXT_CLK1
Select mux mode: ALT6 mux port: EXT_CLK1 of instance: CCM
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO00 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO00
End of enumeration elements list.
SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_ONOFF SW PAD Control Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_POR_B SW PAD Control Register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_RTC_RESET_B SW PAD Control Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO10 SW PAD Control Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO11 SW PAD Control Register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO01
Select mux mode: ALT0 mux port: IO01 of instance: GPIO1
0x1 : ALT1_PWM1_OUT
Select mux mode: ALT1 mux port: OUT of instance: PWM1
0x5 : ALT5_ANAMIX_REF_CLK_24M
Select mux mode: ALT5 mux port: REF_CLK_24M of instance: ANAMIX
0x6 : ALT6_CCM_EXT_CLK2
Select mux mode: ALT6 mux port: EXT_CLK2 of instance: CCM
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO01 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO01
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Control Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO13 SW PAD Control Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO14 SW PAD Control Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_GPIO1_IO15 SW PAD Control Register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_MDC SW PAD Control Register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_MDIO SW PAD Control Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_TD3 SW PAD Control Register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_TD2 SW PAD Control Register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_TD1 SW PAD Control Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_TD0 SW PAD Control Register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_TX_CTL SW PAD Control Register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_TXC SW PAD Control Register
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_RX_CTL SW PAD Control Register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_RXC SW PAD Control Register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_RD0 SW PAD Control Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_RD1 SW PAD Control Register
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO02
Select mux mode: ALT0 mux port: IO02 of instance: GPIO1
0x1 : ALT1_WDOG1_WDOG_B
Select mux mode: ALT1 mux port: WDOG_B of instance: WDOG1
0x5 : ALT5_WDOG1_WDOG_ANY
Select mux mode: ALT5 mux port: WDOG_ANY of instance: WDOG1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO02 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO02
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_RD2 SW PAD Control Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ENET_RD3 SW PAD Control Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control Register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control Register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_DATA4 SW PAD Control Register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_DATA5 SW PAD Control Register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_DATA6 SW PAD Control Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_DATA7 SW PAD Control Register
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_RESET_B SW PAD Control Register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD1_STROBE SW PAD Control Register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_CD_B SW PAD Control Register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_CLK SW PAD Control Register
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO03
Select mux mode: ALT0 mux port: IO03 of instance: GPIO1
0x1 : ALT1_USDHC1_VSELECT
Select mux mode: ALT1 mux port: VSELECT of instance: USDHC1
0x5 : ALT5_SDMA1_EXT_EVENT0
Select mux mode: ALT5 mux port: EXT_EVENT0 of instance: SDMA1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO03 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO03
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_CMD SW PAD Control Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_DATA0 SW PAD Control Register
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_DATA1 SW PAD Control Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_DATA2 SW PAD Control Register
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_DATA3 SW PAD Control Register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_RESET_B SW PAD Control Register
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SD2_WP SW PAD Control Register
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_ALE SW PAD Control Register
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_CE0_B SW PAD Control Register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_CE1_B SW PAD Control Register
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_CE2_B SW PAD Control Register
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_CE3_B SW PAD Control Register
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_CLE SW PAD Control Register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DATA00 SW PAD Control Register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DATA01 SW PAD Control Register
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DATA02 SW PAD Control Register
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO04
Select mux mode: ALT0 mux port: IO04 of instance: GPIO1
0x1 : ALT1_USDHC2_VSELECT
Select mux mode: ALT1 mux port: VSELECT of instance: USDHC2
0x5 : ALT5_SDMA1_EXT_EVENT1
Select mux mode: ALT5 mux port: EXT_EVENT1 of instance: SDMA1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO04 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO04
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DATA03 SW PAD Control Register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DATA04 SW PAD Control Register
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DATA05 SW PAD Control Register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DATA06 SW PAD Control Register
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DATA07 SW PAD Control Register
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_DQS SW PAD Control Register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_RE_B SW PAD Control Register
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_READY_B SW PAD Control Register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_WE_B SW PAD Control Register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_NAND_WP_B SW PAD Control Register
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI5_RXFS SW PAD Control Register
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI5_RXC SW PAD Control Register
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI5_RXD0 SW PAD Control Register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI5_RXD1 SW PAD Control Register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI5_RXD2 SW PAD Control Register
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI5_RXD3 SW PAD Control Register
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO05
Select mux mode: ALT0 mux port: IO05 of instance: GPIO1
0x1 : ALT1_M4_NMI
Select mux mode: ALT1 mux port: NMI of instance: M4
0x5 : ALT5_CCM_PMIC_READY
Select mux mode: ALT5 mux port: PMIC_READY of instance: CCM
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO05 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO05
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI5_MCLK SW PAD Control Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXFS SW PAD Control Register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXC SW PAD Control Register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXD0 SW PAD Control Register
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXD1 SW PAD Control Register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXD2 SW PAD Control Register
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXD3 SW PAD Control Register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXD4 SW PAD Control Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXD5 SW PAD Control Register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXD6 SW PAD Control Register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_RXD7 SW PAD Control Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXFS SW PAD Control Register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXC SW PAD Control Register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXD0 SW PAD Control Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXD1 SW PAD Control Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXD2 SW PAD Control Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO06
Select mux mode: ALT0 mux port: IO06 of instance: GPIO1
0x1 : ALT1_ENET1_MDC
Select mux mode: ALT1 mux port: MDC of instance: ENET1
0x5 : ALT5_USDHC1_CD_B
Select mux mode: ALT5 mux port: CD_B of instance: USDHC1
0x6 : ALT6_CCM_EXT_CLK3
Select mux mode: ALT6 mux port: EXT_CLK3 of instance: CCM
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO06 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO06
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXD3 SW PAD Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXD4 SW PAD Control Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXD5 SW PAD Control Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXD6 SW PAD Control Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_TXD7 SW PAD Control Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI1_MCLK SW PAD Control Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI2_RXFS SW PAD Control Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI2_RXC SW PAD Control Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI2_RXD0 SW PAD Control Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI2_TXFS SW PAD Control Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI2_TXC SW PAD Control Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI2_TXD0 SW PAD Control Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI2_MCLK SW PAD Control Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI3_RXFS SW PAD Control Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI3_RXC SW PAD Control Register
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI3_RXD SW PAD Control Register
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO07
Select mux mode: ALT0 mux port: IO07 of instance: GPIO1
0x1 : ALT1_ENET1_MDIO
Select mux mode: ALT1 mux port: MDIO of instance: ENET1
0x5 : ALT5_USDHC1_WP
Select mux mode: ALT5 mux port: WP of instance: USDHC1
0x6 : ALT6_CCM_EXT_CLK4
Select mux mode: ALT6 mux port: EXT_CLK4 of instance: CCM
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO07 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO07
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI3_TXFS SW PAD Control Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI3_TXC SW PAD Control Register
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI3_TXD SW PAD Control Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SAI3_MCLK SW PAD Control Register
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SPDIF_TX SW PAD Control Register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SPDIF_RX SW PAD Control Register
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_SPDIF_EXT_CLK SW PAD Control Register
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ECSPI1_SCLK SW PAD Control Register
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ECSPI1_MOSI SW PAD Control Register
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ECSPI1_MISO SW PAD Control Register
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ECSPI1_SS0 SW PAD Control Register
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ECSPI2_SCLK SW PAD Control Register
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_ECSPI2_MOSI SW PAD Control Register
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ECSPI2_MISO SW PAD Control Register
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_ECSPI2_SS0 SW PAD Control Register
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_I2C1_SCL SW PAD Control Register
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO08
Select mux mode: ALT0 mux port: IO08 of instance: GPIO1
0x1 : ALT1_ENET1_1588_EVENT0_IN
Select mux mode: ALT1 mux port: 1588_EVENT0_IN of instance: ENET1
0x5 : ALT5_USDHC2_RESET_B
Select mux mode: ALT5 mux port: RESET_B of instance: USDHC2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO08 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO08
End of enumeration elements list.
SW_PAD_CTL_PAD_I2C1_SDA SW PAD Control Register
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_I2C2_SCL SW PAD Control Register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_I2C2_SDA SW PAD Control Register
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_I2C3_SDA SW PAD Control Register
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_I2C4_SCL SW PAD Control Register
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_I2C4_SDA SW PAD Control Register
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_UART1_RXD SW PAD Control Register
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_UART1_TXD SW PAD Control Register
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_UART2_RXD SW PAD Control Register
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_UART2_TXD SW PAD Control Register
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_UART3_RXD SW PAD Control Register
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
VSEL : Voltage Select Field
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : VSEL_0_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x1 : VSEL_1_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x2 : VSEL_2_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x3 : VSEL_3_Auto_Detct_Mode
Auto Detect 3.3/2.5/1.2/1.8 V mode
0x4 : VSEL_4_Manual_3p3V_Mode
Manually Set 3.3V mode
0x5 : VSEL_5_Manual_2p5V_Mode
Manually Set 2.5V mode
0x6 : VSEL_6_Manual_2p5V_Mode
Manually Set 2.5V mode
0x7 : VSEL_7_Manual_1p2_1p8V_Mode
Manually Set 1.2V/1.8V mode
End of enumeration elements list.
SW_PAD_CTL_PAD_UART3_TXD SW PAD Control Register
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_UART4_RXD SW PAD Control Register
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Drive Strength Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DSE_0
HI-Z
0x1 : 255_OHM
255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
0x2 : 105_OHM
105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
0x3 : 75_OHM
75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
0x4 : 85_OHM
85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
0x5 : 65_OHM
65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
0x6 : 45_OHM
45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
0x7 : 40_OHM
40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
End of enumeration elements list.
SRE : Slew Rate Field
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : SLOW
Slow Frequency Slew Rate (50Mhz)
0x1 : MEDIUM
Medium Frequency Slew Rate (100Mhz)
0x2 : FAST
Fast Frequency Slew Rate (150Mhz)
0x3 : MAX
Max Frequency Slew Rate (200Mhz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Open Drain Disabled
0x1 : Enabled
Open Drain Enabled
End of enumeration elements list.
PUE : Pull Up Enable Field
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Pull Up Resistor Disabled
0x1 : Enabled
Pull Up Resistor Enabled
End of enumeration elements list.
HYS : Schmitt trigger Enable Field
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : Disabled
Schmitt Trigger Disabled
0x1 : Enabled
Schmitt Trigger Enabled
End of enumeration elements list.
LVTTL : Lvttl Enable Field
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : Disabled
LVTTL Disabled
0x1 : Enabled
LVTTL Enabled
End of enumeration elements list.
CCM_PMIC_READY_SELECT_INPUT DAISY Register
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO09
Select mux mode: ALT0 mux port: IO09 of instance: GPIO1
0x1 : ALT1_ENET1_1588_EVENT0_OUT
Select mux mode: ALT1 mux port: 1588_EVENT0_OUT of instance: ENET1
0x5 : ALT5_SDMA2_EXT_EVENT0
Select mux mode: ALT5 mux port: EXT_EVENT0 of instance: SDMA2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO09 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO09
End of enumeration elements list.
ENET1_MDIO_SELECT_INPUT DAISY Register
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
SAI1_RX_SYNC_SELECT_INPUT DAISY Register
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SAI1_RXFS_ALT0
Selecting Pad: SAI1_RXFS Mode: ALT0 for SAI1_RX_SYNC
0x1 : SAI1_RXD5_ALT3
Selecting Pad: SAI1_RXD5 Mode: ALT3 for SAI1_RX_SYNC
End of enumeration elements list.
SAI1_TX_BCLK_SELECT_INPUT DAISY Register
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SAI5_MCLK_ALT1
Selecting Pad: SAI5_MCLK Mode: ALT1 for SAI1_TX_BCLK
0x1 : SAI1_TXC_ALT0
Selecting Pad: SAI1_TXC Mode: ALT0 for SAI1_TX_BCLK
0x2 : SAI1_MCLK_ALT2
Selecting Pad: SAI1_MCLK Mode: ALT2 for SAI1_TX_BCLK
End of enumeration elements list.
SAI1_TX_SYNC_SELECT_INPUT DAISY Register
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SAI5_RXD1_ALT2
Selecting Pad: SAI5_RXD1 Mode: ALT2 for SAI1_TX_SYNC
0x1 : SAI5_RXD2_ALT2
Selecting Pad: SAI5_RXD2 Mode: ALT2 for SAI1_TX_SYNC
0x2 : SAI5_RXD3_ALT2
Selecting Pad: SAI5_RXD3 Mode: ALT2 for SAI1_TX_SYNC
0x3 : SAI1_TXFS_ALT0
Selecting Pad: SAI1_TXFS Mode: ALT0 for SAI1_TX_SYNC
0x4 : SAI1_RXD7_ALT2
Selecting Pad: SAI1_RXD7 Mode: ALT2 for SAI1_TX_SYNC
End of enumeration elements list.
SAI5_RX_BCLK_SELECT_INPUT DAISY Register
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
SAI5_RXD0_SELECT_INPUT DAISY Register
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
SAI5_RXD1_SELECT_INPUT DAISY Register
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
SAI5_RXD2_SELECT_INPUT DAISY Register
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
SAI5_RXD3_SELECT_INPUT DAISY Register
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
SAI5_RX_SYNC_SELECT_INPUT DAISY Register
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
SAI5_TX_BCLK_SELECT_INPUT DAISY Register
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SAI5_RXD2_ALT3
Selecting Pad: SAI5_RXD2 Mode: ALT3 for SAI5_TX_BCLK
0x1 : SAI1_TXC_ALT1
Selecting Pad: SAI1_TXC Mode: ALT1 for SAI5_TX_BCLK
0x2 : SAI2_RXC_ALT1
Selecting Pad: SAI2_RXC Mode: ALT1 for SAI5_TX_BCLK
End of enumeration elements list.
SAI5_TX_SYNC_SELECT_INPUT DAISY Register
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SAI5_RXD1_ALT3
Selecting Pad: SAI5_RXD1 Mode: ALT3 for SAI5_TX_SYNC
0x1 : SAI1_TXFS_ALT1
Selecting Pad: SAI1_TXFS Mode: ALT1 for SAI5_TX_SYNC
0x2 : SAI2_RXFS_ALT1
Selecting Pad: SAI2_RXFS Mode: ALT1 for SAI5_TX_SYNC
End of enumeration elements list.
UART1_RTS_B_SELECT_INPUT DAISY Register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UART3_RXD_ALT1
Selecting Pad: UART3_RXD Mode: ALT1 for UART1_RTS_B
0x1 : UART3_TXD_ALT1
Selecting Pad: UART3_TXD Mode: ALT1 for UART1_RTS_B
End of enumeration elements list.
UART1_RXD_SELECT_INPUT DAISY Register
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UART1_RXD_ALT0
Selecting Pad: UART1_RXD Mode: ALT0 for UART1_RXD
0x1 : UART1_TXD_ALT0
Selecting Pad: UART1_TXD Mode: ALT0 for UART1_RXD
End of enumeration elements list.
UART2_RTS_B_SELECT_INPUT DAISY Register
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UART4_RXD_ALT1
Selecting Pad: UART4_RXD Mode: ALT1 for UART2_RTS_B
0x1 : UART4_TXD_ALT1
Selecting Pad: UART4_TXD Mode: ALT1 for UART2_RTS_B
End of enumeration elements list.
UART2_RXD_SELECT_INPUT DAISY Register
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UART2_RXD_ALT0
Selecting Pad: UART2_RXD Mode: ALT0 for UART2_RXD
0x1 : UART2_TXD_ALT0
Selecting Pad: UART2_TXD Mode: ALT0 for UART2_RXD
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO10
Select mux mode: ALT0 mux port: IO10 of instance: GPIO1
0x1 : ALT1_USB1_OTG_ID
Select mux mode: ALT1 mux port: OTG_ID of instance: USB1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO10 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO10
End of enumeration elements list.
UART3_RTS_B_SELECT_INPUT DAISY Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ECSPI1_MISO_ALT1
Selecting Pad: ECSPI1_MISO Mode: ALT1 for UART3_RTS_B
0x1 : ECSPI1_SS0_ALT1
Selecting Pad: ECSPI1_SS0 Mode: ALT1 for UART3_RTS_B
End of enumeration elements list.
UART3_RXD_SELECT_INPUT DAISY Register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ECSPI1_SCLK_ALT1
Selecting Pad: ECSPI1_SCLK Mode: ALT1 for UART3_RXD
0x1 : ECSPI1_MOSI_ALT1
Selecting Pad: ECSPI1_MOSI Mode: ALT1 for UART3_RXD
0x2 : UART3_RXD_ALT0
Selecting Pad: UART3_RXD Mode: ALT0 for UART3_RXD
0x3 : UART3_TXD_ALT0
Selecting Pad: UART3_TXD Mode: ALT0 for UART3_RXD
End of enumeration elements list.
UART4_RTS_B_SELECT_INPUT DAISY Register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ECSPI2_MISO_ALT1
Selecting Pad: ECSPI2_MISO Mode: ALT1 for UART4_RTS_B
0x1 : ECSPI2_SS0_ALT1
Selecting Pad: ECSPI2_SS0 Mode: ALT1 for UART4_RTS_B
End of enumeration elements list.
UART4_RXD_SELECT_INPUT DAISY Register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ECSPI2_SCLK_ALT1
Selecting Pad: ECSPI2_SCLK Mode: ALT1 for UART4_RXD
0x1 : ECSPI2_MOSI_ALT1
Selecting Pad: ECSPI2_MOSI Mode: ALT1 for UART4_RXD
0x2 : UART4_RXD_ALT0
Selecting Pad: UART4_RXD Mode: ALT0 for UART4_RXD
End of enumeration elements list.
SAI6_RX_BCLK_SELECT_INPUT DAISY Register
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
SAI6_RXD0_SELECT_INPUT DAISY Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
SAI6_RX_SYNC_SELECT_INPUT DAISY Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
SAI6_TX_BCLK_SELECT_INPUT DAISY Register
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SAI1_RXD4_ALT1
Selecting Pad: SAI1_RXD4 Mode: ALT1 for SAI6_TX_BCLK
0x1 : SAI1_TXD4_ALT2
Selecting Pad: SAI1_TXD4 Mode: ALT2 for SAI6_TX_BCLK
End of enumeration elements list.
SAI6_TX_SYNC_SELECT_INPUT DAISY Register
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SAI1_RXD6_ALT1
Selecting Pad: SAI1_RXD6 Mode: ALT1 for SAI6_TX_SYNC
0x1 : SAI1_TXD6_ALT2
Selecting Pad: SAI1_TXD6 Mode: ALT2 for SAI6_TX_SYNC
End of enumeration elements list.
PCIE1_CLKREQ_B_SELECT_INPUT DAISY Register
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : I2C4_SCL_ALT2
Selecting Pad: I2C4_SCL Mode: ALT2 for PCIE1_CLKREQ_B
0x1 : UART4_RXD_ALT2
Selecting Pad: UART4_RXD Mode: ALT2 for PCIE1_CLKREQ_B
End of enumeration elements list.
PCIE2_CLKREQ_B_SELECT_INPUT DAISY Register
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : I2C4_SDA_ALT2
Selecting Pad: I2C4_SDA Mode: ALT2 for PCIE2_CLKREQ_B
0x1 : UART4_TXD_ALT2
Selecting Pad: UART4_TXD Mode: ALT2 for PCIE2_CLKREQ_B
End of enumeration elements list.
SAI5_MCLK_SELECT_INPUT DAISY Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SAI5_MCLK_ALT0
Selecting Pad: SAI5_MCLK Mode: ALT0 for SAI5_MCLK
0x1 : SAI1_MCLK_ALT1
Selecting Pad: SAI1_MCLK Mode: ALT1 for SAI5_MCLK
0x2 : SAI2_MCLK_ALT1
Selecting Pad: SAI2_MCLK Mode: ALT1 for SAI5_MCLK
0x3 : SAI3_MCLK_ALT2
Selecting Pad: SAI3_MCLK Mode: ALT2 for SAI5_MCLK
End of enumeration elements list.
SAI6_MCLK_SELECT_INPUT DAISY Register
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAISY : Input Select (DAISY) Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SAI1_RXD7_ALT1
Selecting Pad: SAI1_RXD7 Mode: ALT1 for SAI6_MCLK
0x1 : SAI1_TXD7_ALT1
Selecting Pad: SAI1_TXD7 Mode: ALT1 for SAI6_MCLK
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO11
Select mux mode: ALT0 mux port: IO11 of instance: GPIO1
0x1 : ALT1_USB2_OTG_ID
Select mux mode: ALT1 mux port: OTG_ID of instance: USB2
0x5 : ALT5_CCM_PMIC_READY
Select mux mode: ALT5 mux port: PMIC_READY of instance: CCM
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO11 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO11
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO12
Select mux mode: ALT0 mux port: IO12 of instance: GPIO1
0x1 : ALT1_USB1_OTG_PWR
Select mux mode: ALT1 mux port: OTG_PWR of instance: USB1
0x5 : ALT5_SDMA2_EXT_EVENT1
Select mux mode: ALT5 mux port: EXT_EVENT1 of instance: SDMA2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO12 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO12
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO13
Select mux mode: ALT0 mux port: IO13 of instance: GPIO1
0x1 : ALT1_USB1_OTG_OC
Select mux mode: ALT1 mux port: OTG_OC of instance: USB1
0x5 : ALT5_PWM2_OUT
Select mux mode: ALT5 mux port: OUT of instance: PWM2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO13 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO13
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO14
Select mux mode: ALT0 mux port: IO14 of instance: GPIO1
0x1 : ALT1_USB2_OTG_PWR
Select mux mode: ALT1 mux port: OTG_PWR of instance: USB2
0x5 : ALT5_PWM3_OUT
Select mux mode: ALT5 mux port: OUT of instance: PWM3
0x6 : ALT6_CCM_CLKO1
Select mux mode: ALT6 mux port: CLKO1 of instance: CCM
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO14 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO14
End of enumeration elements list.
SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_GPIO1_IO15
Select mux mode: ALT0 mux port: IO15 of instance: GPIO1
0x1 : ALT1_USB2_OTG_OC
Select mux mode: ALT1 mux port: OTG_OC of instance: USB2
0x5 : ALT5_PWM4_OUT
Select mux mode: ALT5 mux port: OUT of instance: PWM4
0x6 : ALT6_CCM_CLKO2
Select mux mode: ALT6 mux port: CLKO2 of instance: CCM
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad GPIO1_IO15 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad GPIO1_IO15
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_MDC SW MUX Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_MDC
Select mux mode: ALT0 mux port: MDC of instance: ENET1
0x5 : ALT5_GPIO1_IO16
Select mux mode: ALT5 mux port: IO16 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_MDC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_MDC
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_MDIO SW MUX Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_MDIO
Select mux mode: ALT0 mux port: MDIO of instance: ENET1
0x5 : ALT5_GPIO1_IO17
Select mux mode: ALT5 mux port: IO17 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_MDIO is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_MDIO
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_TD3 SW MUX Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_TD3
Select mux mode: ALT0 mux port: RGMII_TD3 of instance: ENET1
0x5 : ALT5_GPIO1_IO18
Select mux mode: ALT5 mux port: IO18 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_TD3 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_TD3
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_TD2 SW MUX Control Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_TD2
Select mux mode: ALT0 mux port: RGMII_TD2 of instance: ENET1
0x1 : ALT1_ENET1_TX_CLK
Select mux mode: ALT1 mux port: TX_CLK of instance: ENET1
0x5 : ALT5_GPIO1_IO19
Select mux mode: ALT5 mux port: IO19 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_TD2 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_TD2
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_TD1 SW MUX Control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_TD1
Select mux mode: ALT0 mux port: RGMII_TD1 of instance: ENET1
0x5 : ALT5_GPIO1_IO20
Select mux mode: ALT5 mux port: IO20 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_TD1 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_TD1
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_TD0 SW MUX Control Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_TD0
Select mux mode: ALT0 mux port: RGMII_TD0 of instance: ENET1
0x5 : ALT5_GPIO1_IO21
Select mux mode: ALT5 mux port: IO21 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_TD0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_TD0
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_TX_CTL SW MUX Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_TX_CTL
Select mux mode: ALT0 mux port: RGMII_TX_CTL of instance: ENET1
0x5 : ALT5_GPIO1_IO22
Select mux mode: ALT5 mux port: IO22 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_TX_CTL is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_TX_CTL
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_TXC SW MUX Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_TXC
Select mux mode: ALT0 mux port: RGMII_TXC of instance: ENET1
0x1 : ALT1_ENET1_TX_ER
Select mux mode: ALT1 mux port: TX_ER of instance: ENET1
0x5 : ALT5_GPIO1_IO23
Select mux mode: ALT5 mux port: IO23 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_TXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_TXC
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_RX_CTL SW MUX Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_RX_CTL
Select mux mode: ALT0 mux port: RGMII_RX_CTL of instance: ENET1
0x5 : ALT5_GPIO1_IO24
Select mux mode: ALT5 mux port: IO24 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_RX_CTL is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_RX_CTL
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_RXC SW MUX Control Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_RXC
Select mux mode: ALT0 mux port: RGMII_RXC of instance: ENET1
0x1 : ALT1_ENET1_RX_ER
Select mux mode: ALT1 mux port: RX_ER of instance: ENET1
0x5 : ALT5_GPIO1_IO25
Select mux mode: ALT5 mux port: IO25 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_RXC is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_RXC
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_RD0 SW MUX Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_RD0
Select mux mode: ALT0 mux port: RGMII_RD0 of instance: ENET1
0x5 : ALT5_GPIO1_IO26
Select mux mode: ALT5 mux port: IO26 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_RD0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_RD0
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_RD1 SW MUX Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_RD1
Select mux mode: ALT0 mux port: RGMII_RD1 of instance: ENET1
0x5 : ALT5_GPIO1_IO27
Select mux mode: ALT5 mux port: IO27 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_RD1 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_RD1
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_RD2 SW MUX Control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_RD2
Select mux mode: ALT0 mux port: RGMII_RD2 of instance: ENET1
0x5 : ALT5_GPIO1_IO28
Select mux mode: ALT5 mux port: IO28 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_RD2 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_RD2
End of enumeration elements list.
SW_MUX_CTL_PAD_ENET_RD3 SW MUX Control Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ENET1_RGMII_RD3
Select mux mode: ALT0 mux port: RGMII_RD3 of instance: ENET1
0x5 : ALT5_GPIO1_IO29
Select mux mode: ALT5 mux port: IO29 of instance: GPIO1
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad ENET_RD3 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad ENET_RD3
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_CLK
Select mux mode: ALT0 mux port: CLK of instance: USDHC1
0x5 : ALT5_GPIO2_IO00
Select mux mode: ALT5 mux port: IO00 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_CLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_CLK
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_CMD
Select mux mode: ALT0 mux port: CMD of instance: USDHC1
0x5 : ALT5_GPIO2_IO01
Select mux mode: ALT5 mux port: IO01 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_CMD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_CMD
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_DATA0
Select mux mode: ALT0 mux port: DATA0 of instance: USDHC1
0x5 : ALT5_GPIO2_IO02
Select mux mode: ALT5 mux port: IO02 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_DATA0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_DATA0
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_DATA1
Select mux mode: ALT0 mux port: DATA1 of instance: USDHC1
0x5 : ALT5_GPIO2_IO03
Select mux mode: ALT5 mux port: IO03 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_DATA1 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_DATA1
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_DATA2
Select mux mode: ALT0 mux port: DATA2 of instance: USDHC1
0x5 : ALT5_GPIO2_IO04
Select mux mode: ALT5 mux port: IO04 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_DATA2 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_DATA2
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_DATA3
Select mux mode: ALT0 mux port: DATA3 of instance: USDHC1
0x5 : ALT5_GPIO2_IO05
Select mux mode: ALT5 mux port: IO05 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_DATA3 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_DATA3
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_DATA4 SW MUX Control Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_DATA4
Select mux mode: ALT0 mux port: DATA4 of instance: USDHC1
0x5 : ALT5_GPIO2_IO06
Select mux mode: ALT5 mux port: IO06 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_DATA4 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_DATA4
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_DATA5 SW MUX Control Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_DATA5
Select mux mode: ALT0 mux port: DATA5 of instance: USDHC1
0x5 : ALT5_GPIO2_IO07
Select mux mode: ALT5 mux port: IO07 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_DATA5 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_DATA5
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_DATA6 SW MUX Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_DATA6
Select mux mode: ALT0 mux port: DATA6 of instance: USDHC1
0x5 : ALT5_GPIO2_IO08
Select mux mode: ALT5 mux port: IO08 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_DATA6 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_DATA6
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_DATA7 SW MUX Control Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_DATA7
Select mux mode: ALT0 mux port: DATA7 of instance: USDHC1
0x5 : ALT5_GPIO2_IO09
Select mux mode: ALT5 mux port: IO09 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_DATA7 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_DATA7
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_RESET_B
Select mux mode: ALT0 mux port: RESET_B of instance: USDHC1
0x5 : ALT5_GPIO2_IO10
Select mux mode: ALT5 mux port: IO10 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_RESET_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_RESET_B
End of enumeration elements list.
SW_MUX_CTL_PAD_SD1_STROBE SW MUX Control Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC1_STROBE
Select mux mode: ALT0 mux port: STROBE of instance: USDHC1
0x5 : ALT5_GPIO2_IO11
Select mux mode: ALT5 mux port: IO11 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD1_STROBE is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD1_STROBE
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_CD_B
Select mux mode: ALT0 mux port: CD_B of instance: USDHC2
0x5 : ALT5_GPIO2_IO12
Select mux mode: ALT5 mux port: IO12 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_CD_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_CD_B
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_CLK
Select mux mode: ALT0 mux port: CLK of instance: USDHC2
0x5 : ALT5_GPIO2_IO13
Select mux mode: ALT5 mux port: IO13 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_CLK is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_CLK
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_CMD
Select mux mode: ALT0 mux port: CMD of instance: USDHC2
0x5 : ALT5_GPIO2_IO14
Select mux mode: ALT5 mux port: IO14 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_CMD is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_CMD
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_DATA0
Select mux mode: ALT0 mux port: DATA0 of instance: USDHC2
0x5 : ALT5_GPIO2_IO15
Select mux mode: ALT5 mux port: IO15 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_DATA0 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_DATA0
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_DATA1
Select mux mode: ALT0 mux port: DATA1 of instance: USDHC2
0x5 : ALT5_GPIO2_IO16
Select mux mode: ALT5 mux port: IO16 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_DATA1 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_DATA1
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_DATA2
Select mux mode: ALT0 mux port: DATA2 of instance: USDHC2
0x5 : ALT5_GPIO2_IO17
Select mux mode: ALT5 mux port: IO17 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_DATA2 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_DATA2
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_DATA3
Select mux mode: ALT0 mux port: DATA3 of instance: USDHC2
0x5 : ALT5_GPIO2_IO18
Select mux mode: ALT5 mux port: IO18 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_DATA3 is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_DATA3
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_RESET_B
Select mux mode: ALT0 mux port: RESET_B of instance: USDHC2
0x5 : ALT5_GPIO2_IO19
Select mux mode: ALT5 mux port: IO19 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_RESET_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_RESET_B
End of enumeration elements list.
SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_USDHC2_WP
Select mux mode: ALT0 mux port: WP of instance: USDHC2
0x5 : ALT5_GPIO2_IO20
Select mux mode: ALT5 mux port: IO20 of instance: GPIO2
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad SD2_WP is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad SD2_WP
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_ALE SW MUX Control Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_ALE
Select mux mode: ALT0 mux port: ALE of instance: RAWNAND
0x1 : ALT1_QSPI_A_SCLK
Select mux mode: ALT1 mux port: A_SCLK of instance: QSPI
0x5 : ALT5_GPIO3_IO00
Select mux mode: ALT5 mux port: IO00 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_ALE is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_ALE
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_CE0_B
Select mux mode: ALT0 mux port: CE0_B of instance: RAWNAND
0x1 : ALT1_QSPI_A_SS0_B
Select mux mode: ALT1 mux port: A_SS0_B of instance: QSPI
0x5 : ALT5_GPIO3_IO01
Select mux mode: ALT5 mux port: IO01 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_CE0_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_CE0_B
End of enumeration elements list.
SW_MUX_CTL_PAD_NAND_CE1_B SW MUX Control Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_RAWNAND_CE1_B
Select mux mode: ALT0 mux port: CE1_B of instance: RAWNAND
0x1 : ALT1_QSPI_A_SS1_B
Select mux mode: ALT1 mux port: A_SS1_B of instance: QSPI
0x5 : ALT5_GPIO3_IO02
Select mux mode: ALT5 mux port: IO02 of instance: GPIO3
End of enumeration elements list.
SION : Software Input On Field
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SION_DISABLED
Input Path of pad NAND_CE1_B is determined by functionality
0x1 : SION_ENABLED
Force Input Path of pad NAND_CE1_B
End of enumeration elements list.
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