Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x30838 byte (0x0)
mem_usage : registers
protection : not protected
no description available
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
apb_xt_reset : APB Control on the CPU reset active High
bits : 0 - 0 (1 bit)
access : read-write
apb_dram_path : When 1 enable APB to R/W the DRAM
bits : 1 - 1 (1 bit)
access : read-write
apb_iram_path : When 1 enable APB to R/W the IRAM
bits : 2 - 2 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 3 - 31 (29 bit)
access : read-only
no description available
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mailbox0_wr_data : Write Data to Mailbox
bits : 0 - 7 (8 bit)
access : read-write
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
mailbox0_rd_data : Mailbox Read data
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
keep_alive_cnt : Software keep alive counter
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ver_lsb : Software Version LSB
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ver_msb : Software Version MSB
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sw_lib_ver_l : Software Lib version written by CPU
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sw_lib_ver_h : Software Lib version written by CPU
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sw_debug_7_0 : sw_debug_7_0
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sw_debug_15_8 : sw_debug_15_8
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x30000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sw_rst : Software reset. Active high.
bits : 0 - 0 (1 bit)
access : read-write
i2s_dec_start : When high Source Decoder starts.
bits : 1 - 1 (1 bit)
access : read-write
i2s_block_start_force : Force a "Block Start" in the audio stream.
bits : 2 - 2 (1 bit)
access : read-write
spdif_ts_en : Enble SPDIF Time Stamp when decoders are disabled
bits : 3 - 3 (1 bit)
access : read-write
i2s_ts_en : Enble I2S Time Stamp when decoders are disabled
bits : 4 - 4 (1 bit)
access : read-write
valid_bits_force : Force valid bits of the channels
bits : 5 - 5 (1 bit)
access : read-write
valid_all : valid bit for all samples
bits : 6 - 6 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 7 - 31 (25 bit)
access : read-only
no description available
address_offset : 0x30004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
low_index_msb : When low MSB is transmitted first. When high LSB is transmitted first.
bits : 0 - 0 (1 bit)
access : read-write
ws_polarity : Word Select Polarity. 0: No change, 1: Inverted.
bits : 1 - 1 (1 bit)
access : read-write
audio_ch_num : Number of channels to decode
bits : 2 - 6 (5 bit)
access : read-write
audio_sample_just : Data justification setting:00 left-justified, 01 right-justified
bits : 7 - 8 (2 bit)
access : read-write
audio_sample_width : Decoder sample width:00-16 bit, 01-24 bit, 10-32 bit
bits : 9 - 10 (2 bit)
access : read-write
trans_smpl_width : Decoder Word Select width: 00-16 bit, 01-24 bit, 10-32 bit
bits : 11 - 12 (2 bit)
access : read-write
audio_channel_type : Set the transmission type.
bits : 13 - 16 (4 bit)
access : read-write
i2s_dec_port_en : Enables the I2S Decoder ports. Allowed values are:0001 - I2S port 0 is enabled.0011 - I2S ports 0,1 are enabled.1111 - I2S ports 0,1,2,3 are enabled. No other values are allowed.
bits : 17 - 20 (4 bit)
access : read-write
reserved_0 : reserved_0
bits : 21 - 31 (11 bit)
access : read-only
no description available
address_offset : 0x30008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Byte0 : Byte 0 of transmitted channel. Same for all channels.
bits : 0 - 7 (8 bit)
access : read-write
Category_Code : Category Code of transmitted channel. Same for all channels.
bits : 8 - 15 (8 bit)
access : read-write
Sampling_Freq : Sampling Frequency of transmitted channel. Same for all channels.
bits : 16 - 19 (4 bit)
access : read-write
Clock_accuracy : Clock Accuracy of transmitted channel. Same for all channels.
bits : 20 - 23 (4 bit)
access : read-write
Original_samp_freq : Original Sampling Freq. of transmitted channel. Same for all channels.
bits : 24 - 27 (4 bit)
access : read-write
reserved_0 : reserved_0
bits : 28 - 31 (4 bit)
access : read-only
no description available
address_offset : 0x3000C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch0 : Channel 0 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch0 : Channel 0 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch0 : Channel 0 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch1 : Channel 1 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch1 : Channel 1 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch1 : Channel 1 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits1_0 : Valid Bits for channel 1 and 0 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch2 : Channel 2 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch2 : Channel 2 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch2 : Channel 2 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch3 : Channel 3 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch3 : Channel 3 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch3 : Channel 3 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits3_2 : Valid Bits for channel 3 and 2 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch4 : Channel 4 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch4 : Channel 4 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch4 : Channel 4 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch5 : Channel 5 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch5 : Channel 5 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch5 : Channel 5 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits5_4 : Valid Bits for channel 5 and 4 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch6 : Channel 6 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch6 : Channel 6 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch6 : Channel 6 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch7 : Channel 7 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch7 : Channel 7 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch7 : Channel 7 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits7_6 : Valid Bits for channel 7 and 6 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x3001C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch8 : Channel 8 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch8 : Channel 8 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch8 : Channel 8 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch9 : Channel 9 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch9 : Channel 9 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch9 : Channel 9 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits9_8 : Valid Bits for channel 9 and 8 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch10 : Channel 10 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch10 : Channel 10 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch10 : Channel 10 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch11 : Channel 11 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch11 : Channel 11 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch11 : Channel 11 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits11_10 : Valid Bits for channel 11 and 10 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch12 : Channel 12 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch12 : Channel 12 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch12 : Channel 12 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch13 : Channel 13 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch13 : Channel 13 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch13 : Channel 13 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits13_12 : Valid Bits for channel 13 and 12 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch14 : Channel 14 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch14 : Channel 14 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch14 : Channel 14 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch15 : Channel 15 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch15 : Channel 15 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch15 : Channel 15 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits15_14 : Valid Bits for channel 15 and 14 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x3002C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch16 : Channel 16 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch16 : Channel 16 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch16 : Channel 16 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch17 : Channel 17 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch17 : Channel 17 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch17 : Channel 17 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits17_16 : Valid Bits for channel 17 and 16 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch18 : Channel 18 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch18 : Channel 18 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch18 : Channel 18 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch19 : Channel 19 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch19 : Channel 19 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch19 : Channel 19 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits19_18 : Valid Bits for channel 19 and 18 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch20 : Channel 20 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch20 : Channel 20 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch20 : Channel 20 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch21 : Channel 21 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch21 : Channel 21 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch21 : Channel 21 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits21_20 : Valid Bits for channel 21 and 20 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch22 : Channel 22 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch22 : Channel 22 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch22 : Channel 22 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch23 : Channel 23 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch23 : Channel 23 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch23 : Channel 23 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits23_22 : Valid Bits for channel 23 and 22 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x3003C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch24 : Channel 24 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch24 : Channel 24 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch24 : Channel 24 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch25 : Channel 25 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch25 : Channel 25 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch25 : Channel 25 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits25_24 : Valid Bits for channel 25 and 24 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch26 : Channel 26 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch26 : Channel 26 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch26 : Channel 26 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch27 : Channel 27 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch27 : Channel 27 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch27 : Channel 27 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits27_26 : Valid Bits for channel 27 and 26 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch28 : Channel 28 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch28 : Channel 28 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch28 : Channel 28 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch29 : Channel 29 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch29 : Channel 29 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch29 : Channel 29 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits29_28 : Valid Bits for channel 29 and 28 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
source_num_ch30 : Channel 30 Source number.
bits : 0 - 3 (4 bit)
access : read-write
channel_num_ch30 : Channel 30 channel number.
bits : 4 - 7 (4 bit)
access : read-write
word_length_ch30 : Channel 30 word length.
bits : 8 - 11 (4 bit)
access : read-write
source_num_ch31 : Channel 31 Source number.
bits : 12 - 15 (4 bit)
access : read-write
channel_num_ch31 : Channel 31 channel number.
bits : 16 - 19 (4 bit)
access : read-write
word_length_ch31 : Channel 31 word length.
bits : 20 - 23 (4 bit)
access : read-write
valid_bits31_30 : Valid Bits for channel 31 and 30 if force is enabled
bits : 24 - 25 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x3004C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spdif_jitter_avg_win : Spdif Jitter AVG Window
bits : 0 - 2 (3 bit)
access : read-write
spdif_jitter_thrsh : SPDIF Jitter threshold
bits : 3 - 10 (8 bit)
access : read-write
spdif_fifo_mid_range : SPDIF fifo mid range
bits : 11 - 18 (8 bit)
access : read-write
spdif_jitter_bypass : SPDIF Jitter Bypass
bits : 19 - 19 (1 bit)
access : read-write
spdif_avg_sel : SPDIF average Select
bits : 20 - 20 (1 bit)
access : read-write
spdif_enable : SPDIF Enable
bits : 21 - 21 (1 bit)
access : read-write
spdif_jitter_status : SPDIF Jitter Status
bits : 22 - 25 (4 bit)
access : read-only
reserved_0 : reserved_0
bits : 26 - 31 (6 bit)
access : read-only
no description available
address_offset : 0x30050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch1_st_stts_bits3100 : SPDIF Channel 1 Status bits[31:0]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch1_st_stts_bits6332 : SPDIF Channel 1 Status bits[63:32]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30058 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch1_st_stts_bits9564 : SPDIF Channel 1 Status bits[95:64]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x3005C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch1_st_stts_bits12796 : SPDIF Channel 1 Status bits[127:96]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch1_st_stts_bits159128 : SPDIF Channel 1 Status bits[159:128]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30064 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch1_st_stts_bits191160 : SPDIF Channel 1 Status bits[191160]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30068 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch2_st_stts_bits3100 : SPDIF Channel 2 Status bits[31:0]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x3006C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch2_st_stts_bits6332 : SPDIF Channel 2 Status bits[63:32]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30070 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch2_st_stts_bits9564 : SPDIF Channel 2 Status bits[95:64]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30074 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch2_st_stts_bits12796 : SPDIF Channel 2 Status bits[127:96]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30078 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch2_st_stts_bits159128 : SPDIF Channel 2 Status bits[159:128]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x3007C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
spdif_ch2_st_stts_bits191160 : SPDIF Channel 2 Status bits[191160]
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sw_rst : Software reset. Active high.
bits : 0 - 0 (1 bit)
access : read-write
smpl2pkt_en : When high Sample to Packets Block starts.
bits : 1 - 1 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 2 - 31 (30 bit)
access : read-only
no description available
address_offset : 0x30084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
max_num_ch : Number of channels to decode. 0: 1 channel, 31: 32 channels
bits : 0 - 4 (5 bit)
access : read-write
num_of_i2s_ports : Number ofactive I2S ports. 00- 1 port, 01-2 ports, 11- 4 ports, 11 -NA.
bits : 5 - 6 (2 bit)
access : read-write
audio_type : Audio Type setting. Packet is structured according to audio type.
bits : 7 - 10 (4 bit)
access : read-write
cfg_sub_pckt_num : Number of sub-packets in HDMI audio 2-ch packet. 00: 1-SP, 01: 2-SP, 10: 3-SP, 11: 4-SP.100-111: NA.
bits : 11 - 13 (3 bit)
access : read-write
cfg_block_lpcm_first_pkt : 0 - All packets behave the same. 1- First lpcm audio packet is sent with 1 - SP.
bits : 14 - 14 (1 bit)
access : read-write
cfg_en_auto_sub_pckt_num : Enable automatics sub packet number. When enabled number of sub-packts will be set according to MEM FIFO number of samples.
bits : 15 - 15 (1 bit)
access : read-write
cfg_sample_present : Sample present bits if force them is active
bits : 16 - 19 (4 bit)
access : read-write
cfg_sample_present_force : Force sample present bits
bits : 20 - 20 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 21 - 31 (11 bit)
access : read-only
no description available
address_offset : 0x30088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fifo_sw_rst : Resets Fifo's write and read pointers. When FIFO configuration bits change this signal should be high (due to synchronization issues).
bits : 0 - 0 (1 bit)
access : read-write
sync_wr_to_ch_zero : When high the last channel index synchronizes the write addresses (to the next channel group)
bits : 1 - 1 (1 bit)
access : read-write
fifo_dir : 0 - smpl2pkt (inc_step=number of I2S ports), 1 - pkt2smpl (inc_step=num_ch_per_port)
bits : 2 - 2 (1 bit)
access : read-write
fifo_empty_calc : 0- Empty is a function of read address. 1 - Empty is a function of BASE read address.
bits : 3 - 3 (1 bit)
access : read-write
cfg_dis_port3 : 0 - Normal Operation. 1 - I2S port 3 is disabled (user should ignore its outputs). This allows for 24-ch, 12-ch, 6-ch transfer.
bits : 4 - 4 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 5 - 31 (27 bit)
access : read-only
no description available
address_offset : 0x3008C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
wfull : Indicates FIFO Full - indication comes with delay caused by Synchronization.
bits : 0 - 0 (1 bit)
access : read-only
rempty : Indicates FIFO Empty - indication comes with delay caused by Synchronization.
bits : 1 - 1 (1 bit)
access : read-only
overrun : Indicates a FIFO overrun error has occured - FIFO written to when it was full.
bits : 2 - 2 (1 bit)
access : read-only
underrun : Indicates a FIFO underrun error has occured - FIFO read when it was empty.
bits : 3 - 3 (1 bit)
access : read-only
reserved_0 : reserved_0
bits : 4 - 31 (28 bit)
access : read-only
no description available
address_offset : 0x30090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
cfg_mem_fifo_thrsh1 : If number of samples in MEM FIFO is below Threshold 1: Each Packet will contain only 1 subpacket.
bits : 0 - 7 (8 bit)
access : read-write
cfg_mem_fifo_thrsh2 : If number of samples in MEM FIFO is below Threshold2: Each Packet will contain only 2 subpacket.
bits : 8 - 15 (8 bit)
access : read-write
cfg_mem_fifo_thrsh3 : If number of samples in MEM FIFO is below Threshold 3: Each Packet will contain only 3 subpacket.
bits : 16 - 23 (8 bit)
access : read-write
reserved_0 : reserved_0
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x30800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wr_addr : 4 MSB of the packet memory address in which the data is written.
bits : 0 - 3 (4 bit)
access : read-write
reserved_0 : reserved_0
bits : 4 - 31 (28 bit)
access : read-only
no description available
address_offset : 0x30804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
host_wr : Write request bit for the host write transaction.
bits : 0 - 0 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
no description available
address_offset : 0x30808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_addr : 4 MSB of the packet memory address from which the data is read.
bits : 0 - 3 (4 bit)
access : read-write
reserved_0 : reserved_0
bits : 4 - 31 (28 bit)
access : read-only
no description available
address_offset : 0x3080C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
host_rd : Read request bit for the host read transaction
bits : 0 - 0 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
no description available
address_offset : 0x30810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data_wr : The 32 bits of the data to be written to the packet memory. When written to this register fifo1_wr_enable will be asserted.
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x30814 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
fifo2_data_out : The 32 bits of the data to be read from the packet memory. When read from this register fifo2_rd_enable will be asserted.
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x30818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fifo1_flush : Fifo1 flush bit
bits : 0 - 0 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
no description available
address_offset : 0x3081C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fifo2_flush : Fifo2 flush bit
bits : 0 - 0 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
no description available
address_offset : 0x30820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
source_pkt_mem_ctrl_fsm_state : State of the FSM that controls packet memory transactions.
bits : 0 - 1 (2 bit)
access : read-only
fifo1_full : Fifo1 full indication
bits : 2 - 2 (1 bit)
access : read-only
fifo2_empty : Fifo2 empty indication
bits : 3 - 3 (1 bit)
access : read-only
reserved_0 : reserved_0
bits : 4 - 31 (28 bit)
access : read-only
no description available
address_offset : 0x30824 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
host_wr_done_int : Indication that the host write transaction finished.
bits : 0 - 0 (1 bit)
access : read-only
host_rd_done_int : Indication that the host read transaction finished.
bits : 1 - 1 (1 bit)
access : read-only
nonvalid_type_requested_int : Indication that nonvalid type of packet is requested by the packet interface.
bits : 2 - 2 (1 bit)
access : read-only
pslverr : APB slave error interrupt
bits : 3 - 3 (1 bit)
access : read-only
alloc_wr_done : Successful write to the allocation table.
bits : 4 - 4 (1 bit)
access : read-only
alloc_wr_error : Error happened, invalid write to the allocation table.
bits : 5 - 5 (1 bit)
access : read-only
fifo1_overflow : Fifo1 overflow indication
bits : 6 - 6 (1 bit)
access : read-only
fifo1_underflow : Fifo1 underflow indication
bits : 7 - 7 (1 bit)
access : read-only
fifo2_overflow : Fifo2 overflow indication
bits : 8 - 8 (1 bit)
access : read-only
fifo2_underflow : Fifo2 underflow indication
bits : 9 - 9 (1 bit)
access : read-only
reserved_0 : reserved_0
bits : 10 - 31 (22 bit)
access : read-only
no description available
address_offset : 0x30828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
host_wr_done_int_mask : Masks the host_wr_done_int interrupt
bits : 0 - 0 (1 bit)
access : read-write
host_rd_done_int_mask : Masks the host_rd_done_int interrupt
bits : 1 - 1 (1 bit)
access : read-write
nonvalid_type_requested_int_mask : Masks the nonvalid_type_requested_int interrupt
bits : 2 - 2 (1 bit)
access : read-write
pslverr_mask : Masks the pslverr interrupt
bits : 3 - 3 (1 bit)
access : read-write
alloc_wr_done_mask : Masks the alloc_wr_done interrupt
bits : 4 - 4 (1 bit)
access : read-write
alloc_wr_error_mask : Masks the alloc_wr_error interrupt
bits : 5 - 5 (1 bit)
access : read-write
fifo1_overflow_mask : Masks the fifo1_overflow interrupt
bits : 6 - 6 (1 bit)
access : read-write
fifo1_underflow_mask : Masks the fifo1_underflow interrupt
bits : 7 - 7 (1 bit)
access : read-write
fifo2_overflow_mask : Masks the fifo2_overflow interrupt
bits : 8 - 8 (1 bit)
access : read-write
fifo2_underflow_mask : Masks the fifo2_underflow interrupt
bits : 9 - 9 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 10 - 31 (22 bit)
access : read-only
no description available
address_offset : 0x3082C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pkt_alloc_address : Address of the register in the source allocation table
bits : 0 - 3 (4 bit)
access : read-write
reserved_0 : reserved_0
bits : 4 - 7 (4 bit)
access : read-only
packet_type : Type of packet
bits : 8 - 15 (8 bit)
access : read-write
type_valid : 1 for valid, 0 for nonvalid
bits : 16 - 16 (1 bit)
access : read-write
active_idle_type : active_idle_type
bits : 17 - 17 (1 bit)
access : read-write
reserved_1 : reserved_1
bits : 18 - 31 (14 bit)
access : read-only
no description available
address_offset : 0x30830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pkt_alloc_wr_en : Enable bit for writing to the allocation table
bits : 0 - 0 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
no description available
address_offset : 0x30834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sw_rst : Software reset
bits : 0 - 0 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
no description available
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mailbox_int_mask : Mailbox Interupt mask Bit[0] - Empty Bit[1] - Full
bits : 0 - 1 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 2 - 31 (30 bit)
access : read-only
no description available
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
mailbox_int_status : Mailbox Interupt Status Bit[0] - Empty Bit[1] - Full
bits : 0 - 1 (2 bit)
access : read-only
reserved_0 : reserved_0
bits : 2 - 31 (30 bit)
access : read-only
no description available
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sw_clock_val_l : Fractial of the clock decimal value
bits : 0 - 7 (8 bit)
access : read-write
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
xt_int_polarity : xt_int_polarity
bits : 0 - 1 (2 bit)
access : read-write
reserved_0 : reserved_0
bits : 2 - 31 (30 bit)
access : read-only
no description available
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sw_clock_val_h : Clock frequency in decimal values
bits : 0 - 7 (8 bit)
access : read-write
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sw_events7_0 : When SW writes it updted just the extra event bits When Host read it is cleared
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sw_events15_8 : When SW writes it updted just the extra event bits When Host read it is cleared
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sw_events23_16 : When SW writes it updted just the extra event bits When Host read it is cleared
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
sw_events31_24 : When SW writes it updted just the extra event bits When Host read it is cleared
bits : 0 - 7 (8 bit)
access : read-only
reserved_0 : reserved_0
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
xt_dreset : Xtensa Dreset control register
bits : 0 - 0 (1 bit)
access : read-write
xt_ocdhaltonreset : Xtensa Halt On Reget configuration register
bits : 1 - 1 (1 bit)
access : read-write
reserved_0 : reserved_0
bits : 2 - 31 (30 bit)
access : read-only
no description available
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
xt_xocdmode : Xtensa OCD mode configuration
bits : 0 - 0 (1 bit)
access : read-only
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
no description available
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
apb_intr_mask : Mask the APB interupt Bit0 - Mailbox Interupt Bit1 - PIF Interupt Bit2 - CEC Interupt
bits : 0 - 2 (3 bit)
access : read-write
reserved_0 : reserved_0
bits : 3 - 31 (29 bit)
access : read-only
no description available
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
apb_intr_status : APB interupt STATUS Bit0 - Mailbox Interupt Bit1 - PIF Interupt Bit2 - CEC Interupt
bits : 0 - 2 (3 bit)
access : read-only
reserved_0 : reserved_0
bits : 3 - 31 (29 bit)
access : read-only
no description available
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
mailbox_full : Mailboxes full indication
bits : 0 - 0 (1 bit)
access : read-only
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
no description available
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
mailbox_empty : Mailboxes Empty indication
bits : 0 - 0 (1 bit)
access : read-only
reserved_0 : reserved_0
bits : 1 - 31 (31 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.