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MCM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

FADR

FATR

FDR

PLASC

PLAMC

PLACR


FADR

Fault address register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FADR FADR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Fault address
bits : 0 - 31 (32 bit)
access : read-only


FATR

Fault attributes register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FATR FATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BEDA BEMD BESZ BEWT BEMN BEOVR

BEDA : Bus error access type
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : BEDA_0

Instruction

0x1 : BEDA_1

Data

End of enumeration elements list.

BEMD : Bus error privilege level
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : BEMD_0

User mode

0x1 : BEMD_1

Supervisor/privileged mode

End of enumeration elements list.

BESZ : Bus error size
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

0 : BESZ_0

8-bit access

0x1 : BESZ_1

16-bit access

0x2 : BESZ_2

32-bit access

End of enumeration elements list.

BEWT : Bus error write
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

0 : BEWT_0

Read access

0x1 : BEWT_1

Write access

End of enumeration elements list.

BEMN : Bus error master number
bits : 8 - 11 (4 bit)
access : read-only

BEOVR : Bus error overrun
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : BEOVR_0

No bus error overrun

0x1 : BEOVR_1

Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.

End of enumeration elements list.


FDR

Fault data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDR FDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Fault data
bits : 0 - 31 (32 bit)
access : read-only


PLASC

Crossbar Switch (AXBS) Slave Configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLASC PLASC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASC

ASC : Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

0 : ASC_0

A bus slave connection to AXBS input port n is absent

0x1 : ASC_1

A bus slave connection to AXBS input port n is present

End of enumeration elements list.


PLAMC

Crossbar Switch (AXBS) Master Configuration
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLAMC PLAMC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC

AMC : Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

0 : AMC_0

A bus master connection to AXBS input port n is absent

0x1 : AMC_1

A bus master connection to AXBS input port n is present

End of enumeration elements list.


PLACR

Crossbar Switch (AXBS) Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLACR PLACR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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