Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8008 byte (0x0)
mem_usage : registers
protection : not protected
25M Oscillator Control Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSC_ALC_CTL : Automatic Level Controller Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : OSC_ALC_CTL_0
Enable automatic level controller
0x1 : OSC_ALC_CTL_1
Disable automatic level controller
End of enumeration elements list.
OSC_HYST_CTL : Hysteresis Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : OSC_HYST_CTL_0
Enable hysteresis control
0x1 : OSC_HYST_CTL_1
Disable hysteresis control
End of enumeration elements list.
OSC_GM_SEL : Crystal overdrive protection
bits : 4 - 6 (3 bit)
access : read-write
OSC_INT_STU : Crystal oscillator clock interrupt This bit is set by hardware when OSCCNT counter reaches the count value EOCV x 512
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : OSC_INT_STU_0
No oscillator clock interrupt occurred
0x1 : OSC_INT_STU_1
Oscillator clock interrupt pending
End of enumeration elements list.
OSC_DIV : Crystal oscillator clock division factor These bits specify the crystal oscillator output clock division factor
bits : 8 - 12 (5 bit)
access : read-write
OSC_OK_BYPASS : OSC ok output bypass
bits : 13 - 13 (1 bit)
access : read-write
OSC_INT_MASK : Crystal oscillator clock interrupt mask This bit masks the I_OSC interrupt bit.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : OSC_INT_MASK_0
Crystal oscillator clock interrupt is masked
0x1 : OSC_INT_MASK_1
Crystal oscillator clock interrupt is enabled
End of enumeration elements list.
OSC_EOCV : End of Count Value These bits specify the end of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state
bits : 16 - 23 (8 bit)
access : read-write
OSC_GM_TST_SEL : Test mode GM measurement
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : OSC_GM_TST_SEL_0
Normal run mode
0x1 : OSC_GM_TST_SEL_1
Enable test mode measurement of GM
End of enumeration elements list.
OSC_BYPSS : Crystal Oscillator bypass This bit specifies whether the oscillator should be bypassed or not
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : OSC_BYPSS_0
Oscillator output is used as root clock.
0x1 : OSC_BYPSS_1
EXTAL is used as root clock
End of enumeration elements list.
25M Oscillator Test Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOSC_TESTEN : 25M Oscillator Test Enable
bits : 31 - 31 (1 bit)
access : read-write
27M Oscillator Control Configuration Register
address_offset : 0x8000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSC_ALC_CTL : Automatic Level Controller Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : OSC_ALC_CTL_0
Enable automatic level controller
0x1 : OSC_ALC_CTL_1
Disable automatic level controller
End of enumeration elements list.
OSC_HYST_CTL : Hysteresis Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : OSC_HYST_CTL_0
Enable hysteresis control
0x1 : OSC_HYST_CTL_1
Disable hysteresis control
End of enumeration elements list.
OSC_GM_SEL : Crystal overdrive protection
bits : 4 - 6 (3 bit)
access : read-write
OSC_INT_STU : Crystal oscillator clock interrupt This bit is set by hardware when OSCCNT counter reaches the count value EOCV x 512
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : OSC_INT_STU_0
No oscillator clock interrupt occurred
0x1 : OSC_INT_STU_1
Oscillator clock interrupt pending
End of enumeration elements list.
OSC_DIV : Crystal oscillator clock division factor These bits specify the crystal oscillator output clock division factor
bits : 8 - 12 (5 bit)
access : read-write
OSC_OK_BYPASS : OSC ok output bypass
bits : 13 - 13 (1 bit)
access : read-write
OSC_INT_MASK : Crystal oscillator clock interrupt mask This bit masks the I_OSC interrupt bit.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : OSC_INT_MASK_0
Crystal oscillator clock interrupt is masked
0x1 : OSC_INT_MASK_1
Crystal oscillator clock interrupt is enabled
End of enumeration elements list.
OSC_EOCV : End of Count Value These bits specify the end of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state
bits : 16 - 23 (8 bit)
access : read-write
OSC_GM_TST_SEL : Test mode GM measurement
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : OSC_GM_TST_SEL_0
Normal run mode
0x1 : OSC_GM_TST_SEL_1
Enable test mode measurement of GM
End of enumeration elements list.
OSC_BYPSS : Crystal Oscillator bypass This bit specifies whether the oscillator should be bypassed or not
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : OSC_BYPSS_0
Oscillator output is used as root clock.
0x1 : OSC_BYPSS_1
EXTAL is used as root clock
End of enumeration elements list.
27M Oscillator Test Configuration Register
address_offset : 0x8004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOSC_TESTEN : 27M Oscillator Test Enable
bits : 31 - 31 (1 bit)
access : read-write
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