\n
address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
no description available
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_pd_dphy : DPHY PD_DPHY input control. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 0 (1 bit)
access : read-write
no description available
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_mc_prg_hs_zero : DPHY mc_PRG_HS_ZERO input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x20 : dphy_mc_prg_hs_zero_32
32
0x21 : dphy_mc_prg_hs_zero_33
33
0x22 : dphy_mc_prg_hs_zero_34
34
0x23 : dphy_mc_prg_hs_zero_35
35
0x24 : dphy_mc_prg_hs_zero_36
36
0x25 : dphy_mc_prg_hs_zero_37
37
0x26 : dphy_mc_prg_hs_zero_38
38
0x27 : dphy_mc_prg_hs_zero_39
39
0x28 : dphy_mc_prg_hs_zero_40
40
0x29 : dphy_mc_prg_hs_zero_41
41
0x2A : dphy_mc_prg_hs_zero_42
42
0x2B : dphy_mc_prg_hs_zero_43
43
0x2C : dphy_mc_prg_hs_zero_44
44
0x2D : dphy_mc_prg_hs_zero_45
45
0x2E : dphy_mc_prg_hs_zero_46
46
0x2F : dphy_mc_prg_hs_zero_47
47
0x30 : dphy_mc_prg_hs_zero_48
48
0x31 : dphy_mc_prg_hs_zero_49
49
0x32 : dphy_mc_prg_hs_zero_50
50
0x33 : dphy_mc_prg_hs_zero_51
51
0x34 : dphy_mc_prg_hs_zero_52
52
0x35 : dphy_mc_prg_hs_zero_53
53
0x36 : dphy_mc_prg_hs_zero_54
54
0x37 : dphy_mc_prg_hs_zero_55
55
0x38 : dphy_mc_prg_hs_zero_56
56
0x39 : dphy_mc_prg_hs_zero_57
57
0x3A : dphy_mc_prg_hs_zero_58
58
0x3B : dphy_mc_prg_hs_zero_59
59
0x3C : dphy_mc_prg_hs_zero_60
60
0x3D : dphy_mc_prg_hs_zero_61
61
0x3E : dphy_mc_prg_hs_zero_62
62
0x3F : dphy_mc_prg_hs_zero_63
63
End of enumeration elements list.
no description available
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_m_prg_hs_trail : DPHY m_PRG_HS_TRAIL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : dphy_m_prg_hs_trail_0
0
0x1 : dphy_m_prg_hs_trail_1
1
0x2 : dphy_m_prg_hs_trail_2
2
0x3 : dphy_m_prg_hs_trail_3
3
0x4 : dphy_m_prg_hs_trail_4
4
0x5 : dphy_m_prg_hs_trail_5
5
0x6 : dphy_m_prg_hs_trail_6
6
0x7 : dphy_m_prg_hs_trail_7
7
0x8 : dphy_m_prg_hs_trail_8
8
0x9 : dphy_m_prg_hs_trail_9
9
0xA : dphy_m_prg_hs_trail_10
10
0xB : dphy_m_prg_hs_trail_11
11
0xC : dphy_m_prg_hs_trail_12
12
0xD : dphy_m_prg_hs_trail_13
13
0xE : dphy_m_prg_hs_trail_14
14
0xF : dphy_m_prg_hs_trail_15
15
End of enumeration elements list.
no description available
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_mc_prg_hs_trail : DPHY mc_PRG_HS_TRAIL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : dphy_mc_prg_hs_trail_0
0
0x1 : dphy_mc_prg_hs_trail_1
1
0x2 : dphy_mc_prg_hs_trail_2
2
0x3 : dphy_mc_prg_hs_trail_3
3
0x4 : dphy_mc_prg_hs_trail_4
4
0x5 : dphy_mc_prg_hs_trail_5
5
0x6 : dphy_mc_prg_hs_trail_6
6
0x7 : dphy_mc_prg_hs_trail_7
7
0x8 : dphy_mc_prg_hs_trail_8
8
0x9 : dphy_mc_prg_hs_trail_9
9
0xA : dphy_mc_prg_hs_trail_10
10
0xB : dphy_mc_prg_hs_trail_11
11
0xC : dphy_mc_prg_hs_trail_12
12
0xD : dphy_mc_prg_hs_trail_13
13
0xE : dphy_mc_prg_hs_trail_14
14
0xF : dphy_mc_prg_hs_trail_15
15
End of enumeration elements list.
no description available
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD : DPHY PD_PLL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 0 (1 bit)
access : read-write
no description available
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TST : DPHY TST input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 5 (6 bit)
access : read-write
no description available
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CN : DPHY PLL Input Divider
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : CN_0
Divide by 2
0x1 : CN_1
Divide by 32
0x2 : CN_2
Divide by 11
0x3 : CN_3
Divide by 31
0x4 : CN_4
Divide by 10
0x5 : CN_5
Divide by 26
0x6 : CN_6
Divide by 30
0x7 : CN_7
Divide by 7
0x8 : CN_8
Divide by 13
0x9 : CN_9
Divide by 9
0xA : CN_10
Divide by 15
0xB : CN_11
Divide by 25
0xC : CN_12
Divide by 29
0xD : CN_13
Divide by 23
0xE : CN_14
Divide by 6
0xF : CN_15
Divide by 20
0x10 : CN_16
Divide by 3
0x11 : CN_17
Divide by 12
0x12 : CN_18
Divide by 27
0x13 : CN_19
Divide by 8
0x14 : CN_20
Divide by 14
0x15 : CN_21
Divide by 16
0x16 : CN_22
Divide by 24
0x17 : CN_23
Divide by 21
0x18 : CN_24
Divide by 4
0x19 : CN_25
Divide by 28
0x1A : CN_26
Divide by 17
0x1B : CN_27
Divide by 22
0x1C : CN_28
Divide by 5
0x1D : CN_29
Divide by 18
0x1E : CN_30
Divide by 19
0x1F : CN_31
Divide by 1
End of enumeration elements list.
no description available
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM : DPHY PLL Feedback Divider
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : CM_0
Divide by 128
0x7F : CM_127
Divide by 255
0x80 : CM_128
Divide by 64
0xBF : CM_191
Divide by 127
0xC0 : CM_192
Divide by 32
0xDF : CM_223
Divide by 63
#111x0000 : CM_224
Divide by 16
#111x1111 : CM_239
Divide by 31
End of enumeration elements list.
no description available
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CO : DPHY PLL Output Divider
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : CO_0
Divide by 1
0x1 : CO_1
Divide by 2
0x2 : CO_2
Divide by 4
0x3 : CO_3
Divide by 8
End of enumeration elements list.
no description available
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCK : DPHY PLL LOCK output. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 0 (1 bit)
access : read-only
no description available
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_lock_byp : DPHY LOCK_BYP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 0 (1 bit)
access : read-write
no description available
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_rterm_sel : DPHY RTERM_SEL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 0 (1 bit)
access : read-write
no description available
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_auto_pd_en : DPHY AUTO_PD_EN input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 0 (1 bit)
access : read-write
no description available
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_m_prg_hs_prepare : DPHY m_PRG_HS_PREPARE input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : dphy_m_prg_hs_prepare_0
1
0x1 : dphy_m_prg_hs_prepare_1
1.5
0x2 : dphy_m_prg_hs_prepare_2
2
0x3 : dphy_m_prg_hs_prepare_3
2.5
End of enumeration elements list.
no description available
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_rxlprp : DPHY RXLPRP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 1 (2 bit)
access : read-write
no description available
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_rxcdrp : DPHY RXCDRP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 1 (2 bit)
access : read-write
no description available
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_mc_prg_hs_prepare : DPHY mc_PRG_HS_PREPARE input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : dphy_mc_prg_hs_prepare_0
1
0x1 : dphy_mc_prg_hs_prepare_1
1.5
End of enumeration elements list.
no description available
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dphy_m_prg_hs_zero : DPHY m_PRG_HS_ZERO input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : dphy_m_prg_hs_zero_0
0
0x1 : dphy_m_prg_hs_zero_1
1
0x2 : dphy_m_prg_hs_zero_2
2
0x3 : dphy_m_prg_hs_zero_3
3
0x4 : dphy_m_prg_hs_zero_4
4
0x5 : dphy_m_prg_hs_zero_5
5
0x6 : dphy_m_prg_hs_zero_6
6
0x7 : dphy_m_prg_hs_zero_7
7
0x8 : dphy_m_prg_hs_zero_8
8
0x9 : dphy_m_prg_hs_zero_9
9
0xA : dphy_m_prg_hs_zero_10
10
0xB : dphy_m_prg_hs_zero_11
11
0xC : dphy_m_prg_hs_zero_12
12
0xD : dphy_m_prg_hs_zero_13
13
0xE : dphy_m_prg_hs_zero_14
14
0xF : dphy_m_prg_hs_zero_15
15
0x10 : dphy_m_prg_hs_zero_16
16
0x11 : dphy_m_prg_hs_zero_17
17
0x12 : dphy_m_prg_hs_zero_18
18
0x13 : dphy_m_prg_hs_zero_19
19
0x14 : dphy_m_prg_hs_zero_20
20
0x15 : dphy_m_prg_hs_zero_21
21
0x16 : dphy_m_prg_hs_zero_22
22
0x17 : dphy_m_prg_hs_zero_23
23
0x18 : dphy_m_prg_hs_zero_24
24
0x19 : dphy_m_prg_hs_zero_25
25
0x1A : dphy_m_prg_hs_zero_26
26
0x1B : dphy_m_prg_hs_zero_27
27
0x1C : dphy_m_prg_hs_zero_28
28
0x1D : dphy_m_prg_hs_zero_29
29
0x1E : dphy_m_prg_hs_zero_30
30
0x1F : dphy_m_prg_hs_zero_31
31
End of enumeration elements list.
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