\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
no description available
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
csi2rx_cfg_num_lanes : Sets the number of active lanes that are to be used for receiving data.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : csi2rx_cfg_num_lanes_0
1 Lane
0x1 : csi2rx_cfg_num_lanes_1
2 Lane
0x2 : csi2rx_cfg_num_lanes_2
3 Lane
0x3 : csi2rx_cfg_num_lanes_3
4 Lane
End of enumeration elements list.
no description available
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
csi2rx_irq_mask : CSI2 RX IRQ Mask setting
bits : 0 - 8 (9 bit)
access : read-write
no description available
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
csi2rx_ulps_status : Status of RX DPHY ULPS state
bits : 0 - 9 (10 bit)
access : read-only
no description available
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
csi2rx_ppi_errsot_hs : CSI2 RX DPHY PPI ErrSotHS captured status from the DPHY.
bits : 0 - 3 (4 bit)
access : read-only
no description available
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
csi2rx_ppi_errsotsync_hs : CSI2 RX DPHY PPI ErrSotSync_HS captured status from the DPHY.
bits : 0 - 3 (4 bit)
access : read-only
no description available
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
csi2rx_ppi_erresc : CSI2 RX DPHY PPI ErrEsc captured status from the DPHY.
bits : 0 - 3 (4 bit)
access : read-only
no description available
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
csi2rx_ppi_errsyncesc : CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY.
bits : 0 - 3 (4 bit)
access : read-only
no description available
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
csi2rx_ppi_errcontrol : CSI2 RX DPHY PPI ErrControl captured status from the DPHY.
bits : 0 - 3 (4 bit)
access : read-only
no description available
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
csi2rx_cfg_disable_payload_null : Null
bits : 0 - 0 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_blank : Blank
bits : 1 - 1 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_embedded : Embedded
bits : 2 - 2 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_legacy_yuv_8 : Legacy YUV 420 8 bit
bits : 10 - 10 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_yuv_8 : YUV422 8 bit
bits : 14 - 14 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_yuv_10 : YUV422 10 bit
bits : 15 - 15 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_rgb444 : RGB444
bits : 16 - 16 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_rgb555 : RGB555
bits : 17 - 17 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_rgb565 : RGB565
bits : 18 - 18 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_rgb666 : RGB666
bits : 19 - 19 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_rgb888 : RGB888
bits : 20 - 20 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_raw6 : RAW6
bits : 24 - 24 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_raw7 : RAW7
bits : 25 - 25 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_raw8 : RAW8
bits : 26 - 26 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_raw10 : RAW10
bits : 27 - 27 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_raw12 : RAW12
bits : 28 - 28 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_raw14 : RAW14
bits : 29 - 29 (1 bit)
access : read-write
no description available
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
csi2rx_cfg_disable_payload_udef_30 : User defined type 0x31
bits : 0 - 0 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_udef_31 : User defined type 0x32
bits : 1 - 1 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_udef_32 : User defined type 0x33
bits : 2 - 2 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_udef_33 : User defined type 0x34
bits : 3 - 3 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_udef_34 : User defined type 0x35
bits : 4 - 4 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_udef_35 : User defined type 0x35
bits : 5 - 5 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_udef_36 : User defined type 0x36
bits : 6 - 6 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_udef_37 : User defined type 0x37
bits : 7 - 7 (1 bit)
access : read-write
csi2rx_cfg_disable_payload_unsupported : Unsupported Data Types
bits : 16 - 16 (1 bit)
access : read-write
no description available
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
csi2rx_cfg_disable_data_lanes : Setting bits to a '1' value causes the DPHY Enable signal to deassert.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : csi2rx_cfg_disable_data_lanes_1
Data Lane 0
0x2 : csi2rx_cfg_disable_data_lanes_2
Data Lane 1
0x4 : csi2rx_cfg_disable_data_lanes_4
Data Lane 2
0x8 : csi2rx_cfg_disable_data_lanes_8
Data Lane 3
End of enumeration elements list.
no description available
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
csi2rx_bit_err : BIT_ERR: CSI-2 RX Controller ECC and CRC error status.
bits : 0 - 9 (10 bit)
access : read-only
no description available
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
csi2rx_irq_status : CSI2 RX IRQ status
bits : 0 - 8 (9 bit)
access : read-only
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