Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection : not protected
Hardware BCH ECC Accelerator Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPLETE_IRQ : This bit indicates the state of the external interrupt line
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : This field is reserved.
bits : 1 - 1 (1 bit)
access : read-only
DEBUG_STALL_IRQ : DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit.
bits : 2 - 2 (1 bit)
access : read-write
BM_ERROR_IRQ : AHB Bus interface Error Interrupt Status
bits : 3 - 3 (1 bit)
access : read-write
RSVD1 : This field is reserved.
bits : 4 - 7 (4 bit)
access : read-only
COMPLETE_IRQ_EN : 1 = interrupt on completion of correction is enabled.
bits : 8 - 8 (1 bit)
access : read-write
RSVD2 : This field is reserved.
bits : 9 - 9 (1 bit)
access : read-only
DEBUG_STALL_IRQ_EN : 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block
bits : 10 - 10 (1 bit)
access : read-write
RSVD3 : This field is reserved.
bits : 11 - 15 (5 bit)
access : read-only
M2M_ENABLE : NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION
bits : 16 - 16 (1 bit)
access : read-write
M2M_ENCODE : Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations.
bits : 17 - 17 (1 bit)
access : read-write
M2M_LAYOUT : Selects the flash page format for memory-to-memory operations.
bits : 18 - 19 (2 bit)
access : read-write
RSVD4 : This field is reserved.
bits : 20 - 21 (2 bit)
access : read-only
DEBUGSYNDROME : (For debug purposes only)
bits : 22 - 22 (1 bit)
access : read-write
RSVD5 : This field is reserved.
bits : 23 - 29 (7 bit)
access : read-only
CLKGATE : This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Allow BCH to operate normally.
0x1 : NO_CLKS
Do not clock BCH gates in order to minimize power consumption.
End of enumeration elements list.
SFTRST : Set this bit to 0 to enable normal BCH operation
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : RUN
Allow BCH to operate normally.
0x1 : RESET
Hold BCH in reset.
End of enumeration elements list.
Hardware ECC Accelerator Status Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : This field is reserved.
bits : 0 - 1 (2 bit)
access : read-only
UNCORRECTABLE : 1 = Uncorrectable error encountered during last processing cycle.
bits : 2 - 2 (1 bit)
access : read-only
CORRECTED : 1 = At least one correctable error encountered during last processing cycle.
bits : 3 - 3 (1 bit)
access : read-only
ALLONES : 1 = All data bits of this transaction are ONE.
bits : 4 - 4 (1 bit)
access : read-only
RSVD1 : This field is reserved.
bits : 5 - 7 (3 bit)
access : read-only
STATUS_BLK0 : Count of symbols in error during processing of first block of flash (metadata block)
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
0 : ZERO
No errors found on block.
0x1 : ERROR1
One error found on block.
0x2 : ERROR2
One errors found on block.
0x3 : ERROR3
One errors found on block.
0x4 : ERROR4
One errors found on block.
0xFE : UNCORRECTABLE
Block exhibited uncorrectable errors.
0xFF : ERASED
Page is erased.
End of enumeration elements list.
COMPLETED_CE : This is the chip enable number corresponding to the NAND device from which this data came.
bits : 16 - 19 (4 bit)
access : read-only
HANDLE : Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction
bits : 20 - 31 (12 bit)
access : read-only
Hardware BCH ECC Debug Register0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEBUG_REG_SELECT : The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : This field is reserved.
bits : 6 - 7 (2 bit)
access : read-only
BM_KES_TEST_BYPASS : 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
KES_DEBUG_STALL : Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
KES FSM proceeds to next block supplied by bus master.
0x1 : WAIT
KES FSM waits after current equations are solved and the search engine is started.
End of enumeration elements list.
KES_DEBUG_STEP : Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block
bits : 10 - 10 (1 bit)
access : read-write
KES_STANDALONE : Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
KES_DEBUG_KICK : Toggling causes KES engine FSM to start as if kick by the Bus Master
bits : 12 - 12 (1 bit)
access : read-write
KES_DEBUG_MODE4K : When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages)
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x1 : 4k
Mode is set for 4K NAND pages.
End of enumeration elements list.
KES_DEBUG_PAYLOAD_FLAG : When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x1 : DATA
Payload is set for 512 bytes data block.
End of enumeration elements list.
KES_DEBUG_SHIFT_SYND : Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine
bits : 15 - 15 (1 bit)
access : read-write
KES_DEBUG_SYNDROME_SYMBOL : The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled
bits : 16 - 24 (9 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
RSVD1 : This field is reserved.
bits : 25 - 31 (7 bit)
access : read-only
Hardware BCH ECC Debug Register0
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEBUG_REG_SELECT : The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : This field is reserved.
bits : 6 - 7 (2 bit)
access : read-only
BM_KES_TEST_BYPASS : 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
KES_DEBUG_STALL : Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
KES FSM proceeds to next block supplied by bus master.
0x1 : WAIT
KES FSM waits after current equations are solved and the search engine is started.
End of enumeration elements list.
KES_DEBUG_STEP : Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block
bits : 10 - 10 (1 bit)
access : read-write
KES_STANDALONE : Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
KES_DEBUG_KICK : Toggling causes KES engine FSM to start as if kick by the Bus Master
bits : 12 - 12 (1 bit)
access : read-write
KES_DEBUG_MODE4K : When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages)
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x1 : 4k
Mode is set for 4K NAND pages.
End of enumeration elements list.
KES_DEBUG_PAYLOAD_FLAG : When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x1 : DATA
Payload is set for 512 bytes data block.
End of enumeration elements list.
KES_DEBUG_SHIFT_SYND : Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine
bits : 15 - 15 (1 bit)
access : read-write
KES_DEBUG_SYNDROME_SYMBOL : The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled
bits : 16 - 24 (9 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
RSVD1 : This field is reserved.
bits : 25 - 31 (7 bit)
access : read-only
Hardware BCH ECC Debug Register0
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEBUG_REG_SELECT : The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : This field is reserved.
bits : 6 - 7 (2 bit)
access : read-only
BM_KES_TEST_BYPASS : 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
KES_DEBUG_STALL : Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
KES FSM proceeds to next block supplied by bus master.
0x1 : WAIT
KES FSM waits after current equations are solved and the search engine is started.
End of enumeration elements list.
KES_DEBUG_STEP : Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block
bits : 10 - 10 (1 bit)
access : read-write
KES_STANDALONE : Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
KES_DEBUG_KICK : Toggling causes KES engine FSM to start as if kick by the Bus Master
bits : 12 - 12 (1 bit)
access : read-write
KES_DEBUG_MODE4K : When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages)
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x1 : 4k
Mode is set for 4K NAND pages.
End of enumeration elements list.
KES_DEBUG_PAYLOAD_FLAG : When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x1 : DATA
Payload is set for 512 bytes data block.
End of enumeration elements list.
KES_DEBUG_SHIFT_SYND : Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine
bits : 15 - 15 (1 bit)
access : read-write
KES_DEBUG_SYNDROME_SYMBOL : The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled
bits : 16 - 24 (9 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
RSVD1 : This field is reserved.
bits : 25 - 31 (7 bit)
access : read-only
Hardware BCH ECC Debug Register0
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEBUG_REG_SELECT : The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : This field is reserved.
bits : 6 - 7 (2 bit)
access : read-only
BM_KES_TEST_BYPASS : 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
KES_DEBUG_STALL : Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
KES FSM proceeds to next block supplied by bus master.
0x1 : WAIT
KES FSM waits after current equations are solved and the search engine is started.
End of enumeration elements list.
KES_DEBUG_STEP : Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block
bits : 10 - 10 (1 bit)
access : read-write
KES_STANDALONE : Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
KES_DEBUG_KICK : Toggling causes KES engine FSM to start as if kick by the Bus Master
bits : 12 - 12 (1 bit)
access : read-write
KES_DEBUG_MODE4K : When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages)
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x1 : 4k
Mode is set for 4K NAND pages.
End of enumeration elements list.
KES_DEBUG_PAYLOAD_FLAG : When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x1 : DATA
Payload is set for 512 bytes data block.
End of enumeration elements list.
KES_DEBUG_SHIFT_SYND : Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine
bits : 15 - 15 (1 bit)
access : read-write
KES_DEBUG_SYNDROME_SYMBOL : The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled
bits : 16 - 24 (9 bit)
access : read-write
Enumeration:
0 : NORMAL
Bus master address generator for SYND_GEN writes operates normally.
0x1 : TEST_MODE
Bus master address generator always addresses last four bytes in Auxiliary block.
End of enumeration elements list.
RSVD1 : This field is reserved.
bits : 25 - 31 (7 bit)
access : read-only
KES Debug Read Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : This register returns the ROM BIST CRC value after a BIST test.
bits : 0 - 31 (32 bit)
access : read-only
KES Debug Read Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : This register returns the ROM BIST CRC value after a BIST test.
bits : 0 - 31 (32 bit)
access : read-only
KES Debug Read Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : This register returns the ROM BIST CRC value after a BIST test.
bits : 0 - 31 (32 bit)
access : read-only
KES Debug Read Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : This register returns the ROM BIST CRC value after a BIST test.
bits : 0 - 31 (32 bit)
access : read-only
Chien Search Debug Read Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Chien Search Debug Read Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Chien Search Debug Read Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Chien Search Debug Read Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Syndrome Generator Debug Read Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Syndrome Generator Debug Read Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Syndrome Generator Debug Read Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Syndrome Generator Debug Read Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Hardware ECC Accelerator Status Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : This field is reserved.
bits : 0 - 1 (2 bit)
access : read-only
UNCORRECTABLE : 1 = Uncorrectable error encountered during last processing cycle.
bits : 2 - 2 (1 bit)
access : read-only
CORRECTED : 1 = At least one correctable error encountered during last processing cycle.
bits : 3 - 3 (1 bit)
access : read-only
ALLONES : 1 = All data bits of this transaction are ONE.
bits : 4 - 4 (1 bit)
access : read-only
RSVD1 : This field is reserved.
bits : 5 - 7 (3 bit)
access : read-only
STATUS_BLK0 : Count of symbols in error during processing of first block of flash (metadata block)
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
0 : ZERO
No errors found on block.
0x1 : ERROR1
One error found on block.
0x2 : ERROR2
One errors found on block.
0x3 : ERROR3
One errors found on block.
0x4 : ERROR4
One errors found on block.
0xFE : UNCORRECTABLE
Block exhibited uncorrectable errors.
0xFF : ERASED
Page is erased.
End of enumeration elements list.
COMPLETED_CE : This is the chip enable number corresponding to the NAND device from which this data came.
bits : 16 - 19 (4 bit)
access : read-only
HANDLE : Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction
bits : 20 - 31 (12 bit)
access : read-only
Bus Master and ECC Controller Debug Read Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Bus Master and ECC Controller Debug Read Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Bus Master and ECC Controller Debug Read Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Bus Master and ECC Controller Debug Read Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUES : Reserved
bits : 0 - 31 (32 bit)
access : read-only
Block Name Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NAME : The name is in the ASCII characters BCH (0x20, H, C, B).
bits : 0 - 31 (32 bit)
access : read-only
Block Name Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NAME : The name is in the ASCII characters BCH (0x20, H, C, B).
bits : 0 - 31 (32 bit)
access : read-only
Block Name Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NAME : The name is in the ASCII characters BCH (0x20, H, C, B).
bits : 0 - 31 (32 bit)
access : read-only
Block Name Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NAME : The name is in the ASCII characters BCH (0x20, H, C, B).
bits : 0 - 31 (32 bit)
access : read-only
BCH Version Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : Fixed read-only value reflecting the stepping of the RTL version.
bits : 0 - 15 (16 bit)
access : read-only
MINOR : Fixed read-only value indicates the MINOR field of the RTL version.
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Fixed read-only value indicates the MAJOR field of the RTL version.
bits : 24 - 31 (8 bit)
access : read-only
BCH Version Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : Fixed read-only value reflecting the stepping of the RTL version.
bits : 0 - 15 (16 bit)
access : read-only
MINOR : Fixed read-only value indicates the MINOR field of the RTL version.
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Fixed read-only value indicates the MAJOR field of the RTL version.
bits : 24 - 31 (8 bit)
access : read-only
BCH Version Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : Fixed read-only value reflecting the stepping of the RTL version.
bits : 0 - 15 (16 bit)
access : read-only
MINOR : Fixed read-only value indicates the MINOR field of the RTL version.
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Fixed read-only value indicates the MAJOR field of the RTL version.
bits : 24 - 31 (8 bit)
access : read-only
BCH Version Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : Fixed read-only value reflecting the stepping of the RTL version.
bits : 0 - 15 (16 bit)
access : read-only
MINOR : Fixed read-only value indicates the MINOR field of the RTL version.
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Fixed read-only value indicates the MAJOR field of the RTL version.
bits : 24 - 31 (8 bit)
access : read-only
Hardware BCH ECC Debug Register 1
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASED_ZERO_COUNT : The zero counts on one page.
bits : 0 - 8 (9 bit)
access : read-only
RSVD : This field is reserved.
bits : 9 - 30 (22 bit)
access : read-only
DEBUG1_PREERASECHK : Blank page enables pre-erase check.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DEBUG1_PREERASECHK_0
Turn off pre-erase check
0x1 : DEBUG1_PREERASECHK_1
Turn on pre-erase check
End of enumeration elements list.
Hardware BCH ECC Debug Register 1
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASED_ZERO_COUNT : The zero counts on one page.
bits : 0 - 8 (9 bit)
access : read-only
RSVD : This field is reserved.
bits : 9 - 30 (22 bit)
access : read-only
DEBUG1_PREERASECHK : Blank page enables pre-erase check.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DEBUG1_PREERASECHK_0
Turn off pre-erase check
0x1 : DEBUG1_PREERASECHK_1
Turn on pre-erase check
End of enumeration elements list.
Hardware BCH ECC Debug Register 1
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASED_ZERO_COUNT : The zero counts on one page.
bits : 0 - 8 (9 bit)
access : read-only
RSVD : This field is reserved.
bits : 9 - 30 (22 bit)
access : read-only
DEBUG1_PREERASECHK : Blank page enables pre-erase check.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DEBUG1_PREERASECHK_0
Turn off pre-erase check
0x1 : DEBUG1_PREERASECHK_1
Turn on pre-erase check
End of enumeration elements list.
Hardware BCH ECC Debug Register 1
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASED_ZERO_COUNT : The zero counts on one page.
bits : 0 - 8 (9 bit)
access : read-only
RSVD : This field is reserved.
bits : 9 - 30 (22 bit)
access : read-only
DEBUG1_PREERASECHK : Blank page enables pre-erase check.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DEBUG1_PREERASECHK_0
Turn off pre-erase check
0x1 : DEBUG1_PREERASECHK_1
Turn on pre-erase check
End of enumeration elements list.
Hardware ECC Accelerator Status Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : This field is reserved.
bits : 0 - 1 (2 bit)
access : read-only
UNCORRECTABLE : 1 = Uncorrectable error encountered during last processing cycle.
bits : 2 - 2 (1 bit)
access : read-only
CORRECTED : 1 = At least one correctable error encountered during last processing cycle.
bits : 3 - 3 (1 bit)
access : read-only
ALLONES : 1 = All data bits of this transaction are ONE.
bits : 4 - 4 (1 bit)
access : read-only
RSVD1 : This field is reserved.
bits : 5 - 7 (3 bit)
access : read-only
STATUS_BLK0 : Count of symbols in error during processing of first block of flash (metadata block)
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
0 : ZERO
No errors found on block.
0x1 : ERROR1
One error found on block.
0x2 : ERROR2
One errors found on block.
0x3 : ERROR3
One errors found on block.
0x4 : ERROR4
One errors found on block.
0xFE : UNCORRECTABLE
Block exhibited uncorrectable errors.
0xFF : ERASED
Page is erased.
End of enumeration elements list.
COMPLETED_CE : This is the chip enable number corresponding to the NAND device from which this data came.
bits : 16 - 19 (4 bit)
access : read-only
HANDLE : Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction
bits : 20 - 31 (12 bit)
access : read-only
Hardware ECC Accelerator Status Register 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : This field is reserved.
bits : 0 - 1 (2 bit)
access : read-only
UNCORRECTABLE : 1 = Uncorrectable error encountered during last processing cycle.
bits : 2 - 2 (1 bit)
access : read-only
CORRECTED : 1 = At least one correctable error encountered during last processing cycle.
bits : 3 - 3 (1 bit)
access : read-only
ALLONES : 1 = All data bits of this transaction are ONE.
bits : 4 - 4 (1 bit)
access : read-only
RSVD1 : This field is reserved.
bits : 5 - 7 (3 bit)
access : read-only
STATUS_BLK0 : Count of symbols in error during processing of first block of flash (metadata block)
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
0 : ZERO
No errors found on block.
0x1 : ERROR1
One error found on block.
0x2 : ERROR2
One errors found on block.
0x3 : ERROR3
One errors found on block.
0x4 : ERROR4
One errors found on block.
0xFE : UNCORRECTABLE
Block exhibited uncorrectable errors.
0xFF : ERASED
Page is erased.
End of enumeration elements list.
COMPLETED_CE : This is the chip enable number corresponding to the NAND device from which this data came.
bits : 16 - 19 (4 bit)
access : read-only
HANDLE : Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction
bits : 20 - 31 (12 bit)
access : read-only
Hardware ECC Accelerator Mode Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASE_THRESHOLD : This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased
bits : 0 - 7 (8 bit)
access : read-write
RSVD : This field is reserved.
bits : 8 - 31 (24 bit)
access : read-only
Hardware ECC Accelerator Mode Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASE_THRESHOLD : This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased
bits : 0 - 7 (8 bit)
access : read-write
RSVD : This field is reserved.
bits : 8 - 31 (24 bit)
access : read-only
Hardware ECC Accelerator Mode Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASE_THRESHOLD : This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased
bits : 0 - 7 (8 bit)
access : read-write
RSVD : This field is reserved.
bits : 8 - 31 (24 bit)
access : read-only
Hardware ECC Accelerator Mode Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASE_THRESHOLD : This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased
bits : 0 - 7 (8 bit)
access : read-write
RSVD : This field is reserved.
bits : 8 - 31 (24 bit)
access : read-only
Hardware BCH ECC Loopback Encode Buffer Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to encode buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Encode Buffer Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to encode buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Encode Buffer Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to encode buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Encode Buffer Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to encode buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Accelerator Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPLETE_IRQ : This bit indicates the state of the external interrupt line
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : This field is reserved.
bits : 1 - 1 (1 bit)
access : read-only
DEBUG_STALL_IRQ : DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit.
bits : 2 - 2 (1 bit)
access : read-write
BM_ERROR_IRQ : AHB Bus interface Error Interrupt Status
bits : 3 - 3 (1 bit)
access : read-write
RSVD1 : This field is reserved.
bits : 4 - 7 (4 bit)
access : read-only
COMPLETE_IRQ_EN : 1 = interrupt on completion of correction is enabled.
bits : 8 - 8 (1 bit)
access : read-write
RSVD2 : This field is reserved.
bits : 9 - 9 (1 bit)
access : read-only
DEBUG_STALL_IRQ_EN : 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block
bits : 10 - 10 (1 bit)
access : read-write
RSVD3 : This field is reserved.
bits : 11 - 15 (5 bit)
access : read-only
M2M_ENABLE : NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION
bits : 16 - 16 (1 bit)
access : read-write
M2M_ENCODE : Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations.
bits : 17 - 17 (1 bit)
access : read-write
M2M_LAYOUT : Selects the flash page format for memory-to-memory operations.
bits : 18 - 19 (2 bit)
access : read-write
RSVD4 : This field is reserved.
bits : 20 - 21 (2 bit)
access : read-only
DEBUGSYNDROME : (For debug purposes only)
bits : 22 - 22 (1 bit)
access : read-write
RSVD5 : This field is reserved.
bits : 23 - 29 (7 bit)
access : read-only
CLKGATE : This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Allow BCH to operate normally.
0x1 : NO_CLKS
Do not clock BCH gates in order to minimize power consumption.
End of enumeration elements list.
SFTRST : Set this bit to 0 to enable normal BCH operation
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : RUN
Allow BCH to operate normally.
0x1 : RESET
Hold BCH in reset.
End of enumeration elements list.
Hardware BCH ECC Loopback Data Buffer Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to data buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Data Buffer Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to data buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Data Buffer Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to data buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Data Buffer Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to data buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Metadata Buffer Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to metadata buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Metadata Buffer Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to metadata buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Metadata Buffer Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to metadata buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware BCH ECC Loopback Metadata Buffer Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer to metadata buffer
bits : 0 - 31 (32 bit)
access : read-write
Hardware ECC Accelerator Layout Select Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS0_SELECT : Selects which layout is used for chip select 0.
bits : 0 - 1 (2 bit)
access : read-write
CS1_SELECT : Selects which layout is used for chip select 1.
bits : 2 - 3 (2 bit)
access : read-write
CS2_SELECT : Selects which layout is used for chip select 2.
bits : 4 - 5 (2 bit)
access : read-write
CS3_SELECT : Selects which layout is used for chip select 3.
bits : 6 - 7 (2 bit)
access : read-write
CS4_SELECT : Selects which layout is used for chip select 4.
bits : 8 - 9 (2 bit)
access : read-write
CS5_SELECT : Selects which layout is used for chip select 5.
bits : 10 - 11 (2 bit)
access : read-write
CS6_SELECT : Selects which layout is used for chip select 6.
bits : 12 - 13 (2 bit)
access : read-write
CS7_SELECT : Selects which layout is used for chip select 7.
bits : 14 - 15 (2 bit)
access : read-write
CS8_SELECT : Selects which layout is used for chip select 8.
bits : 16 - 17 (2 bit)
access : read-write
CS9_SELECT : Selects which layout is used for chip select 9.
bits : 18 - 19 (2 bit)
access : read-write
CS10_SELECT : Selects which layout is used for chip select 10.
bits : 20 - 21 (2 bit)
access : read-write
CS11_SELECT : Selects which layout is used for chip select 11.
bits : 22 - 23 (2 bit)
access : read-write
CS12_SELECT : Selects which layout is used for chip select 12.
bits : 24 - 25 (2 bit)
access : read-write
CS13_SELECT : Selects which layout is used for chip select 13.
bits : 26 - 27 (2 bit)
access : read-write
CS14_SELECT : Selects which layout is used for chip select 14.
bits : 28 - 29 (2 bit)
access : read-write
CS15_SELECT : Selects which layout is used for chip select 15.
bits : 30 - 31 (2 bit)
access : read-write
Hardware ECC Accelerator Layout Select Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS0_SELECT : Selects which layout is used for chip select 0.
bits : 0 - 1 (2 bit)
access : read-write
CS1_SELECT : Selects which layout is used for chip select 1.
bits : 2 - 3 (2 bit)
access : read-write
CS2_SELECT : Selects which layout is used for chip select 2.
bits : 4 - 5 (2 bit)
access : read-write
CS3_SELECT : Selects which layout is used for chip select 3.
bits : 6 - 7 (2 bit)
access : read-write
CS4_SELECT : Selects which layout is used for chip select 4.
bits : 8 - 9 (2 bit)
access : read-write
CS5_SELECT : Selects which layout is used for chip select 5.
bits : 10 - 11 (2 bit)
access : read-write
CS6_SELECT : Selects which layout is used for chip select 6.
bits : 12 - 13 (2 bit)
access : read-write
CS7_SELECT : Selects which layout is used for chip select 7.
bits : 14 - 15 (2 bit)
access : read-write
CS8_SELECT : Selects which layout is used for chip select 8.
bits : 16 - 17 (2 bit)
access : read-write
CS9_SELECT : Selects which layout is used for chip select 9.
bits : 18 - 19 (2 bit)
access : read-write
CS10_SELECT : Selects which layout is used for chip select 10.
bits : 20 - 21 (2 bit)
access : read-write
CS11_SELECT : Selects which layout is used for chip select 11.
bits : 22 - 23 (2 bit)
access : read-write
CS12_SELECT : Selects which layout is used for chip select 12.
bits : 24 - 25 (2 bit)
access : read-write
CS13_SELECT : Selects which layout is used for chip select 13.
bits : 26 - 27 (2 bit)
access : read-write
CS14_SELECT : Selects which layout is used for chip select 14.
bits : 28 - 29 (2 bit)
access : read-write
CS15_SELECT : Selects which layout is used for chip select 15.
bits : 30 - 31 (2 bit)
access : read-write
Hardware ECC Accelerator Layout Select Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS0_SELECT : Selects which layout is used for chip select 0.
bits : 0 - 1 (2 bit)
access : read-write
CS1_SELECT : Selects which layout is used for chip select 1.
bits : 2 - 3 (2 bit)
access : read-write
CS2_SELECT : Selects which layout is used for chip select 2.
bits : 4 - 5 (2 bit)
access : read-write
CS3_SELECT : Selects which layout is used for chip select 3.
bits : 6 - 7 (2 bit)
access : read-write
CS4_SELECT : Selects which layout is used for chip select 4.
bits : 8 - 9 (2 bit)
access : read-write
CS5_SELECT : Selects which layout is used for chip select 5.
bits : 10 - 11 (2 bit)
access : read-write
CS6_SELECT : Selects which layout is used for chip select 6.
bits : 12 - 13 (2 bit)
access : read-write
CS7_SELECT : Selects which layout is used for chip select 7.
bits : 14 - 15 (2 bit)
access : read-write
CS8_SELECT : Selects which layout is used for chip select 8.
bits : 16 - 17 (2 bit)
access : read-write
CS9_SELECT : Selects which layout is used for chip select 9.
bits : 18 - 19 (2 bit)
access : read-write
CS10_SELECT : Selects which layout is used for chip select 10.
bits : 20 - 21 (2 bit)
access : read-write
CS11_SELECT : Selects which layout is used for chip select 11.
bits : 22 - 23 (2 bit)
access : read-write
CS12_SELECT : Selects which layout is used for chip select 12.
bits : 24 - 25 (2 bit)
access : read-write
CS13_SELECT : Selects which layout is used for chip select 13.
bits : 26 - 27 (2 bit)
access : read-write
CS14_SELECT : Selects which layout is used for chip select 14.
bits : 28 - 29 (2 bit)
access : read-write
CS15_SELECT : Selects which layout is used for chip select 15.
bits : 30 - 31 (2 bit)
access : read-write
Hardware ECC Accelerator Layout Select Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS0_SELECT : Selects which layout is used for chip select 0.
bits : 0 - 1 (2 bit)
access : read-write
CS1_SELECT : Selects which layout is used for chip select 1.
bits : 2 - 3 (2 bit)
access : read-write
CS2_SELECT : Selects which layout is used for chip select 2.
bits : 4 - 5 (2 bit)
access : read-write
CS3_SELECT : Selects which layout is used for chip select 3.
bits : 6 - 7 (2 bit)
access : read-write
CS4_SELECT : Selects which layout is used for chip select 4.
bits : 8 - 9 (2 bit)
access : read-write
CS5_SELECT : Selects which layout is used for chip select 5.
bits : 10 - 11 (2 bit)
access : read-write
CS6_SELECT : Selects which layout is used for chip select 6.
bits : 12 - 13 (2 bit)
access : read-write
CS7_SELECT : Selects which layout is used for chip select 7.
bits : 14 - 15 (2 bit)
access : read-write
CS8_SELECT : Selects which layout is used for chip select 8.
bits : 16 - 17 (2 bit)
access : read-write
CS9_SELECT : Selects which layout is used for chip select 9.
bits : 18 - 19 (2 bit)
access : read-write
CS10_SELECT : Selects which layout is used for chip select 10.
bits : 20 - 21 (2 bit)
access : read-write
CS11_SELECT : Selects which layout is used for chip select 11.
bits : 22 - 23 (2 bit)
access : read-write
CS12_SELECT : Selects which layout is used for chip select 12.
bits : 24 - 25 (2 bit)
access : read-write
CS13_SELECT : Selects which layout is used for chip select 13.
bits : 26 - 27 (2 bit)
access : read-write
CS14_SELECT : Selects which layout is used for chip select 14.
bits : 28 - 29 (2 bit)
access : read-write
CS15_SELECT : Selects which layout is used for chip select 15.
bits : 30 - 31 (2 bit)
access : read-write
Hardware BCH ECC Accelerator Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPLETE_IRQ : This bit indicates the state of the external interrupt line
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : This field is reserved.
bits : 1 - 1 (1 bit)
access : read-only
DEBUG_STALL_IRQ : DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit.
bits : 2 - 2 (1 bit)
access : read-write
BM_ERROR_IRQ : AHB Bus interface Error Interrupt Status
bits : 3 - 3 (1 bit)
access : read-write
RSVD1 : This field is reserved.
bits : 4 - 7 (4 bit)
access : read-only
COMPLETE_IRQ_EN : 1 = interrupt on completion of correction is enabled.
bits : 8 - 8 (1 bit)
access : read-write
RSVD2 : This field is reserved.
bits : 9 - 9 (1 bit)
access : read-only
DEBUG_STALL_IRQ_EN : 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block
bits : 10 - 10 (1 bit)
access : read-write
RSVD3 : This field is reserved.
bits : 11 - 15 (5 bit)
access : read-only
M2M_ENABLE : NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION
bits : 16 - 16 (1 bit)
access : read-write
M2M_ENCODE : Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations.
bits : 17 - 17 (1 bit)
access : read-write
M2M_LAYOUT : Selects the flash page format for memory-to-memory operations.
bits : 18 - 19 (2 bit)
access : read-write
RSVD4 : This field is reserved.
bits : 20 - 21 (2 bit)
access : read-only
DEBUGSYNDROME : (For debug purposes only)
bits : 22 - 22 (1 bit)
access : read-write
RSVD5 : This field is reserved.
bits : 23 - 29 (7 bit)
access : read-only
CLKGATE : This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Allow BCH to operate normally.
0x1 : NO_CLKS
Do not clock BCH gates in order to minimize power consumption.
End of enumeration elements list.
SFTRST : Set this bit to 0 to enable normal BCH operation
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : RUN
Allow BCH to operate normally.
0x1 : RESET
Hold BCH in reset.
End of enumeration elements list.
Hardware BCH ECC Flash 0 Layout 0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 0 Layout 0 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 0 Layout 0 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 0 Layout 0 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 0 Layout 1 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 0 Layout 1 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 0 Layout 1 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 0 Layout 1 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 1 Layout 0 Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 1 Layout 0 Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 1 Layout 0 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 1 Layout 0 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 1 Layout 1 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 1 Layout 1 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 1 Layout 1 Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 1 Layout 1 Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Accelerator Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPLETE_IRQ : This bit indicates the state of the external interrupt line
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : This field is reserved.
bits : 1 - 1 (1 bit)
access : read-only
DEBUG_STALL_IRQ : DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit.
bits : 2 - 2 (1 bit)
access : read-write
BM_ERROR_IRQ : AHB Bus interface Error Interrupt Status
bits : 3 - 3 (1 bit)
access : read-write
RSVD1 : This field is reserved.
bits : 4 - 7 (4 bit)
access : read-only
COMPLETE_IRQ_EN : 1 = interrupt on completion of correction is enabled.
bits : 8 - 8 (1 bit)
access : read-write
RSVD2 : This field is reserved.
bits : 9 - 9 (1 bit)
access : read-only
DEBUG_STALL_IRQ_EN : 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block
bits : 10 - 10 (1 bit)
access : read-write
RSVD3 : This field is reserved.
bits : 11 - 15 (5 bit)
access : read-only
M2M_ENABLE : NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION
bits : 16 - 16 (1 bit)
access : read-write
M2M_ENCODE : Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations.
bits : 17 - 17 (1 bit)
access : read-write
M2M_LAYOUT : Selects the flash page format for memory-to-memory operations.
bits : 18 - 19 (2 bit)
access : read-write
RSVD4 : This field is reserved.
bits : 20 - 21 (2 bit)
access : read-only
DEBUGSYNDROME : (For debug purposes only)
bits : 22 - 22 (1 bit)
access : read-write
RSVD5 : This field is reserved.
bits : 23 - 29 (7 bit)
access : read-only
CLKGATE : This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Allow BCH to operate normally.
0x1 : NO_CLKS
Do not clock BCH gates in order to minimize power consumption.
End of enumeration elements list.
SFTRST : Set this bit to 0 to enable normal BCH operation
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : RUN
Allow BCH to operate normally.
0x1 : RESET
Hold BCH in reset.
End of enumeration elements list.
Hardware BCH ECC Flash 2 Layout 0 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 2 Layout 0 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 2 Layout 0 Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 2 Layout 0 Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 2 Layout 1 Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 2 Layout 1 Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 2 Layout 1 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 2 Layout 1 Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 3 Layout 0 Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 3 Layout 0 Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 3 Layout 0 Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 3 Layout 0 Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0_SIZE : Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECC0 : Indicates the ECC level for the first block on the flash page
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
META_SIZE : Indicates the size of the metadata (in bytes) to be stored on a flash page
bits : 16 - 23 (8 bit)
access : read-write
NBLOCKS : Number of subsequent blocks on the flash page (excluding the data0 block)
bits : 24 - 31 (8 bit)
access : read-write
Hardware BCH ECC Flash 3 Layout 1 Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 3 Layout 1 Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 3 Layout 1 Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
Hardware BCH ECC Flash 3 Layout 1 Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAN_SIZE : Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page
bits : 0 - 9 (10 bit)
access : read-write
GF13_0_GF14_1 : Select GF13 or GF14: 0-GF13; 1-GF14
bits : 10 - 10 (1 bit)
access : read-write
ECCN : Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : NONE
No ECC to be performed
0x1 : ECC2
ECC 2 to be performed
0x2 : ECC4
ECC 4 to be performed
0x1E : ECC60
ECC 60 to be performed
0x1F : ECC62
ECC 62 to be performed
End of enumeration elements list.
PAGE_SIZE : Indicates the total size of the flash page (in bytes)
bits : 16 - 31 (16 bit)
access : read-write
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