ETMCR

ETMSR

ETMSCR

ETMCNTRLDVR1

ETMSYNCFR

ETMIDR

ETMCCER

ETMTESSEICR

ETMTSEVR

ETMEEVR

ETMTRACEIDR

ETMIDR2

ETMTECR1

ETMFFLR

ETMPDSR

ETMCCR

ETMTRIGGER

ITMISCIN

ITTRIGOUT

ITATBCTR2

ITATBCTR0

ETMITCTRL

ETMCLAIMSET

ETMCLAIMCLR

ETMLAR

ETMLSR

ETMAUTHSTATUS

ETMDEVTYPE

ETMPIDR4

ETMPIDR5

ETMPIDR6

ETMPIDR7

ETMPIDR0

ETMPIDR1

ETMPIDR2

ETMPIDR3

ETMCIDR0

ETMCIDR1

ETMCIDR2

ETMCIDR3

ETMPD : ETM power down. This bit can be used by an implementation to control if the ETM is in a low power state. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, writes to some registers and fields might be ignored.
bits : 0 - 0 (1 bit)
access : read-write

PS : Port size. The ETM-M4 has no influence over the external pins used for trace. These bits are implemented but not used. On an ETM reset these bits reset to 0b001.
bits : 4 - 6 (3 bit)
access : read-write

SP : Stall processor. The FIFOFULL output can be used to stall the processor to prevent overflow. The FIFOFULL output is only enabled when the stall processor bit is set to 1. When the bit is 0 the FIFOFULL output remains LOW at all times and the FIFO overflows if there are too many trace packets. Trace resumes without corruption once the FIFO has drained, if overflow does occur. An ETM reset sets this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

BO : Branch output. When set to 1 all branch addresses are output, even if the branch was because of a direct branch instruction. Setting this bit enables reconstruction of the program flow without having access to the memory image of the code being executed. When this bit is set to 1, more trace data is generated, and this may affect the performance of the trace system. Information about the execution of a branch is traced regardless of the state of this bit. An ETM reset sets this bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

DRC : Debug request control. When set to 1 and the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the ARM processor to be forced into Debug state. An ETM reset sets this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

ETMP : ETM programming. This bit must be set to 1 at the start of the ETM programming sequence. Tracing is prevented while this bit is set to 1.On an ETM reset this bit is set to b1.
bits : 10 - 10 (1 bit)
access : read-write

ETMPS : ETM port selection. This bit can be used to control other trace components in an implementation.This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM.An ETM reset sets this bit to 0.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PM2 : This bit is implemented but has no function.An ETM reset sets this bit to 0.
bits : 13 - 13 (1 bit)
access : read-write

PM : These bits are implemented but have no function.An ETM reset sets these bits to 0.
bits : 16 - 17 (2 bit)
access : read-write

PS3 : This bit is implemented but has no function.An ETM reset sets this bit to 0.
bits : 21 - 21 (1 bit)
access : read-write

TE : When set, this bit enables timestamping. An ETM reset sets this bit to 0.
bits : 28 - 28 (1 bit)
access : read-write

UOF : Untraced overflow flag. If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either:- trace is restarted- the ETM Power Down bit, bit [0] of the ETM Control Register, 0x00, is set to 1.Note: Setting or clearing the ETM programming bit does not cause this bit to be cleared to 0.
bits : 0 - 0 (1 bit)
access : read-only

Progbit : ETM programming bit value (Progbit). The current effective value of the ETM Programming bit (ETM Control Register bit [10]). Tou must wait for this bit to go to 1 before you start to program the ETM.
bits : 1 - 1 (1 bit)
access : read-only

Status : Holds the current status of the trace start/stop resource. If set to 1, it indicates that a trace on address has been matched, without a corresponding trace off address match.
bits : 2 - 2 (1 bit)
access : read-write

Trigger : Trigger bit. Set when the trigger occurs, and prevents the trigger from being output until the ETM is next programmed.
bits : 3 - 3 (1 bit)
access : read-write

MaximumPortSize : Maximum ETM port size bits [2:0]. These bits are used in conjunction with bit [9]. The value of these bits is b001.
bits : 0 - 2 (3 bit)
access : read-only

FIFOFULLsupported : FIFOFULL supported. The value of this bit is 1, indicating that FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETMCCR.
bits : 8 - 8 (1 bit)
access : read-only

MaximumPortSize3 : Maximum ETM port size bit [3]. This bit is used in conjunction with bits [2:0]. Its value is 0.This has no effect on the TPIU trace port.
bits : 9 - 9 (1 bit)
access : read-only

PortSizeSupported : Port size supported. This bit reads as 1 if the currently selected port size is supported. This has no effect on the TPIU trace port.
bits : 10 - 10 (1 bit)
access : read-only

PortModeSupported : Port mode supported. This bit reads as 1 if the currently selected port mode is supported. This has no effect on the TPIU trace port.
bits : 11 - 11 (1 bit)
access : read-only

N : These bits give the number of supported processors minus 1. The value of these bits is b000, indicating that there is only one processor connected.
bits : 12 - 14 (3 bit)
access : read-only

NoFetchComparisons : No Fetch comparisons. The value of this bit is 1, indicating that fetch comparisons are not implemented.
bits : 17 - 17 (1 bit)
access : read-only

IntitialCount : Initial count.
bits : 0 - 15 (16 bit)
access : read-write

SyncFrequency : Synchronization frequency. Default value is 1024.
bits : 0 - 11 (12 bit)
access : read-only

ImplementationRevision : Implementation revision. The value of these bits is b0000, indicating implementation revision, 0.
bits : 0 - 3 (4 bit)
access : read-only

MinorETMarchitectureVersion : Minor ETM architecture version. The value of these bits is 0b0101, indicating minor architecture version number 5.
bits : 4 - 7 (4 bit)
access : read-only

MajorETMarchitectureVersion : Major ETM architecture version. The value of these bits is 0b0010, indicating major architecture version number 3, ETMv3.
bits : 8 - 11 (4 bit)
access : read-only

ProcessorFamily : Processor family. The value of these bits is 0b1111, indicating that the processor family is not identified in this register.
bits : 12 - 15 (4 bit)
access : read-only

LoadPCfirst : Load PC first. The value of this bit is 0, indicating that data tracing is not supported.
bits : 16 - 16 (1 bit)
access : read-only

ThumbInstructionTracing : 32-bit Thumb instruction tracing. The value of this bit is 1, indicating that a 32-bit Thumb instruction is traced as a single instruction.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SecurityExtensionSupport : Security Extensions support. The value of this bit is 0, indicating that the ETM behaves as if the processor is in Secure state at all times.
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BranchPacketEncoding : Branch packet encoding. The value of this bit is 1, indicating that alternative branch packet encoding is implemented.
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ImplementorCode : Implementor code. These bits identify ARM as the implementor of the processor. The value of these bits is 01000001.
bits : 24 - 31 (8 bit)
access : read-only

ExtendedExternalInputSelectors : Extended external input selectors. The value of these bits is 0, indicating that extended external input selectors are not implemented.
bits : 0 - 2 (3 bit)
access : read-only

ExtendedExternalInputBus : Extended external input bus. The value of these bits is 0, indicating that the extended external input bus is not implemented.
bits : 3 - 10 (8 bit)
access : read-only

ReadableRegisters : Readable registers. The value of this bit is 1, indicating that all registers are readable.
bits : 11 - 11 (1 bit)
access : read-only

DataAddressComparisons : Data address comparisons. The value of this bit is 1, indicating that data address comparisons are not supported.
bits : 12 - 12 (1 bit)
access : read-only

InstrumentationResources : Instrumentation resources. The value of these bits is 0b000, indicating that no Instrumentation resources are supported.
bits : 13 - 15 (3 bit)
access : read-only

EmbeddedICEwatchpointInputs : EmbeddedICE watchpoint inputs. The value of these bits is 0b0100, indicating that the number of EmbeddedICE watchpoint inputs implemented is four. These inputs come from the DWT.
bits : 16 - 19 (4 bit)
access : read-only

TraceStartStopBlockUsesEmbeddedICEwatchpointInputs : Trace Start/Stop block uses EmbeddedICE watchpoint inputs. The value of this bit is 1, indicating that the Trace Start/Stop block uses the EmbeddedICE watchpoint inputs.
bits : 20 - 20 (1 bit)
access : read-only

EmbeddedICEbehaviorControlImplemented : EmbeddedICE behavior control implemented. The value of this bit is 0, indicating that the ETMEIBCR is not implemented.
bits : 21 - 21 (1 bit)
access : read-only

TimestampingImplemented : Timestamping implemented. This bit is set to 1, indicating that timestamping is implemented.
bits : 22 - 22 (1 bit)
access : read-only

ReducedFunctionCounter : Reduced function counter. Set to 1 to indicate that Counter 1 is a reduced function counter.
bits : 27 - 27 (1 bit)
access : read-only

TimestampEncoding : Timestamp encoding. Set to 1 to indicate that the timestamp is encoded as a natural binary number.
bits : 28 - 28 (1 bit)
access : read-only

TimestampSize : Timestamp size. Set to 0 to indicate a size of 48 bits.
bits : 29 - 29 (1 bit)
access : read-only

StartResourceSelection : Start resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] corresponds to input 2, bit [2] corresponds to input 3, and bit [3] corresponds to input 4.
bits : 0 - 3 (4 bit)
access : read-write

StopResourceSelection : Stop resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] corresponds to input 2, bit [18] corresponds to input 3, and bit [19] corresponds to input 4.
bits : 16 - 19 (4 bit)
access : read-write

TimestampEvent : Timestamp event.
bits : 0 - 11 (12 bit)
access : read-write

TraceEnableEvent : Trace Enable event.
bits : 0 - 16 (17 bit)
access : read-write

TraceID : Trace ID to output onto the trace bus.On an ETM reset this field is cleared to 0x00.
bits : 0 - 6 (7 bit)
access : read-write

TraceControlEnable : Trace start/stop enable.The trace start/stop resource, resource 0x5F, is unaffected by the value of this bit.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFOFullLevel : FIFO full level. The number of bytes left in FIFO, below which the FIFOFULL or SupressData signal is asserted. For example, setting this value to 15 causes data trace suppression or processor stalling, if enabled, when there are less than 15 free bytes in the FIFO.
bits : 0 - 7 (8 bit)
access : read-write

ETMpoweredup : The value of this bit indicates whether you can access the ETM Trace Registers. The value of this bit is always 1, indicating that the ETM Trace Registers can be accessed.
bits : 0 - 0 (1 bit)
access : read-only

NumberOfAddressComparatorPairs : Number of address comparator pairs. The value of these bits is b0000, indicating that address comparator pairs are not implemented.
bits : 0 - 3 (4 bit)
access : read-only

NDVC : Number of data value comparators. The value of these bits is b0000, indicating that data value comparators are not implemented.
bits : 4 - 7 (4 bit)
access : read-only

NMMD : Number of memory map decoders. The value of these bits is b00000, indicating that memory map decoder inputs are not implemented.
bits : 8 - 12 (5 bit)
access : read-only

NC : Number of counters. The value of these bits is b001, indicating that one counter is implemented.
bits : 13 - 15 (3 bit)
access : read-only

SP : Sequencer present. The value of this bit is 0, indicating that the sequencer is not implemented.
bits : 16 - 16 (1 bit)
access : read-only

NEI : Number of external inputs. The value of these bits is between b000 and b010, indicating the number of external inputs, from 0 to 2, implemented in the system.
bits : 17 - 19 (3 bit)
access : read-only

NEO : Number of external outputs. The value of these bits is b000, indicating that no external outputs are supported.
bits : 20 - 22 (3 bit)
access : read-only

FFLP : FIFOFULL logic present. The value of this bit is 1, indicating that FIFOFULL logic is present in the ETM. To use FIFOFULL the system must also support the function, as indicated by bit [8] of ETMSCR.
bits : 23 - 23 (1 bit)
access : read-only

NCIDC : Number of Context ID comparators. The value of these bits is b00, indicating that Context ID comparators are notimplemented.
bits : 24 - 25 (2 bit)
access : read-only

TSSBP : Trace start/stop block present. The value of this bit is 1, indicating that the Trace start/stop block is present.
bits : 26 - 26 (1 bit)
access : read-only

CMA : Coprocessor and memory access. The value of this bit is 1, indicating that memory-mapped access to registers is supported.
bits : 27 - 27 (1 bit)
access : read-only

ETMIDRP : The value of this bit is 1, indicating that the ETMIDR, register 0x79, is present and defines the ETM architecture version in use.
bits : 31 - 31 (1 bit)
access : read-only

TriggerEvent : Trigger event
bits : 0 - 16 (17 bit)
access : read-write

EXTIN : A read of these bits returns the value of the EXTIN[1:0] input pins.
bits : 0 - 1 (2 bit)
access : read-only

COREHALT : A read of this bit returns the value of the COREHALT input pin.
bits : 4 - 4 (1 bit)
access : read-only

TRIGGER : A write to this bit sets the TRIGGER output.
bits : 0 - 0 (1 bit)
access : write-only

ATREADY : A read of this bit returns the value of the ETM ATREADY input.
bits : 0 - 0 (1 bit)
access : read-only

ATVALID : A write to this bit sets the value of the ETM ATVALID output.
bits : 0 - 0 (1 bit)
access : write-only

Mode : Enable integration mode. When this bit is set to 1, the device enters integration mode to enable Topology Detection or Integration Testing to be checked. On an ETM reset this bit is cleared to 0.
bits : 0 - 0 (1 bit)
access : read-write

CLAIMSET : A bit programmable register bank which sets the Claim Tag Value.Write 1 to set the bit in the claim tag. A read will return a logic 1 for all implemented locations.
bits : 0 - 3 (4 bit)
access : read-write

CLAIMCLR : A bit programmable register bank that is zero at reset.Write 1 to clear the bit in the claim tag. On reads, returns the current setting of the claim tag.
bits : 0 - 3 (4 bit)
access : read-write

WriteAccessCode : Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access.
bits : 0 - 31 (32 bit)
access : read-write

IMP : Lock mechanism is implemented. This bit always reads 1.
bits : 0 - 0 (1 bit)
access : read-only

STATUS : Lock Status. This bit is HIGH when the device is locked, and LOW when unlocked.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

s8BIT : Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present.
bits : 2 - 2 (1 bit)
access : read-only

NSID : Reads as b00, Non-secure invasive debug not supported by the ETM.
bits : 0 - 1 (2 bit)
access : read-only

NSNID : Permission for Non-secure non-invasive debug.
bits : 2 - 3 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SID : Reads as b00, Secure invasive debug not supported by the ETM.
bits : 4 - 5 (2 bit)
access : read-only

SNID : Permission for Secure non-invasive debug.
bits : 6 - 7 (2 bit)
access : read-only

MajorType : Major Type and Class
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SubType : Sub Type
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

JEP106 : JEP106 continuation code.
bits : 0 - 3 (4 bit)
access : read-only

c4KB : 4KB Count
bits : 4 - 7 (4 bit)
access : read-only

PartNumber : Part Number [7:0]
bits : 0 - 7 (8 bit)
access : read-only

PartNumber : Part Number [11:8]
bits : 0 - 3 (4 bit)
access : read-only

JEP106_identity_code : JEP106 identity code [3:0]
bits : 4 - 7 (4 bit)
access : read-only

JEP106_identity_code : JEP106 identity code [6:4]
bits : 0 - 2 (3 bit)
access : read-only

Revision : Revision
bits : 4 - 7 (4 bit)
access : read-only

CustomerModified : Customer Modified.
bits : 0 - 3 (4 bit)
access : read-only

RevAnd : RevAnd
bits : 4 - 7 (4 bit)
access : read-only

Preamble : Preamble
bits : 0 - 7 (8 bit)
access : read-only

Preamble : Preamble
bits : 0 - 3 (4 bit)
access : read-only

ComponentClass : Component class
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

Preamble : Preamble
bits : 0 - 7 (8 bit)
access : read-only

Preamble : Preamble
bits : 0 - 7 (8 bit)
access : read-only