Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC0 byte (0x0)
mem_usage : registers
protection : not protected
GPR0 General Purpose Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_MUX_SEL0 : Selects between two possible sources for SDMA_EVENT18
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DMAREQ_MUX_SEL0_0
I2C1 DMA event
0x1 : DMAREQ_MUX_SEL0_1
SIM1 receive DMA request
End of enumeration elements list.
DMAREQ_MUX_SEL1 : Selects between two possible sources for SDMA_EVENT19
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DMAREQ_MUX_SEL1_0
I2C2 DMA event
0x1 : DMAREQ_MUX_SEL1_1
SIM1 transmit DMA request
End of enumeration elements list.
DMAREQ_MUX_SEL2 : Selects between two possible sources for SDMA_EVENT20
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DMAREQ_MUX_SEL2_0
I2C3 DMA event
0x1 : DMAREQ_MUX_SEL2_1
SIM1 receive DMA request
End of enumeration elements list.
DMAREQ_MUX_SEL3 : Selects between two possible sources for SDMA_EVENT21
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DMAREQ_MUX_SEL3_0
I2C4 DMA event
0x1 : DMAREQ_MUX_SEL3_1
SIM2 transmit DMA request
End of enumeration elements list.
DMAREQ_MUX_SEL4 : Selects between two possible sources for SDMA_EVENT47
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DMAREQ_MUX_SEL4_0
ENET1 1588 Event1 out
0x1 : DMAREQ_MUX_SEL4_1
ENET2 1588 Event1 out
End of enumeration elements list.
DMAREQ_MUX_SEL5 : Selects between two possible sources for SDMA_EVENT40
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DMAREQ_MUX_SEL5_0
GPT3 counter event
0x1 : DMAREQ_MUX_SEL5_1
FTM1 7 channel DMA request
End of enumeration elements list.
DMAREQ_MUX_SEL6 : Selects between two possible sources for SDMA_EVENT41
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DMAREQ_MUX_SEL6_0
GPT4 counter event
0x1 : DMAREQ_MUX_SEL6_1
FTM2 8 channel DMA request
End of enumeration elements list.
GPR4 General Purpose Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMA1_IPG_STOP : SDMA1 stop request
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SDMA1_IPG_STOP_0
stop request off
0x1 : SDMA1_IPG_STOP_1
stop request on
End of enumeration elements list.
ENET1_IPD_REQ_TIMER_SEL0 : ENET1 IPD_REQ Timer Select 0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ENET1_IPD_REQ_TIMER_SEL0_0
Select ipd_req_mac0_timer2 to SDMA IRQ 45
0x1 : ENET1_IPD_REQ_TIMER_SEL0_1
Select ipd_req_mac0_timer0 to SDMA IRQ 45
End of enumeration elements list.
ENET1_IPD_REQ_TIMER_SEL1 : ENET1 IPD_REQ Timer Select 1
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ENET1_IPD_REQ_TIMER_SEL1_0
Select ipd_req_mac0_timer3 to SDMA IRQ 47
0x1 : ENET1_IPD_REQ_TIMER_SEL1_1
Select ipd_req_mac0_timer1 to SDMA IRQ 47
End of enumeration elements list.
ENET1_IPG_STOP : ENET1 stop request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ENET1_IPG_STOP_0
stop request off
0x1 : ENET1_IPG_STOP_1
stop request on
End of enumeration elements list.
SDMA2_IPG_STOP : SDMA2 stop request
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SDMA2_IPG_STOP_0
stop request off
0x1 : SDMA2_IPG_STOP_1
stop request on
End of enumeration elements list.
SDMA1_IPG_STOP_ACK : SDMA1 stop acknowledge
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : SDMA1_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : SDMA1_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
ENET1_IPG_STOP_ACK : ENET1 stop acknowledge
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : ENET1_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : ENET1_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
SDMA2_IPG_STOP_ACK : SDMA2 stop acknowledge
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : SDMA2_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : SDMA2_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
SAI1_IPG_STOP_ACK : SAI1 stop acknowledge
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : SAI1_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : SAI1_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
SAI2_IPG_STOP_ACK : SAI2 stop acknowledge
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : SAI2_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : SAI2_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
SAI3_IPG_STOP_ACK : SAI3 stop acknowledge
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : SAI3_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : SAI3_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
SAI4_IPG_STOP_ACK : SAI4 stop acknowledge
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : SAI4_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : SAI4_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
SAI5_IPG_STOP_ACK : SAI5 stop acknowledge
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : SAI5_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : SAI5_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
SAI6_IPG_STOP_ACK : SAI6 stop acknowledge
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : SAI6_IPG_STOP_ACK_0
stop acknowledge is not asserted
0x1 : SAI6_IPG_STOP_ACK_1
stop acknowledge is asserted, peripheral is in STOP mode
End of enumeration elements list.
GPR5 General Purpose Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HDMI_HPD_PD : Connect to hdmi_hpd_pd_pad
bits : 0 - 0 (1 bit)
access : read-write
HDMI_DDC_SDA_PD : Connect to hdmi_ddc_sda_pd_pad
bits : 1 - 1 (1 bit)
access : read-write
HDMI_DDC_SCL_PD : Connect to hdmi_ddc_scl_pd_pad
bits : 2 - 2 (1 bit)
access : read-write
HDMI_CEC_PD : Connect to hdmi_cec_pd_pad
bits : 3 - 3 (1 bit)
access : read-write
WDOG1_MASK : WDOG1 Timeout Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : WDOG1_MASK_0
WDOG1 Timeout behaves normally
0x1 : WDOG1_MASK_1
WDOG1 Timeout is masked
End of enumeration elements list.
WDOG2_MASK : WDOG2 Timeout Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : WDOG2_MASK_0
WDOG2 Timeout behaves normally
0x1 : WDOG2_MASK_1
WDOG2 Timeout is masked
End of enumeration elements list.
WDOG3_MASK : WDOG3 Timeout Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : WDOG3_MASK_0
WDOG3 Timeout behaves normally
0x1 : WDOG3_MASK_1
WDOG3 Timeout is masked
End of enumeration elements list.
GPR6 General Purpose Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR7 General Purpose Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR8 General Purpose Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR9 General Purpose Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR10 General Purpose Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TZASC_EN : Connect to tzasc_en input on tzasc_id_wrap
bits : 0 - 0 (1 bit)
access : read-write
TZASC_ID_SWAP_BYPASS : Connect to id_swap_bypass input on tzasc_id_wrap
bits : 1 - 1 (1 bit)
access : read-write
SEC_ERR_RESP_EN : Security error response enable for all security gaskets (on both AHB and AXI busses) This is a "lock" type bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SEC_ERR_RESP_EN_0
OKAY response
0x1 : SEC_ERR_RESP_EN_1
SLVERR response
End of enumeration elements list.
EXC_ERR_RESP_EN : Security exclusive access error response enable for all security gaskets (on both AHB and AXI busses)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : EXC_ERR_RESP_EN_0
OK response on the AXI for an exclusive access error
0x1 : EXC_ERR_RESP_EN_1
ERR response on the AXI for an exclusive access error
End of enumeration elements list.
TZASC_EN_LOCK : Lock bit for TZASC_EN
bits : 16 - 16 (1 bit)
access : read-write
TZASC_ID_SWAP_BYPASS_LOCK : Lock bit for TZASC_ID_SWAP_BYPASS
bits : 17 - 17 (1 bit)
access : read-write
SEC_ERR_RESP_EN_LOCK : Lock bit for SEC_ERR_RESP_EN
bits : 18 - 18 (1 bit)
access : read-write
EXC_ERR_RESP_EN_LOCK : Lock bit for EXC_ERR_RESP_EN
bits : 19 - 19 (1 bit)
access : read-write
GPR11 General Purpose Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCRAM_TZ_EN : OCRAM TrustZone (TZ) enable This is a "lock" type bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : OCRAM_TZ_EN_0
The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor).
0x1 : OCRAM_TZ_EN_1
The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.
End of enumeration elements list.
OCRAM_TZ_ADDR : OCRAM TrustZone (TZ) start address
bits : 1 - 5 (5 bit)
access : read-write
OCRAM_S_TZ_EN : State Retention OCRAM TrustZone (TZ) enable This is a "lock" type bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : OCRAM_S_TZ_EN_0
The TrustZone feature is disabled. Entire State Retention OCRAM space is available for all access types (secure/non-secure/user/supervisor).
0x1 : OCRAM_S_TZ_EN_1
The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.
End of enumeration elements list.
OCRAM_S_TZ_ADDR : State Retention OCRAM TrustZone (TZ) start address
bits : 11 - 13 (3 bit)
access : read-write
OCRAM_TZ_EN_LOCK : Lock Bit
bits : 16 - 16 (1 bit)
access : read-write
OCRAM_TZ_ADDR_LOCK : Lock Bits
bits : 17 - 21 (5 bit)
access : read-write
OCRAM_S_TZ_EN_LOCK : Lock Bit
bits : 26 - 26 (1 bit)
access : read-write
OCRAM_S_TZ_ADDR_LOCK : Lock Bits
bits : 27 - 29 (3 bit)
access : read-write
GPR12 General Purpose Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCIE2_CTRL_DEVICE_TYPE : PCI Express device/port type
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : PCIE2_CTRL_DEVICE_TYPE_0
PCI Express endpoint
0x1 : PCIE2_CTRL_DEVICE_TYPE_1
Legacy PCI Express endpoint
0x4 : PCIE2_CTRL_DEVICE_TYPE_4
Root port of PCI Express root complex
End of enumeration elements list.
PCIE1_CTRL_DEVICE_TYPE : PCI Express device/port type
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : PCIE1_CTRL_DEVICE_TYPE_0
PCI Express endpoint
0x1 : PCIE1_CTRL_DEVICE_TYPE_1
Legacy PCI Express endpoint
0x4 : PCIE1_CTRL_DEVICE_TYPE_4
Root port of PCI Express root complex
End of enumeration elements list.
PCIE1_CTRL_DIAG_STATUS_BUS_SELECT : PCI Express Diagnostic Status Bus Select
bits : 17 - 20 (4 bit)
access : read-write
PCIE1_CTRL_DIAG_CTRL_BUS : PCI Express Diagnostic Control Bus
bits : 21 - 22 (2 bit)
access : read-write
PCIE2_CTRL_DIAG_STATUS_BUS_SELECT : PCI Express Diagnostic Status Bus Select
bits : 25 - 28 (4 bit)
access : read-write
PCIE2_CTRL_DIAG_CTRL_BUS : PCI Express Diagnostic Control Bus
bits : 29 - 30 (2 bit)
access : read-write
PCIE_DIAG_BUS_SEL : Control the source of the PCIE DIAG STATUS bus, PCIe1 or PCIe2.
bits : 31 - 31 (1 bit)
access : read-write
GPR13 General Purpose Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCACHE_USDHC : USDHC 1-3 AXI Master ARCACHE Override Value Note: this bit always overrides
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ARCACHE_USDHC_0
Drive USDHC AXI Master ARCACHE[1] to 0
0x1 : ARCACHE_USDHC_1
Drive USDHC AXI Master ARCACHE[1] to 1
End of enumeration elements list.
AWCACHE_USDHC : USDHC 1-3 AXI Master AWCACHE Override Value Note: this bit always overrides
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : AWCACHE_USDHC_0
Drive USDHC AXI Master AWCACHE[1] to 0
0x1 : AWCACHE_USDHC_1
Drive USDHC AXI Master AWCACHE[1] to 1
End of enumeration elements list.
MIPI_MUX_SEL : MIPI MUX SEL
bits : 2 - 2 (1 bit)
access : read-write
MIPI_MUX_INV : MIPI MUX INV
bits : 3 - 3 (1 bit)
access : read-write
ARCACHE_PCIE1 : PCIe AXI Master Port ARCACHE Override Value Note: this bit only takes effect when ARCACHE_PCIE_EN = 1
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ARCACHE_PCIE1_0
Drive PCIe AXI Master Port ARCACHE[1] to 0
0x1 : ARCACHE_PCIE1_1
Drive PCIe AXI Master Port ARCACHE[1] to 1
End of enumeration elements list.
AWCACHE_PCIE1 : PCIe AXI Master Port AWCACHE Override Value Note: this bit only takes effect when AWCACHE_PCIE_EN = 1
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : AWCACHE_PCIE1_0
Drive PCIe AXI Master Port AWCACHE[1] to 0
0x1 : AWCACHE_PCIE1_1
Drive PCIe AXI Master Port AWCACHE[1] to 1
End of enumeration elements list.
ARCACHE_LCDIF : LCDIF AXI Master Port ARCACHE Override Value Note: this bit only takes effect when ARCACHE_LCDIF_EN = 1
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : ARCACHE_LCDIF_0
Drive LCDIF AXI Master Port ARCACHE[1] to 0
0x1 : ARCACHE_LCDIF_1
Drive LCDIF AXI Master Port ARCACHE[1] to 1
End of enumeration elements list.
ARCACHE_PCIE2_EN : PCIe AXI Master Port ARCACHE Override Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : ARCACHE_PCIE2_EN_0
PCIE Primary AXI Master Port ARCACHE[1] driven by PCIE
0x1 : ARCACHE_PCIE2_EN_1
PCIE Primary AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PCIE2 bit
End of enumeration elements list.
AWCACHE_PCIE2_EN : PCIe AXI Master Port AWCACHE Override Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : AWCACHE_PCIE2_EN_0
PCIE Primary AXI Master Port AWCACHE[1] driven by PCIE
0x1 : AWCACHE_PCIE2_EN_1
PXP Primary AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE2 bit
End of enumeration elements list.
ARCACHE_PCIE1_EN : PCIe AXI Master Port ARCACHE Override Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : ARCACHE_PCIE1_EN_0
PCIe AXI Master Port ARCACHE[1] driven by PCIe
0x1 : ARCACHE_PCIE1_EN_1
PCIe AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PXP1 bit
End of enumeration elements list.
AWCACHE_PCIE1_EN : PCIe AXI Master Port AWCACHE Override Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : AWCACHE_PCIE1_EN_0
PCIe AXI Master Port AWCACHE[1] driven by PCIe
0x1 : AWCACHE_PCIE1_EN_1
PCIe AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE1 bit
End of enumeration elements list.
ARCACHE_LCDIF_EN : LCDIF AXI Master Port ARCACHE Override Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : ARCACHE_LCDIF_EN_0
LCDIF AXI Master Port ARCACHE[1] driven by LCDIF
0x1 : ARCACHE_LCDIF_EN_1
LCDIF AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_LCDIF bit
End of enumeration elements list.
ARCACHE_PCIE2 : PCIe AXI Master Port ARCACHE Override Value Note: this bit only takes effect when ARCACHE_PCIE_EN = 1
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : ARCACHE_PCIE2_0
Drive PCIe AXI Master Port ARCACHE[1] to 0
0x1 : ARCACHE_PCIE2_1
Drive PCIe AXI Master Port ARCACHE[1] to 1
End of enumeration elements list.
AWCACHE_PCIE2 : PCIe AXI Master Port AWCACHE Override Value Note: this bit only takes effect when AWCACHE_PCIE_EN = 1
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AWCACHE_PCIE2_0
Drive PCIe AXI Master Port AWCACHE[1] to 0
0x1 : AWCACHE_PCIE2_1
Drive PCIe AXI Master Port AWCACHE[1] to 1
End of enumeration elements list.
GPR14 General Purpose Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCIE1_APP_CLK_PM_EN : To PCIe PHY
bits : 8 - 8 (1 bit)
access : read-write
PCIE1_REF_USE_PAD : To PCIe PHY
bits : 9 - 9 (1 bit)
access : read-write
PCIE1_CLKREQ_B_OVERRIDE_EN : Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller
bits : 10 - 10 (1 bit)
access : read-write
PCIE1_CLKREQ_B_OVERRIDE : Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller
bits : 11 - 11 (1 bit)
access : read-write
PCIE1_VREG_BYPASS : To PCIe PHY
bits : 12 - 12 (1 bit)
access : read-write
PCIE1_PHY_TX_VBOOST_LVL : To PCIe PHY
bits : 13 - 15 (3 bit)
access : read-write
PCIE1_PHY_TX0_TERM_OFFSET : To PCIe PHY
bits : 16 - 20 (5 bit)
access : read-write
PCIE1_PHY_RX0_EQ : To PCIe PHY
bits : 21 - 23 (3 bit)
access : read-write
PCIE1_PHY_LOS_LEVEL : To PCIe PHY
bits : 24 - 28 (5 bit)
access : read-write
PCIE1_PHY_LOS_BIAS : To PCIe PHY
bits : 29 - 31 (3 bit)
access : read-write
GPR15 General Purpose Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCIE1_PCS_TX_SWING_LOW : To PCIe PHY
bits : 0 - 6 (7 bit)
access : read-write
PCIE1_PCS_TX_SWING_FULL : To PCIe PHY
bits : 7 - 13 (7 bit)
access : read-write
PCIE1_PCS_TX_DEEMPH_GEN2_6DB : To PCIe PHY
bits : 14 - 19 (6 bit)
access : read-write
PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB : To PCIe PHY
bits : 20 - 25 (6 bit)
access : read-write
PCIE1_PCS_TX_DEEMPH_GEN1 : To PCIe PHY
bits : 26 - 31 (6 bit)
access : read-write
GPR1 General Purpose Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ : Interrupt signal which is connected to CPU IRQS[0]
bits : 12 - 12 (1 bit)
access : read-write
ENET1_TX_CLK_SEL : ENET1 reference clock mode select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : ENET1_TX_CLK_SEL_0
Gets ENET1 TX reference clk. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function.
0x1 : ENET1_TX_CLK_SEL_1
Gets ENET1 TX reference clk from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller
End of enumeration elements list.
ENET1_CLK_DIR : ENET1_TX_CLK data direction control when ANATOP ENET_REF_CLK1 is selected
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : ENET1_CLK_DIR_0
ENET1_TX_CLK output driver is disabled when configured for ALT1
0x1 : ENET1_CLK_DIR_1
ENET1_TX_CLK output driver is enabled when configured for ALT1
End of enumeration elements list.
TZASC1_SECURE_BOOT_LOCK : TZASC-1 Secure Boot Lock
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TZASC1_SECURE_BOOT_LOCK_0
Secure boot lock is disabled
0x1 : TZASC1_SECURE_BOOT_LOCK_1
Secure boot lock is enabled
End of enumeration elements list.
DBG_ACK : Debug Acknowledge
bits : 28 - 31 (4 bit)
access : read-write
GPR16 General Purpose Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCIE2_APP_CLK_PM_EN : To PCIe PHY
bits : 8 - 8 (1 bit)
access : read-write
PCIE2_REF_USE_PAD : To PCIe PHY
bits : 9 - 9 (1 bit)
access : read-write
PCIE2_CLKREQ_B_OVERRIDE_EN : Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller
bits : 10 - 10 (1 bit)
access : read-write
PCIE2_CLKREQ_B_OVERRIDE : Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller
bits : 11 - 11 (1 bit)
access : read-write
PCIE2_VREG_BYPASS : To PCIe PHY
bits : 12 - 12 (1 bit)
access : read-write
PCIE2_PHY_TX_VBOOST_LVL : To PCIe PHY
bits : 13 - 15 (3 bit)
access : read-write
PCIE2_PHY_TX0_TERM_OFFSET : To PCIe PHY
bits : 16 - 20 (5 bit)
access : read-write
PCIE2_PHY_RX0_EQ : To PCIe PHY
bits : 21 - 23 (3 bit)
access : read-write
PCIE2_PHY_LOS_LEVEL : To PCIe PHY
bits : 24 - 28 (5 bit)
access : read-write
PCIE2_PHY_LOS_BIAS : To PCIe PHY
bits : 29 - 31 (3 bit)
access : read-write
GPR17 General Purpose Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCIE2_PCS_TX_SWING_LOW : To PCIe PHY
bits : 0 - 6 (7 bit)
access : read-write
PCIE2_PCS_TX_SWING_FULL : To PCIe PHY
bits : 7 - 13 (7 bit)
access : read-write
PCIE2_PCS_TX_DEEMPH_GEN2_6DB : To PCIe PHY
bits : 14 - 19 (6 bit)
access : read-write
PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB : To PCIe PHY
bits : 20 - 25 (6 bit)
access : read-write
PCIE2_PCS_TX_DEEMPH_GEN1 : To PCIe PHY
bits : 26 - 31 (6 bit)
access : read-write
GPR18 General Purpose Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR19 General Purpose Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCIE_DIAG_STATUS : PCIe DIAG Status Bus
bits : 0 - 31 (32 bit)
access : read-only
GPR20 General Purpose Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR21 General Purpose Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR22 General Purpose Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_STANDBYWFI : Status of CPU STANDBYWFI low power states MSB: status of core 3 STANDBYWFI low power state LSB: status of core 0 STANDBYWFI low power state
bits : 16 - 19 (4 bit)
access : read-only
CPU_STANDBYWFE : Status of CPU STANDBYWFE low power states MSB: status of core 3 STANDBYWFE low power state LSB: status of core 0 STANDBYWFE low power state
bits : 20 - 23 (4 bit)
access : read-only
GPR23 General Purpose Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_RX_RCAL : For DSI Control
bits : 0 - 1 (2 bit)
access : read-write
DSI_RTERM_SEL : For DSI Control
bits : 2 - 2 (1 bit)
access : read-write
DSI_RCALT : For DSI Control
bits : 3 - 4 (2 bit)
access : read-write
DSI_NOCAL : For DSI Control
bits : 5 - 5 (1 bit)
access : read-write
DSI_HSEL : For DSI Control
bits : 6 - 6 (1 bit)
access : read-write
DSI_TX_ULPS_ENABLE : For DSI Control
bits : 7 - 11 (5 bit)
access : read-write
DSI_TRIGGER_SEND : For DSI Control
bits : 12 - 13 (2 bit)
access : read-write
DSI_TRIGGER_REQ : For DSI Control
bits : 14 - 14 (1 bit)
access : read-write
DDSI_DPHY_TURNAROUND : For DSI Control
bits : 15 - 15 (1 bit)
access : read-write
GPR24 General Purpose Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_TWO_BIT_ERR : for DSI status
bits : 0 - 0 (1 bit)
access : read-only
DSI_ECC_ONE_BIT_ERR_POS : for DSI status
bits : 1 - 5 (5 bit)
access : read-only
DSI_ECC_ONE_BIT_ERR : for DSI status
bits : 6 - 6 (1 bit)
access : read-only
DSI_ECC_ERR_POS : for DSI status
bits : 7 - 9 (3 bit)
access : read-only
DSI_ECC_ERR : for DSI status
bits : 10 - 10 (1 bit)
access : read-only
DSI_HOST_UNDERRUN_ERR : for DSI status
bits : 11 - 11 (1 bit)
access : read-only
DSI_TRIGGER_ACK : for DSI status
bits : 12 - 12 (1 bit)
access : read-only
DSI_LP_RX_TIMEOUT : for DSI status
bits : 13 - 13 (1 bit)
access : read-only
DSI_HS_TX_TIMEOUT : for DSI status
bits : 14 - 14 (1 bit)
access : read-only
DSI_HOST_BTA_TIMEOUT : for DSI status
bits : 15 - 15 (1 bit)
access : read-only
DSI_DPHY_DIRECTION : for DSI status
bits : 16 - 16 (1 bit)
access : read-only
DSI_CRC_ERR : for DSI status
bits : 17 - 17 (1 bit)
access : read-only
DSI_CALOUT : for DSI status
bits : 18 - 19 (2 bit)
access : read-only
DSI_CALCOMPL : for DSI status
bits : 20 - 20 (1 bit)
access : read-only
DSI_ULPS_ACTIVE : for DSI status
bits : 21 - 25 (5 bit)
access : read-only
GPR25 General Purpose Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_UI_STATUS3_RO : for DSI status: host_ui_status[125:96]
bits : 0 - 29 (30 bit)
access : read-only
GPR26 General Purpose Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_UI_STATUS2_RO : for DSI status: host_ui_status[95:64]
bits : 0 - 31 (32 bit)
access : read-only
GPR27 General Purpose Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_UI_STATUS1_RO : for DSI status: host_ui_status[63:32]
bits : 0 - 31 (32 bit)
access : read-only
GPR28 General Purpose Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_UI_STATUS0_RO : for DSI status: host_ui_status[31:0]
bits : 0 - 31 (32 bit)
access : read-only
GPR29 General Purpose Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_TEST_PATTERN : for DSI test control
bits : 0 - 31 (32 bit)
access : read-only
GPR30 General Purpose Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_D0_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
DSI_D0_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
DSI_D0_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR31 General Purpose Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_D1_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
DSI_D1_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
DSI_D1_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR2 General Purpose Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR_SAI1_EXT_MCLK_EN : SAI1 External MCLK Enable
bits : 0 - 0 (1 bit)
access : read-write
GPR_SAI2_EXT_MCLK_EN : SAI2 External MCLK Enable
bits : 1 - 1 (1 bit)
access : read-write
GPR_SAI3_EXT_MCLK_EN : SAI3 External MCLK Enable
bits : 2 - 2 (1 bit)
access : read-write
GPR_SAI4_EXT_MCLK_EN : SAI4 External MCLK Enable
bits : 3 - 3 (1 bit)
access : read-write
GPR_SAI5_EXT_MCLK_EN : SAI5 External MCLK Enable
bits : 4 - 4 (1 bit)
access : read-write
GPR_SAI6_EXT_MCLK_EN : SAI6 External MCLK Enable
bits : 5 - 5 (1 bit)
access : read-write
GPR32 General Purpose Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_D2_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
DSI_D2_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
DSI_D2_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR33 General Purpose Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSI_D3_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
DSI_D3_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
DSI_D3_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR34 General Purpose Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSI2_1_RX_RCAL : for CSI2_1 control
bits : 0 - 1 (2 bit)
access : read-write
CSI2_1_S_PRG_RXHS_SETTLE : for DSI test status
bits : 2 - 7 (6 bit)
access : read-write
CSI2_1_CONT_CLK_MODE : for DSI test status
bits : 8 - 8 (1 bit)
access : read-write
CSI2_1_AUTO_PD_EN : for DSI test status
bits : 9 - 9 (1 bit)
access : read-write
CSI2_1_HSEL : for DSI test status
bits : 10 - 10 (1 bit)
access : read-write
CSI2_1_PD_RX : for DSI test status
bits : 11 - 11 (1 bit)
access : read-write
CSI2_1_VID_INTFC_ENB : for DSI test status
bits : 12 - 12 (1 bit)
access : read-write
CSI2_1_RX_ENABLE : for DSI test status
bits : 13 - 13 (1 bit)
access : read-write
GPR35 General Purpose Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_1_ECC_TWO_BIT_ERROR : for CSI2_1 status
bits : 0 - 0 (1 bit)
access : read-only
CSI2_1_ECC_ONE_BIT_ERR_POS : for CSI2_1 status
bits : 1 - 5 (5 bit)
access : read-only
CSI2_1_ECC_ONE_BIT_ERROR : for CSI2_1 status
bits : 6 - 6 (1 bit)
access : read-only
CSI2_1_ECC_ERR_POS : for CSI2_1 status
bits : 7 - 9 (3 bit)
access : read-only
CSI2_1_ECC_ERR : for CSI2_1 status
bits : 10 - 10 (1 bit)
access : read-only
CSI2_1_ULPS_MARK_ACTIVE : for CSI2_1 status
bits : 11 - 15 (5 bit)
access : read-only
CSI2_1_RX_DPHY_RDY : for CSI2_1 status
bits : 16 - 16 (1 bit)
access : read-only
CSI2_1_CRC_ERR : for CSI2_1 status
bits : 17 - 17 (1 bit)
access : read-only
CSI2_1_ULPS_ACTIVE : for CSI2_1 status
bits : 18 - 22 (5 bit)
access : read-only
CSI2_1_ERR_FIFO_WR_OVFL : for CSI2_1 status
bits : 23 - 23 (1 bit)
access : read-only
CSI2_1_ERR_SEND_LEVEL : for CSI2_1 status
bits : 24 - 24 (1 bit)
access : read-only
GPR36 General Purpose Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_1_TEST_PATTERN : for CSI2_1 test control
bits : 0 - 31 (32 bit)
access : read-only
GPR37 General Purpose Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_1_D0_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
CSI2_1_D0_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
CSI2_1_D0_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR38 General Purpose Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_1_D1_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
CSI2_1_D1_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
CSI2_1_D1_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR39 General Purpose Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_1_D2_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
CSI2_1_D2_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
CSI2_1_D2_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR40 General Purpose Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_1_D3_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
CSI2_1_D3_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
CSI2_1_D3_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR41 General Purpose Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSI2_2_RX_RCAL : for CSI2_2 control
bits : 0 - 1 (2 bit)
access : read-write
CSI2_2_S_PRG_RXHS_SETTLE : for DSI test status
bits : 2 - 7 (6 bit)
access : read-write
CSI2_2_CONT_CLK_MODE : for DSI test status
bits : 8 - 8 (1 bit)
access : read-write
CSI2_2_AUTO_PD_EN : for DSI test status
bits : 9 - 9 (1 bit)
access : read-write
CSI2_2_HSEL : for DSI test status
bits : 10 - 10 (1 bit)
access : read-write
CSI2_2_PD_RX : for DSI test status
bits : 11 - 11 (1 bit)
access : read-write
CSI2_2_VID_INTFC_ENB : for DSI test status
bits : 12 - 12 (1 bit)
access : read-write
CSI2_2_RX_ENABLE : for DSI test status
bits : 13 - 13 (1 bit)
access : read-write
GPR42 General Purpose Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_2_ECC_TWO_BIT_ERROR : for CSI2_2 status
bits : 0 - 0 (1 bit)
access : read-only
CSI2_2_ECC_ONE_BIT_ERR_POS : for CSI2_2 status
bits : 1 - 5 (5 bit)
access : read-only
CSI2_2_ECC_ONE_BIT_ERROR : for CSI2_2 status
bits : 6 - 6 (1 bit)
access : read-only
CSI2_2_ECC_ERR_POS : for CSI2_2 status
bits : 7 - 9 (3 bit)
access : read-only
CSI2_2_ECC_ERR : for CSI2_2 status
bits : 10 - 10 (1 bit)
access : read-only
CSI2_2_ULPS_MARK_ACTIVE : for CSI2_2 status
bits : 11 - 15 (5 bit)
access : read-only
CSI2_2_RX_DPHY_RDY : for CSI2_2 status
bits : 16 - 16 (1 bit)
access : read-only
CSI2_2_CRC_ERR : for CSI2_2 status
bits : 17 - 17 (1 bit)
access : read-only
CSI2_2_ULPS_ACTIVE : for CSI2_2 status
bits : 18 - 22 (5 bit)
access : read-only
CSI2_2_ERR_FIFO_WR_OVFL : for CSI2_2 status
bits : 23 - 23 (1 bit)
access : read-only
CSI2_2_ERR_SEND_LEVEL : for CSI2_2 status
bits : 24 - 24 (1 bit)
access : read-only
GPR43 General Purpose Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_2_TEST_PATTERN : for CSI2_2 test control
bits : 0 - 31 (32 bit)
access : read-only
GPR44 General Purpose Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_2_D0_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
CSI2_2_D0_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
CSI2_2_D0_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR45 General Purpose Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_2_D1_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
CSI2_2_D1_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
CSI2_2_D1_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR46 General Purpose Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_2_D2_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
CSI2_2_D2_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
CSI2_2_D2_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR47 General Purpose Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSI2_2_D3_INT_LB_BYTE_CNT : for DSI test status
bits : 0 - 9 (10 bit)
access : read-only
CSI2_2_D3_INT_LB_ERR_CNT : for DSI test status
bits : 10 - 19 (10 bit)
access : read-only
CSI2_2_D3_LB_ACTIVE : for DSI test status
bits : 20 - 20 (1 bit)
access : read-only
GPR3 General Purpose Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDATA_WAIT_EN : On-chip RAM read data wait state control When the read data wait state is enabled, it will cost 2 cycles for each read access, (each beat of a read burst)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RDATA_WAIT_EN_0
read data wait state disabled
0x1 : RDATA_WAIT_EN_1
read data wait state enabled
End of enumeration elements list.
RADDR_PIPE_EN : On-chip RAM read address pipeline enable When this feature is enabled, the read address from the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RADDR_PIPE_EN_0
read address pipeline is disabled
0x1 : RADDR_PIPE_EN_1
read address pipeline is enabled
End of enumeration elements list.
WDATA_PIPE_EN : On-chip RAM write data pipeline enable When this feature is enabled, the write data from the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WDATA_PIPE_EN_0
write data pipeline is disabled
0x1 : WDATA_PIPE_EN_1
write data pipeline is enabled
End of enumeration elements list.
WADDR_PIPE_EN : On-chip RAM write address pipeline enable When this feature is enabled, the write address from the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : WADDR_PIPE_EN_0
write address pipeline is disabled
0x1 : WADDR_PIPE_EN_1
write address pipeline is enabled
End of enumeration elements list.
S_RDATA_WAIT_EN : State Retention On-chip RAM read data wait state control For description, please refer to RDATA_WAIT_EN bit
bits : 4 - 4 (1 bit)
access : read-write
S_RADDR_PIPE_EN : State Retention On-chip RAM read address pipeline enable For description, please refer to RADDR_PIPE_EN bit
bits : 5 - 5 (1 bit)
access : read-write
S_WDATA_PIPE_EN : State Retention On-chip RAM write data pipeline enable For description, please refer to WDATA_PIPE_EN bit
bits : 6 - 6 (1 bit)
access : read-write
S_WADDR_PIPE_EN : State Retention On-chip RAM write address pipeline enable For description, please refer to WADDR_PIPE_EN bit
bits : 7 - 7 (1 bit)
access : read-write
RDATA_WAIT_EN_PDG : On-chip RAM read data wait state control update is pending
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : RDATA_WAIT_EN_PDG_0
read data wait state control configuration valid
0x1 : RDATA_WAIT_EN_PDG_1
read data wait state control bit changed
End of enumeration elements list.
RADDR_PIPE_EN_PDG : On-chip RAM read address pipeline enable update is pending
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : RADDR_PIPE_EN_PDG_0
read address pipeline enable configuration valid
0x1 : RADDR_PIPE_EN_PDG_1
read address pipeline enable bit changed
End of enumeration elements list.
WDATA_PIPE_EN_PDG : On-chip RAM write data pipeline enable update is pending
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : WDATA_PIPE_EN_PDG_0
write data pipeline enable configuration valid
0x1 : WDATA_PIPE_EN_PDG_1
write data pipeline enable bit changed
End of enumeration elements list.
WADDR_PIPE_EN_PNDG : On-chip RAM write address pipeline enable update is pending
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : WADDR_PIPE_EN_PNDG_0
write address pipeline enable configuration valid
0x1 : WADDR_PIPE_EN_PNDG_1
write address pipeline enable bit changed
End of enumeration elements list.
S_RDATA_WAIT_EN_PNDG : State Retention On-chip RAM read data wait state control update is pending
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : S_RDATA_WAIT_EN_PNDG_0
read data wait state control configuration valid
0x1 : S_RDATA_WAIT_EN_PNDG_1
read data wait state control bit changed
End of enumeration elements list.
S_RADDR_PIPE_EN_PNDG : State Retention On-chip RAM read address pipeline enable update is pending
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : S_RADDR_PIPE_EN_PNDG_0
read address pipeline enable configuration valid
0x1 : S_RADDR_PIPE_EN_PNDG_1
read address pipeline enable bit changed
End of enumeration elements list.
S_WDATA_PIPE_EN_PNDG : State Retention On-chip RAM write data pipeline enable update is pending
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : S_WDATA_PIPE_EN_PNDG_0
write data pipeline enable configuration valid
0x1 : S_WDATA_PIPE_EN_PNDG_1
write data pipeline enable bit changed
End of enumeration elements list.
S_WADDR_PIPE_EN_PNDG : State Retention On-chip RAM write address pipeline enable update is pending
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : S_WADDR_PIPE_EN_PNDG_0
write address pipeline enable configuration valid
0x1 : S_WADDR_PIPE_EN_PNDG_1
write address pipeline enable bit changed
End of enumeration elements list.
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