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SPDIF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCR

SIC

SIS

SRL

SRR

SRCSH

SRCSL

SRU

SRQ

STL

STR

STCSCH

STCSCL

SRCD

SRFM

STC

SRPC

SIE


SCR

SPDIF Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USrc_Sel TxSel ValCtrl DMA_TX_En DMA_Rx_En TxFIFO_Ctrl soft_reset LOW_POWER TxFIFOEmpty_Sel TxAutoSync RxAutoSync RxFIFOFull_Sel RxFIFO_Rst RxFIFO_Off_On RxFIFO_Ctrl

USrc_Sel : no description available
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : USrc_Sel_0

No embedded U channel

0x1 : USrc_Sel_1

U channel from SPDIF receive block (CD mode)

0x3 : USrc_Sel_3

U channel from on chip transmitter

End of enumeration elements list.

TxSel : no description available
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : TxSel_0

Off and output 0

0x1 : TxSel_1

Feed-through SPDIFIN

0x5 : TxSel_5

Tx Normal operation

End of enumeration elements list.

ValCtrl : no description available
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ValCtrl_0

Outgoing Validity always set

0x1 : ValCtrl_1

Outgoing Validity always clear

End of enumeration elements list.

DMA_TX_En : DMA Transmit Request Enable (Tx FIFO empty)
bits : 8 - 8 (1 bit)
access : read-write

DMA_Rx_En : DMA Receive Request Enable (RX FIFO full)
bits : 9 - 9 (1 bit)
access : read-write

TxFIFO_Ctrl : no description available
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0 : TxFIFO_Ctrl_0

Send out digital zero on SPDIF Tx

0x1 : TxFIFO_Ctrl_1

Tx Normal operation

0x2 : TxFIFO_Ctrl_2

Reset to 1 sample remaining

End of enumeration elements list.

soft_reset : When write 1 to this bit, it will cause SPDIF software reset
bits : 12 - 12 (1 bit)
access : read-write

LOW_POWER : When write 1 to this bit, it will cause SPDIF enter low-power mode
bits : 13 - 13 (1 bit)
access : read-write

TxFIFOEmpty_Sel : no description available
bits : 15 - 16 (2 bit)
access : read-write

Enumeration:

0 : TxFIFOEmpty_Sel_0

Empty interrupt if 0 sample in Tx left and right FIFOs

0x1 : TxFIFOEmpty_Sel_1

Empty interrupt if at most 4 sample in Tx left and right FIFOs

0x2 : TxFIFOEmpty_Sel_2

Empty interrupt if at most 8 sample in Tx left and right FIFOs

0x3 : TxFIFOEmpty_Sel_3

Empty interrupt if at most 12 sample in Tx left and right FIFOs

End of enumeration elements list.

TxAutoSync : no description available
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : TxAutoSync_0

Tx FIFO auto sync off

0x1 : TxAutoSync_1

Tx FIFO auto sync on

End of enumeration elements list.

RxAutoSync : no description available
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : RxAutoSync_0

Rx FIFO auto sync off

0x1 : RxAutoSync_1

RxFIFO auto sync on

End of enumeration elements list.

RxFIFOFull_Sel : no description available
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

0 : RxFIFOFull_Sel_0

Full interrupt if at least 1 sample in Rx left and right FIFOs

0x1 : RxFIFOFull_Sel_1

Full interrupt if at least 4 sample in Rx left and right FIFOs

0x2 : RxFIFOFull_Sel_2

Full interrupt if at least 8 sample in Rx left and right FIFOs

0x3 : RxFIFOFull_Sel_3

Full interrupt if at least 16 sample in Rx left and right FIFO

End of enumeration elements list.

RxFIFO_Rst : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : RxFIFO_Rst_0

Normal operation

0x1 : RxFIFO_Rst_1

Reset register to 1 sample remaining

End of enumeration elements list.

RxFIFO_Off_On : no description available
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : RxFIFO_Off_On_0

SPDIF Rx FIFO is on

0x1 : RxFIFO_Off_On_1

SPDIF Rx FIFO is off. Does not accept data from interface

End of enumeration elements list.

RxFIFO_Ctrl : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : RxFIFO_Ctrl_0

Normal operation

0x1 : RxFIFO_Ctrl_1

Always read zero from Rx data register

End of enumeration elements list.


SIC

InterruptClear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SIC_SIS
reset_Mask : 0x0

SIC SIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LockLoss RxFIFOResyn RxFIFOUnOv UQErr UQSync QRxOv URxOv BitErr SymErr ValNoGood CNew TxResyn TxUnOv Lock

LockLoss : SPDIF receiver loss of lock
bits : 2 - 2 (1 bit)
access : write-only

RxFIFOResyn : Rx FIFO resync
bits : 3 - 3 (1 bit)
access : write-only

RxFIFOUnOv : Rx FIFO underrun/overrun
bits : 4 - 4 (1 bit)
access : write-only

UQErr : U/Q Channel framing error
bits : 5 - 5 (1 bit)
access : write-only

UQSync : U/Q Channel sync found
bits : 6 - 6 (1 bit)
access : write-only

QRxOv : Q Channel receive register overrun
bits : 7 - 7 (1 bit)
access : write-only

URxOv : U Channel receive register overrun
bits : 9 - 9 (1 bit)
access : write-only

BitErr : SPDIF receiver found parity bit error
bits : 14 - 14 (1 bit)
access : write-only

SymErr : SPDIF receiver found illegal symbol
bits : 15 - 15 (1 bit)
access : write-only

ValNoGood : SPDIF validity flag no good
bits : 16 - 16 (1 bit)
access : write-only

CNew : SPDIF receive change in value of control channel
bits : 17 - 17 (1 bit)
access : write-only

TxResyn : SPDIF Tx FIFO resync
bits : 18 - 18 (1 bit)
access : write-only

TxUnOv : SPDIF Tx FIFO under/overrun
bits : 19 - 19 (1 bit)
access : write-only

Lock : SPDIF receiver's DPLL is locked
bits : 20 - 20 (1 bit)
access : write-only


SIS

InterruptStat Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SIC_SIS
reset_Mask : 0x0

SIS SIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxFIFOFul TxEm LockLoss RxFIFOResyn RxFIFOUnOv UQErr UQSync QRxOv QRxFul URxOv URxFul BitErr SymErr ValNoGood CNew TxResyn TxUnOv Lock

RxFIFOFul : SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.
bits : 0 - 0 (1 bit)
access : read-only

TxEm : SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.
bits : 1 - 1 (1 bit)
access : read-only

LockLoss : SPDIF receiver loss of lock
bits : 2 - 2 (1 bit)
access : read-only

RxFIFOResyn : Rx FIFO resync
bits : 3 - 3 (1 bit)
access : read-only

RxFIFOUnOv : Rx FIFO underrun/overrun
bits : 4 - 4 (1 bit)
access : read-only

UQErr : U/Q Channel framing error
bits : 5 - 5 (1 bit)
access : read-only

UQSync : U/Q Channel sync found
bits : 6 - 6 (1 bit)
access : read-only

QRxOv : Q Channel receive register overrun
bits : 7 - 7 (1 bit)
access : read-only

QRxFul : Q Channel receive register full, can't be cleared with reg
bits : 8 - 8 (1 bit)
access : read-only

URxOv : U Channel receive register overrun
bits : 9 - 9 (1 bit)
access : read-only

URxFul : U Channel receive register full, can't be cleared with reg
bits : 10 - 10 (1 bit)
access : read-only

BitErr : SPDIF receiver found parity bit error
bits : 14 - 14 (1 bit)
access : read-only

SymErr : SPDIF receiver found illegal symbol
bits : 15 - 15 (1 bit)
access : read-only

ValNoGood : SPDIF validity flag no good
bits : 16 - 16 (1 bit)
access : read-only

CNew : SPDIF receive change in value of control channel
bits : 17 - 17 (1 bit)
access : read-only

TxResyn : SPDIF Tx FIFO resync
bits : 18 - 18 (1 bit)
access : read-only

TxUnOv : SPDIF Tx FIFO under/overrun
bits : 19 - 19 (1 bit)
access : read-only

Lock : SPDIF receiver's DPLL is locked
bits : 20 - 20 (1 bit)
access : read-only


SRL

SPDIFRxLeft Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRL SRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxDataLeft

RxDataLeft : Processor receive SPDIF data left
bits : 0 - 23 (24 bit)
access : read-only


SRR

SPDIFRxRight Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRR SRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxDataRight

RxDataRight : Processor receive SPDIF data right
bits : 0 - 23 (24 bit)
access : read-only


SRCSH

SPDIFRxCChannel_h Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRCSH SRCSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxCChannel_h

RxCChannel_h : SPDIF receive C channel register, contains first 24 bits of C channel without interpretation
bits : 0 - 23 (24 bit)
access : read-only


SRCSL

SPDIFRxCChannel_l Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRCSL SRCSL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxCChannel_l

RxCChannel_l : SPDIF receive C channel register, contains next 24 bits of C channel without interpretation
bits : 0 - 23 (24 bit)
access : read-only


SRU

UchannelRx Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRU SRU read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxUChannel

RxUChannel : SPDIF receive U channel register, contains next 3 U channel bytes
bits : 0 - 23 (24 bit)
access : read-only


SRQ

QchannelRx Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRQ SRQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxQChannel

RxQChannel : SPDIF receive Q channel register, contains next 3 Q channel bytes
bits : 0 - 23 (24 bit)
access : read-only


STL

SPDIFTxLeft Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STL STL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDataLeft

TxDataLeft : SPDIF transmit left channel data. It is write-only, and always returns zeros when read
bits : 0 - 23 (24 bit)
access : write-only


STR

SPDIFTxRight Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STR STR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDataRight

TxDataRight : SPDIF transmit right channel data. It is write-only, and always returns zeros when read
bits : 0 - 23 (24 bit)
access : write-only


STCSCH

SPDIFTxCChannelCons_h Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCSCH STCSCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCChannelCons_h

TxCChannelCons_h : SPDIF transmit Cons
bits : 0 - 23 (24 bit)
access : read-write


STCSCL

SPDIFTxCChannelCons_l Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCSCL STCSCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCChannelCons_l

TxCChannelCons_l : SPDIF transmit Cons
bits : 0 - 23 (24 bit)
access : read-write


SRCD

CDText Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCD SRCD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USyncMode

USyncMode : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : USyncMode_0

Non-CD data

0x1 : USyncMode_1

CD user channel subcode

End of enumeration elements list.


SRFM

FreqMeas Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRFM SRFM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FreqMeas

FreqMeas : Frequency measurement data
bits : 0 - 23 (24 bit)
access : read-only


STC

SPDIFTxClk Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STC STC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxClk_DF tx_all_clk_en TxClk_Source SYSCLK_DF

TxClk_DF : Divider factor (1-128)
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0 : TxClk_DF_0

divider factor is 1

0x1 : TxClk_DF_1

divider factor is 2

0x7F : TxClk_DF_127

divider factor is 128

End of enumeration elements list.

tx_all_clk_en : Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : tx_all_clk_en_0

disable transfer clock.

0x1 : tx_all_clk_en_1

enable transfer clock.

End of enumeration elements list.

TxClk_Source : no description available
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : TxClk_Source_0

REF_CLK_32K input (XTALOSC 32 kHz clock)

0x1 : TxClk_Source_1

tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)

0x3 : TxClk_Source_3

SPDIF_EXT_CLK, from pads

0x5 : TxClk_Source_5

ipg_clk input (frequency divided)

End of enumeration elements list.

SYSCLK_DF : system clock divider factor, 2~512.
bits : 11 - 19 (9 bit)
access : read-write

Enumeration:

0 : SYSCLK_DF_0

no clock signal

0x1 : SYSCLK_DF_1

divider factor is 2

0x1FF : SYSCLK_DF_511

divider factor is 512

End of enumeration elements list.


SRPC

PhaseConfig Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRPC SRPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GainSel LOCK ClkSrc_Sel

GainSel : Gain selection:
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

0 : GainSel_0

24*(2**10)

0x1 : GainSel_1

16*(2**10)

0x2 : GainSel_2

12*(2**10)

0x3 : GainSel_3

8*(2**10)

0x4 : GainSel_4

6*(2**10)

0x5 : GainSel_5

4*(2**10)

0x6 : GainSel_6

3*(2**10)

End of enumeration elements list.

LOCK : LOCK bit to show that the internal DPLL is locked, read only
bits : 6 - 6 (1 bit)
access : read-only

ClkSrc_Sel : Clock source selection, all other settings not shown are reserved:
bits : 7 - 10 (4 bit)
access : read-write

Enumeration:

0 : ClkSrc_Sel_0

if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)

0x1 : ClkSrc_Sel_1

if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)

0x3 : ClkSrc_Sel_3

if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK

0x5 : ClkSrc_Sel_5

REF_CLK_32K (XTALOSC)

0x6 : ClkSrc_Sel_6

tx_clk (SPDIF0_CLK_ROOT)

0x8 : ClkSrc_Sel_8

SPDIF_EXT_CLK

End of enumeration elements list.


SIE

InterruptEn Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIE SIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxFIFOFul TxEm LockLoss RxFIFOResyn RxFIFOUnOv UQErr UQSync QRxOv QRxFul URxOv URxFul BitErr SymErr ValNoGood CNew TxResyn TxUnOv Lock

RxFIFOFul : SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.
bits : 0 - 0 (1 bit)
access : read-write

TxEm : SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.
bits : 1 - 1 (1 bit)
access : read-write

LockLoss : SPDIF receiver loss of lock
bits : 2 - 2 (1 bit)
access : read-write

RxFIFOResyn : Rx FIFO resync
bits : 3 - 3 (1 bit)
access : read-write

RxFIFOUnOv : Rx FIFO underrun/overrun
bits : 4 - 4 (1 bit)
access : read-write

UQErr : U/Q Channel framing error
bits : 5 - 5 (1 bit)
access : read-write

UQSync : U/Q Channel sync found
bits : 6 - 6 (1 bit)
access : read-write

QRxOv : Q Channel receive register overrun
bits : 7 - 7 (1 bit)
access : read-write

QRxFul : Q Channel receive register full, can't be cleared with reg
bits : 8 - 8 (1 bit)
access : read-write

URxOv : U Channel receive register overrun
bits : 9 - 9 (1 bit)
access : read-write

URxFul : U Channel receive register full, can't be cleared with reg
bits : 10 - 10 (1 bit)
access : read-write

BitErr : SPDIF receiver found parity bit error
bits : 14 - 14 (1 bit)
access : read-write

SymErr : SPDIF receiver found illegal symbol
bits : 15 - 15 (1 bit)
access : read-write

ValNoGood : SPDIF validity flag no good
bits : 16 - 16 (1 bit)
access : read-write

CNew : SPDIF receive change in value of control channel
bits : 17 - 17 (1 bit)
access : read-write

TxResyn : SPDIF Tx FIFO resync
bits : 18 - 18 (1 bit)
access : read-write

TxUnOv : SPDIF Tx FIFO under/overrun
bits : 19 - 19 (1 bit)
access : read-write

Lock : SPDIF receiver's DPLL is locked
bits : 20 - 20 (1 bit)
access : read-write



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