\n
address_offset : 0x0 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : registers
protection : not protected
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FDYDSADDR
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FDCDSADDR
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FDYTSADDR
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FDCTSADDR
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FSIZE
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FSYSSA
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FSYSEA
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FSUVSSA
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FSUVSEA
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FCROPORIG
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FCROPSIZE
FRAME_REGISTERS[1]-FRAME_REGISTERS[0]-FDCTL
Luma video data start address
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DYDSADDR : Luma video data start address
bits : 0 - 31 (32 bit)
access : read-write
Frame size
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0WIDTH : Frame width
bits : 0 - 9 (10 bit)
access : read-write
F0HEIGHT : Frame height
bits : 16 - 25 (10 bit)
access : read-write
Luma data slave start address
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0YSTRBYPASS : Luma Start Tile to Raster scan Bypass
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0YSTRBYPASS_0
All ARADDR does NOT bypass the tile-to-rasterscan logic.
0x1 : F0YSTRBYPASS_1
All ARADDR bypasses the tile-to-rasterscan logic.
End of enumeration elements list.
F0SYSSA : Luma data slave start address
bits : 4 - 31 (28 bit)
access : read-write
Luma data slave end address
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0YETRBYPASS : End Tile to Raster scan Bypass
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0YETRBYPASS_0
All ARADDR does NOT bypass the tile-to-rasterscan logic.
0x1 : F0YETRBYPASS_1
All ARADDR bypasses the tile-to-rasterscan logic.
End of enumeration elements list.
F0SYSEA : Luma data slave end address
bits : 4 - 31 (28 bit)
access : read-write
Chroma data slave start address
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0CSTRBYPASS : Chroma Start Tile to Raster scan Bypass
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0CSTRBYPASS_0
All ARADDR does NOT bypass the tile-to-rasterscan logic.
0x1 : F0CSTRBYPASS_1
All ARADDR bypasses the tile-to-rasterscan logic.
End of enumeration elements list.
F0SUVSSA : Chroma data slave start address
bits : 4 - 31 (28 bit)
access : read-write
Chroma data slave end address
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0CETRBYPASS : End Tile to Raster scan Bypass
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0CETRBYPASS_0
All ARADDR does NOT bypass the tile-to-rasterscan logic.
0x1 : F0CETRBYPASS_1
All ARADDR bypasses the tile-to-rasterscan logic.
End of enumeration elements list.
F0SUVSEA : Chroma data slave end address
bits : 4 - 31 (28 bit)
access : read-write
Cropped picture origin
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0CROPORIGX : Cropped picture x origin
bits : 0 - 12 (13 bit)
access : read-write
F0CROPORIGY : Cropped picture y origin
bits : 16 - 28 (13 bit)
access : read-write
Cropped picture size
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0CROPWIDTH : Cropped picture width
bits : 0 - 12 (13 bit)
access : read-write
F0CROPHEIGHT : Cropped picture height
bits : 16 - 28 (13 bit)
access : read-write
Frame data control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0FRAMECFG : Frame configuration ready
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0FRAMECFG_0
Frame 0 configuration is not ready.
0x1 : F0FRAMECFG_1
Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit to 0.
End of enumeration elements list.
F0PIXELBITDEPTH : Pixel bit depth
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : F0PIXELBITDEPTH_0
10-bit pixel depth
0x1 : F0PIXELBITDEPTH_1
8-bit pixel depth
End of enumeration elements list.
F0DECOMPRESS : Decompress bypass
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : F0DECOMPRESS_0
G2 reference frame is compressed.
0x1 : F0DECOMPRESS_1
G2/G1 reference frame is not compressed.
End of enumeration elements list.
F0CROPENABLE : Cropped enable
bits : 18 - 18 (1 bit)
access : read-write
Chroma video data start address
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DCDSADDR : Chroma video data start address
bits : 0 - 31 (32 bit)
access : read-write
Luma video data start address
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DYDSADDR : Luma video data start address
bits : 0 - 31 (32 bit)
access : read-write
Chroma video data start address
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DCDSADDR : Chroma video data start address
bits : 0 - 31 (32 bit)
access : read-write
Luma table data start address
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DYTSADDR : Luma table data start address
bits : 0 - 31 (32 bit)
access : read-write
Chroma table data start address
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DCTSADDR : Chroma table data start address
bits : 0 - 31 (32 bit)
access : read-write
Frame size
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0WIDTH : Frame width
bits : 0 - 9 (10 bit)
access : read-write
F0HEIGHT : Frame height
bits : 16 - 25 (10 bit)
access : read-write
Luma data slave start address
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0YSTRBYPASS : Luma Start Tile to Raster scan Bypass
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0YSTRBYPASS_0
All ARADDR does NOT bypass the tile-to-rasterscan logic.
0x1 : F0YSTRBYPASS_1
All ARADDR bypasses the tile-to-rasterscan logic.
End of enumeration elements list.
F0SYSSA : Luma data slave start address
bits : 4 - 31 (28 bit)
access : read-write
Luma data slave end address
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0YETRBYPASS : End Tile to Raster scan Bypass
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0YETRBYPASS_0
All ARADDR does NOT bypass the tile-to-rasterscan logic.
0x1 : F0YETRBYPASS_1
All ARADDR bypasses the tile-to-rasterscan logic.
End of enumeration elements list.
F0SYSEA : Luma data slave end address
bits : 4 - 31 (28 bit)
access : read-write
Chroma data slave start address
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0CSTRBYPASS : Chroma Start Tile to Raster scan Bypass
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0CSTRBYPASS_0
All ARADDR does NOT bypass the tile-to-rasterscan logic.
0x1 : F0CSTRBYPASS_1
All ARADDR bypasses the tile-to-rasterscan logic.
End of enumeration elements list.
F0SUVSSA : Chroma data slave start address
bits : 4 - 31 (28 bit)
access : read-write
Luma table data start address
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DYTSADDR : Luma table data start address
bits : 0 - 31 (32 bit)
access : read-write
Chroma data slave end address
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0CETRBYPASS : End Tile to Raster scan Bypass
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0CETRBYPASS_0
All ARADDR does NOT bypass the tile-to-rasterscan logic.
0x1 : F0CETRBYPASS_1
All ARADDR bypasses the tile-to-rasterscan logic.
End of enumeration elements list.
F0SUVSEA : Chroma data slave end address
bits : 4 - 31 (28 bit)
access : read-write
Cropped picture origin
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0CROPORIGX : Cropped picture x origin
bits : 0 - 12 (13 bit)
access : read-write
F0CROPORIGY : Cropped picture y origin
bits : 16 - 28 (13 bit)
access : read-write
Cropped picture size
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0CROPWIDTH : Cropped picture width
bits : 0 - 12 (13 bit)
access : read-write
F0CROPHEIGHT : Cropped picture height
bits : 16 - 28 (13 bit)
access : read-write
Frame data control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0FRAMECFG : Frame configuration ready
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : F0FRAMECFG_0
Frame 0 configuration is not ready.
0x1 : F0FRAMECFG_1
Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit to 0.
End of enumeration elements list.
F0PIXELBITDEPTH : Pixel bit depth
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : F0PIXELBITDEPTH_0
10-bit pixel depth
0x1 : F0PIXELBITDEPTH_1
8-bit pixel depth
End of enumeration elements list.
F0DECOMPRESS : Decompress bypass
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : F0DECOMPRESS_0
G2 reference frame is compressed.
0x1 : F0DECOMPRESS_1
G2/G1 reference frame is not compressed.
End of enumeration elements list.
F0CROPENABLE : Cropped enable
bits : 18 - 18 (1 bit)
access : read-write
Chroma table data start address
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DCTSADDR : Chroma table data start address
bits : 0 - 31 (32 bit)
access : read-write
DTRC Interrupt enables
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAMEFETCHDONE_EN : Frame fetch done interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FRAMEFETCHDONE_EN_0
Frame fetch done interrupt disabled.
0x1 : FRAMEFETCHDONE_EN_1
Frame fetch done interrupt enabled.
End of enumeration elements list.
BUSERROR_EN : Bus error interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : BUSERROR_EN_0
Bus error interrupt disabled.
0x1 : BUSERROR_EN_1
Bus error interrupt enabled.
End of enumeration elements list.
TIMEOUT_EN : Time out enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TIMEOUT_EN_0
Time out disabled.
0x1 : TIMEOUT_EN_1
Time out enabled.
End of enumeration elements list.
SLFRAMEFETCHDONE_EN : Slave frame fetch done
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SLFRAMEFETCHDONE_EN_0
Slave frame fetch done disabled.
0x1 : SLFRAMEFETCHDONE_EN_1
Slave frame fetch done enabled.
End of enumeration elements list.
HOTRESETFINISH_EN : Hot reset finish
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : HOTRESETFINISH_EN_0
Hot reset finish disabled.
0x1 : HOTRESETFINISH_EN_1
Hot reset finish enabled.
End of enumeration elements list.
DTRC Interrupt Requests
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAMEFETCHDONE : Frame fetch done interrupt
bits : 0 - 0 (1 bit)
access : read-only
BUSERROR : Bus error interrupt
bits : 1 - 1 (1 bit)
access : read-only
TIMEOUT : Time out interrupt
bits : 2 - 2 (1 bit)
access : read-write
SLFRAMEFETCHDONE : Slave frame fetch done interrupt
bits : 3 - 3 (1 bit)
access : read-write
HOTRESETFINISH : Hot reset finish interrupt
bits : 4 - 4 (1 bit)
access : read-write
DTRC Control
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARIDRCFG : ARIDR configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ARIDRCFG_0
All ARID is de-tiled.
0x1 : ARIDRCFG_1
ARID in ARIDR is de-tiled, and others are bypass. NOTE: ARID[0] specify decode luma or chroma, so 4 ARIDs in ARIDR should include both of ARID[0] ==1 and ARID[0] ==0.
0x2 : ARIDRCFG_2
ARID in ARIDR is bypass_de-tile, and others are de-tiled.
0x3 : ARIDRCFG_3
Same as 2'b01.
End of enumeration elements list.
HOTRESETTRIG : Hot reset trigger
bits : 2 - 2 (1 bit)
access : read-write
G1G2DATA : G2 or G1 source data
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : G1G2DATA_0
The source data is G2 data.
0x1 : G1G2DATA_1
The source data is G1 tile data
End of enumeration elements list.
AXIMAXBURSTL : Maximum burst length of AXI master port
bits : 4 - 11 (8 bit)
access : read-write
BYTESWAP_SLRAST : Byte swap mode for slave interface raster scan data
bits : 12 - 15 (4 bit)
access : read-write
BYTESWAP_MCOMPTILE : Byte swap mode for master interface compressed data and tiled data
bits : 16 - 19 (4 bit)
access : read-write
BYTESWAP_MTABLE : Byte swap mode for master interface table data
bits : 20 - 23 (4 bit)
access : read-write
BYTESWAP_M_NONG1G2 : Byte swap mode for master interface non-G1/G2 data
bits : 24 - 27 (4 bit)
access : read-write
MERGEG1G2_ARIDEN : Merge G2/G1 ARID enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : MERGEG1G2_ARIDEN_0
G2/G1 transactions at AXI master interface use different id for table/chroma and data/luma according to DTID2DDR definition.
0x1 : MERGEG1G2_ARIDEN_1
All G2/G1 transactions at AXI master interface use the same id configured in DTID2DDR[15:8] Please note that DTID2DDR[15:8] and DTID2DDR[7:0] still need to be set the same way as when DTCTRL[28] is 0.
End of enumeration elements list.
RAST_ENDIAN : Raster endian mode
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : RAST_ENDIAN_0
10-bit output format is little-endian. Byte swap setting of DTCTRL[15:12] is used.
0x1 : RAST_ENDIAN_1
10-bit output format is big-endian. Byte swap setting of DTCTRL[15:12] is ignored.
End of enumeration elements list.
ADDR_ARID : ADDR_ARID
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ADDR_ARID_0
By ARID (See bit[1:0] of this register).
0x1 : ADDR_ARID_1
By ARADDR
End of enumeration elements list.
FRBUFF_PTR : FRBUFF_PTR
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : FRBUFF_PTR_0
Configure frame 0 registers.
0x1 : FRBUFF_PTR_1
Configure frame 1 registers.
End of enumeration elements list.
ARIDR
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARIDR : ARIDR
bits : 0 - 31 (32 bit)
access : read-write
DTID2DDR
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARID_COMPR : ARID_COMPR
bits : 0 - 7 (8 bit)
access : read-write
ARID_TABLE : ARID_TABLE
bits : 8 - 15 (8 bit)
access : read-write
DTRCCONFIG
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
G1G2_KEEPORDER : G1G2_KEEPORDER
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : G1G2_KEEPORDER_0
Not supported. DTRC sends out data transactions as soon as they are ready regardless of the address transactions order, The master connected to AXI slave interface must recognize the data transactions by the RID.
0x1 : G1G2_KEEPORDER_1
Supported, DTRC ensure return read data from a sequence of read transactions in the same order in which it received the address.
End of enumeration elements list.
AXI_MAXBURSTL : AXI_MAXBURSTL
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : AXI_MAXBURSTL_0
Not supported.
0x1 : AXI_MAXBURSTL_1
Supported. DTRC sends the G1/G2 relating requests with ARLEN <= (the maximum burst length - 1). The maximum burst length is set by DTCTRL[16:8].
End of enumeration elements list.
G1TILE_INPUT : G1TILE_INPUT
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : G1TILE_INPUT_0
Not supported.
0x1 : G1TILE_INPUT_1
Supported.
End of enumeration elements list.
MAX_PIC_WIDTH : MAX_PIC_WIDTH
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
0 : MAX_PIC_WIDTH_0
4096
0x1 : MAX_PIC_WIDTH_1
1920
End of enumeration elements list.
DTRC Version
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CUST_VERSION : CUST_VERSION
bits : 0 - 3 (4 bit)
access : read-only
MINOR : MINOR
bits : 4 - 9 (6 bit)
access : read-only
MAJOR : MAJOR
bits : 10 - 15 (6 bit)
access : read-only
Performance counter control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFC_EN : PFC_EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PFC_EN_0
Performance Counter disabled.
0x1 : PFC_EN_1
Performance Counter enabled.
End of enumeration elements list.
Performance counter
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFCR : Performance Counter
bits : 0 - 31 (32 bit)
access : read-write
Time Out Cycles
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOCR : Time Out Cycles
bits : 0 - 31 (32 bit)
access : read-write
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