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address_offset : 0x0 Bytes (0x0)
size : 0xF3 byte (0x0)
mem_usage : registers
protection : not protected
Scale Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_SCALER : This bit, when set to logic 1, causes the scaler to begin processing a frame buffer based on all current programmable settings
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_REPEAT : This bit enables the scaler to restart processing a frame buffer without receiving a SW "kick" event using the ENABLE_SCALER control bit
bits : 4 - 4 (1 bit)
access : read-write
ENABLE_SCALE2MEM : This bit enables the path from the scaler output back to the system memory
bits : 8 - 8 (1 bit)
access : read-write
ENABLE_MEM2OFIFO : This bit enables the path from external memory to drive the data into the scale output FIFO
bits : 12 - 12 (1 bit)
access : read-write
Scale Source Format Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_FORMAT : These bits define the input buffer format
bits : 0 - 1 (2 bit)
access : read-write
Scale Destination Format Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_FORMAT : These bits define the scaler output format. 1: YUV422. 2: RGB888/YUV444. Other: Reserved.
bits : 0 - 1 (2 bit)
access : read-write
Scale Source Luma Resolution Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : This field defines the width of the source image in pixels minus 1
bits : 0 - 11 (12 bit)
access : read-write
HEIGHT : This field defines the height of the source image in pixels minus 1
bits : 16 - 27 (12 bit)
access : read-write
Scale Source Chroma Resolution Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : This field defines the width of the source image in pixels minus 1
bits : 0 - 11 (12 bit)
access : read-write
HEIGHT : This field defines the height of the source image in pixels minus 1
bits : 16 - 27 (12 bit)
access : read-write
Scale Destination Luma Resolution Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : This field defines the width of the destination image in pixels minus 1.
bits : 0 - 11 (12 bit)
access : read-write
HEIGHT : This field defines the height of the destination image in pixels minus 1.
bits : 16 - 27 (12 bit)
access : read-write
Scale Destination Chroma Resolution Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : This field defines the width of the destination image in pixels minus 1.
bits : 0 - 11 (12 bit)
access : read-write
Scale Output FIFO Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFIFO_LOW_THRESH : This value is used to detect when the output FIFO has a number of pixels that are valid that first exceeds this value, and then decrements to a value equal to the value programmed in this register
bits : 0 - 9 (10 bit)
access : read-write
OFIFO_HIGH_THRESH : This value is used to detect when the output FIFO has a number of pixels that are valid that first exceeds this value, and then decrements to a value equal to the value programmed in this register
bits : 16 - 25 (10 bit)
access : read-write
CLEAR_UNDERRUN_DETECT : This bit clears the underrun detected interrupt
bits : 26 - 26 (1 bit)
access : read-write
CLEAR_LOW_THRESH_DETECT : This bit clears the low threshold detect interrupt 0: disabled, no action
bits : 27 - 27 (1 bit)
access : read-write
CLEAR_HIGH_THRESH_DETECT : This bit clears the high threshold detect interrupt
bits : 28 - 28 (1 bit)
access : read-write
ENABLE_UNDERRUN_DETECT : This bit controls if the underrun on the output FIFO can generate an interrupt
bits : 29 - 29 (1 bit)
access : read-write
ENABLE_LOW_THRESH_DETECT : This bit controls if the low threshold detection of the output FIFO can generate an interrupt
bits : 30 - 30 (1 bit)
access : read-write
ENABLE_HIGH_THRESH_DETECT : This bit controls if the high threshold detection of the output FIFO can generate an interrupt
bits : 31 - 31 (1 bit)
access : read-write
Scale Vertical Luma Start Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V_START : This register contains 13 integer and 13 fractional bits to define the vertical offset into the start of the prefetched image
bits : 0 - 25 (26 bit)
access : read-write
Scale Vertical Luma Increment Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V_INC : Vertical increment value used for scaling the image
bits : 0 - 19 (20 bit)
access : read-write
Scale Horizontal Luma Start Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H_START : This register contains 13 integer and 13 fractional bits to define the horizontal offset into the start of the prefetched image
bits : 0 - 25 (26 bit)
access : read-write
Scale Horizontal Luma Increment Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H_INC : Horizontal increment value used for scaling the image
bits : 0 - 19 (20 bit)
access : read-write
Scale Vertical Chroma Start Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V_START : This register contains 13 integer and 13 fractional bits to define the vertical offset into the start of the prefetched image
bits : 0 - 25 (26 bit)
access : read-write
Scale Vertical Chroma Increment Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V_INC : Vertical increment value used for scaling the image
bits : 0 - 19 (20 bit)
access : read-write
Scale Horizontal Chroma Start Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H_START : This register contains 13 integer and 13 fractional bits to define the horizontal offset into the start of the prefetched image
bits : 0 - 25 (26 bit)
access : read-write
Scale Horizontal Chroma Increment Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H_INC : Horizontal increment value used for scaling the image
bits : 0 - 19 (20 bit)
access : read-write
Scale Source Data Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_SELECT : This bit controls whether the source is Video format(YUV) or Graphics(RGB)
bits : 0 - 0 (1 bit)
access : read-write
RTRAM_LINES_PER_BANK : This field determines the number of lines that are used in each bank of the RTRAM_CTRL module
bits : 1 - 1 (1 bit)
access : read-write
Y_UV_BYTE_SWAP : This bit controls the swapping of alternate bytes in the incoming data word
bits : 4 - 4 (1 bit)
access : read-write
A2R10G10B10_FORMAT : This field represents the data arrangement in the memory in case 10 RGB mode
bits : 8 - 11 (4 bit)
access : read-write
Scale Coefficient Memory Array
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEF : The coefficients have 1-bit sign, 1-bit integer, and 10-bits fraction
bits : 0 - 11 (12 bit)
access : read-write
Scale Bit Depth Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LUMA_BIT_DEPTH : These bits determine the bit depth of the primary component (Y, RGB) processing
bits : 0 - 1 (2 bit)
access : read-write
CHROMA_BIT_DEPTH : These bits determine the bit depth of the alternate component (UV 2-plane) processing
bits : 4 - 5 (2 bit)
access : read-write
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