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RD_SRC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL_STATUS

BASE_ADDR

PITCH

WIDTH

HEIGHT

CTRL_STATUS_SET

CTRL_STATUS_CLR

CTRL_STATUS_TOG


CTRL_STATUS

Control register for Read surface.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STATUS CTRL_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE BPP T_SIZE P_SIZE FRAME_COMP_EN RD_ERR_EN FIFO_SIZE FRAME_COMP RD_ERR

ENABLE : Read surface enable.
bits : 0 - 0 (1 bit)
access : read-write

BPP : Bits per pixel
bits : 2 - 4 (3 bit)
access : read-write

T_SIZE : Transaction Size (T_SIZE)
bits : 5 - 6 (2 bit)
access : read-write

P_SIZE : Payload size (P_SIZE)
bits : 7 - 9 (3 bit)
access : read-write

FRAME_COMP_EN : Frame complete IRQ enable
bits : 14 - 14 (1 bit)
access : read-write

RD_ERR_EN : AXI Read Error IRQ enable
bits : 15 - 15 (1 bit)
access : read-write

FIFO_SIZE : FIFO size
bits : 16 - 22 (7 bit)
access : read-only

FRAME_COMP : Frame processing complete
bits : 30 - 30 (1 bit)
access : read-write

RD_ERR : AXI Read Error
bits : 31 - 31 (1 bit)
access : read-write


BASE_ADDR

Read Surface Base address
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASE_ADDR BASE_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDR

BASE_ADDR : Base address
bits : 0 - 31 (32 bit)
access : read-write


PITCH

Read surface vertical pitch
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PITCH PITCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PITCH

PITCH : Pitch
bits : 0 - 15 (16 bit)
access : read-write


WIDTH

Source frame buffer width
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WIDTH WIDTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WIDTH

WIDTH : Width
bits : 0 - 15 (16 bit)
access : read-write


HEIGHT

Height of frame to be read
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HEIGHT HEIGHT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HEIGHT

HEIGHT : Height
bits : 0 - 15 (16 bit)
access : read-write


CTRL_STATUS_SET

Control register for Read surface.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STATUS_SET CTRL_STATUS_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE BPP T_SIZE P_SIZE FRAME_COMP_EN RD_ERR_EN FIFO_SIZE FRAME_COMP RD_ERR

ENABLE : Read surface enable.
bits : 0 - 0 (1 bit)
access : read-write

BPP : Bits per pixel
bits : 2 - 4 (3 bit)
access : read-write

T_SIZE : Transaction Size (T_SIZE)
bits : 5 - 6 (2 bit)
access : read-write

P_SIZE : Payload size (P_SIZE)
bits : 7 - 9 (3 bit)
access : read-write

FRAME_COMP_EN : Frame complete IRQ enable
bits : 14 - 14 (1 bit)
access : read-write

RD_ERR_EN : AXI Read Error IRQ enable
bits : 15 - 15 (1 bit)
access : read-write

FIFO_SIZE : FIFO size
bits : 16 - 22 (7 bit)
access : read-only

FRAME_COMP : Frame processing complete
bits : 30 - 30 (1 bit)
access : read-write

RD_ERR : AXI Read Error
bits : 31 - 31 (1 bit)
access : read-write


CTRL_STATUS_CLR

Control register for Read surface.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STATUS_CLR CTRL_STATUS_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE BPP T_SIZE P_SIZE FRAME_COMP_EN RD_ERR_EN FIFO_SIZE FRAME_COMP RD_ERR

ENABLE : Read surface enable.
bits : 0 - 0 (1 bit)
access : read-write

BPP : Bits per pixel
bits : 2 - 4 (3 bit)
access : read-write

T_SIZE : Transaction Size (T_SIZE)
bits : 5 - 6 (2 bit)
access : read-write

P_SIZE : Payload size (P_SIZE)
bits : 7 - 9 (3 bit)
access : read-write

FRAME_COMP_EN : Frame complete IRQ enable
bits : 14 - 14 (1 bit)
access : read-write

RD_ERR_EN : AXI Read Error IRQ enable
bits : 15 - 15 (1 bit)
access : read-write

FIFO_SIZE : FIFO size
bits : 16 - 22 (7 bit)
access : read-only

FRAME_COMP : Frame processing complete
bits : 30 - 30 (1 bit)
access : read-write

RD_ERR : AXI Read Error
bits : 31 - 31 (1 bit)
access : read-write


CTRL_STATUS_TOG

Control register for Read surface.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STATUS_TOG CTRL_STATUS_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE BPP T_SIZE P_SIZE FRAME_COMP_EN RD_ERR_EN FIFO_SIZE FRAME_COMP RD_ERR

ENABLE : Read surface enable.
bits : 0 - 0 (1 bit)
access : read-write

BPP : Bits per pixel
bits : 2 - 4 (3 bit)
access : read-write

T_SIZE : Transaction Size (T_SIZE)
bits : 5 - 6 (2 bit)
access : read-write

P_SIZE : Payload size (P_SIZE)
bits : 7 - 9 (3 bit)
access : read-write

FRAME_COMP_EN : Frame complete IRQ enable
bits : 14 - 14 (1 bit)
access : read-write

RD_ERR_EN : AXI Read Error IRQ enable
bits : 15 - 15 (1 bit)
access : read-write

FIFO_SIZE : FIFO size
bits : 16 - 22 (7 bit)
access : read-only

FRAME_COMP : Frame processing complete
bits : 30 - 30 (1 bit)
access : read-write

RD_ERR : AXI Read Error
bits : 31 - 31 (1 bit)
access : read-write



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