\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Control register for Read surface.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Read surface enable.
bits : 0 - 0 (1 bit)
access : read-write
BPP : Bits per pixel
bits : 2 - 4 (3 bit)
access : read-write
T_SIZE : Transaction Size (T_SIZE)
bits : 5 - 6 (2 bit)
access : read-write
P_SIZE : Payload size (P_SIZE)
bits : 7 - 9 (3 bit)
access : read-write
FRAME_COMP_EN : Frame complete IRQ enable
bits : 14 - 14 (1 bit)
access : read-write
RD_ERR_EN : AXI Read Error IRQ enable
bits : 15 - 15 (1 bit)
access : read-write
FIFO_SIZE : FIFO size
bits : 16 - 22 (7 bit)
access : read-only
FRAME_COMP : Frame processing complete
bits : 30 - 30 (1 bit)
access : read-write
RD_ERR : AXI Read Error
bits : 31 - 31 (1 bit)
access : read-write
Read Surface Base address
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDR : Base address
bits : 0 - 31 (32 bit)
access : read-write
Read surface vertical pitch
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PITCH : Pitch
bits : 0 - 15 (16 bit)
access : read-write
Source frame buffer width
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width
bits : 0 - 15 (16 bit)
access : read-write
Height of frame to be read
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HEIGHT : Height
bits : 0 - 15 (16 bit)
access : read-write
Control register for Read surface.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Read surface enable.
bits : 0 - 0 (1 bit)
access : read-write
BPP : Bits per pixel
bits : 2 - 4 (3 bit)
access : read-write
T_SIZE : Transaction Size (T_SIZE)
bits : 5 - 6 (2 bit)
access : read-write
P_SIZE : Payload size (P_SIZE)
bits : 7 - 9 (3 bit)
access : read-write
FRAME_COMP_EN : Frame complete IRQ enable
bits : 14 - 14 (1 bit)
access : read-write
RD_ERR_EN : AXI Read Error IRQ enable
bits : 15 - 15 (1 bit)
access : read-write
FIFO_SIZE : FIFO size
bits : 16 - 22 (7 bit)
access : read-only
FRAME_COMP : Frame processing complete
bits : 30 - 30 (1 bit)
access : read-write
RD_ERR : AXI Read Error
bits : 31 - 31 (1 bit)
access : read-write
Control register for Read surface.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Read surface enable.
bits : 0 - 0 (1 bit)
access : read-write
BPP : Bits per pixel
bits : 2 - 4 (3 bit)
access : read-write
T_SIZE : Transaction Size (T_SIZE)
bits : 5 - 6 (2 bit)
access : read-write
P_SIZE : Payload size (P_SIZE)
bits : 7 - 9 (3 bit)
access : read-write
FRAME_COMP_EN : Frame complete IRQ enable
bits : 14 - 14 (1 bit)
access : read-write
RD_ERR_EN : AXI Read Error IRQ enable
bits : 15 - 15 (1 bit)
access : read-write
FIFO_SIZE : FIFO size
bits : 16 - 22 (7 bit)
access : read-only
FRAME_COMP : Frame processing complete
bits : 30 - 30 (1 bit)
access : read-write
RD_ERR : AXI Read Error
bits : 31 - 31 (1 bit)
access : read-write
Control register for Read surface.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Read surface enable.
bits : 0 - 0 (1 bit)
access : read-write
BPP : Bits per pixel
bits : 2 - 4 (3 bit)
access : read-write
T_SIZE : Transaction Size (T_SIZE)
bits : 5 - 6 (2 bit)
access : read-write
P_SIZE : Payload size (P_SIZE)
bits : 7 - 9 (3 bit)
access : read-write
FRAME_COMP_EN : Frame complete IRQ enable
bits : 14 - 14 (1 bit)
access : read-write
RD_ERR_EN : AXI Read Error IRQ enable
bits : 15 - 15 (1 bit)
access : read-write
FIFO_SIZE : FIFO size
bits : 16 - 22 (7 bit)
access : read-only
FRAME_COMP : Frame processing complete
bits : 30 - 30 (1 bit)
access : read-write
RD_ERR : AXI Read Error
bits : 31 - 31 (1 bit)
access : read-write
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