Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1200 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDBG : Enable Debug
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : EDBG_0
When in debug mode, the DMA continues to operate.
0x1 : EDBG_1
When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
End of enumeration elements list.
ERCA : Enable Round Robin Channel Arbitration
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ERCA_0
Fixed priority arbitration is used for channel selection .
0x1 : ERCA_1
Round robin arbitration is used for channel selection .
End of enumeration elements list.
HOE : Halt On Error
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : HOE_0
Normal operation
0x1 : HOE_1
Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
End of enumeration elements list.
HALT : Halt DMA Operations
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HALT_0
Normal operation
0x1 : HALT_1
Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
End of enumeration elements list.
CLM : Continuous Link Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CLM_0
A minor loop channel link made to itself goes through channel arbitration before being activated again.
0x1 : CLM_1
A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
End of enumeration elements list.
EMLM : Enable Minor Loop Mapping
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : EMLM_0
Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
0x1 : EMLM_1
Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
End of enumeration elements list.
ECX : Error Cancel Transfer
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : ECX_0
Normal operation
0x1 : ECX_1
Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
End of enumeration elements list.
CX : Cancel Transfer
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CX_0
Normal operation
0x1 : CX_1
Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
End of enumeration elements list.
ACTIVE : DMA Active Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ACTIVE_0
eDMA is idle.
0x1 : ACTIVE_1
eDMA is executing a channel.
End of enumeration elements list.
Channel Priority Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1004 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1006 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Register
address_offset : 0x101 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Destination Address
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1014 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1016 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1016 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x101C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x101E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x101E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel Priority Register
address_offset : 0x102 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1024 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1026 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Register
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Destination Address
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1034 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1036 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1036 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x103C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x103E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x103E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel Priority Register
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1044 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1046 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Register
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Destination Address
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1054 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1056 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1056 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x105C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x105E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x105E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel Priority Register
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1064 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1066 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Register
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Destination Address
address_offset : 0x1070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1074 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1076 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1076 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x107C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x107E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x107E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel Priority Register
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1084 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1086 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x108C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Register
address_offset : 0x109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Destination Address
address_offset : 0x1090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1094 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1096 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1096 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x109C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x109E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x109E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel Priority Register
address_offset : 0x10A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x10A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x10A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x10A6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x10AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Register
address_offset : 0x10B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Destination Address
address_offset : 0x10B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x10B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x10B6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x10B6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x10B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x10BC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x10BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x10BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel Priority Register
address_offset : 0x10C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x10C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x10C4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x10C6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x10CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Register
address_offset : 0x10D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Destination Address
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x10D4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x10D6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x10D6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x10D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x10DC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x10DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x10DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel Priority Register
address_offset : 0x10E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x10E4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x10E6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x10EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
Channel Priority Register
address_offset : 0x10F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
DPA : Disable Preempt Ability. This field resets to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DPA_0
Channel n can suspend a lower priority channel.
0x1 : DPA_1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption. This field resets to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ECP_0
Channel n cannot be suspended by a higher priority channel's service request.
0x1 : ECP_1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Destination Address
address_offset : 0x10F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x10F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x10F6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x10F6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x10F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x10FC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x10FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x10FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Source Address
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1106 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x110C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1116 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1116 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x111C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x111E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x111E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Source Address
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1126 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x112C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1136 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1136 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x113C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x113E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x113E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Source Address
address_offset : 0x1140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1146 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x114C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1154 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1156 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1156 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x115C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x115E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x115E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Source Address
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1164 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1166 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x116C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1174 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1176 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1176 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x117C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x117E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x117E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Source Address
address_offset : 0x1180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1184 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1186 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x118C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1194 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1196 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1196 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x119C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x119E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x119E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Source Address
address_offset : 0x11A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x11A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x11A6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x11A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x11A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x11A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x11AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x11B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x11B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x11B6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x11B6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x11B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x11BC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x11BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x11BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Source Address
address_offset : 0x11C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x11C4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x11C6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x11C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x11C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x11C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x11CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x11D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x11D4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x11D6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x11D6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x11D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x11DC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x11DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x11DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Source Address
address_offset : 0x11E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x11E4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x11E6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : SSIZE_0
8-bit
0x1 : SSIZE_1
16-bit
0x2 : SSIZE_2
32-bit
0x3 : SSIZE_3
64-bit
0x5 : SSIZE_5
32-byte burst (4 beats of 64 bits)
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : SMOD_0
Source address modulo feature is disabled
0x1 : SMOD_1
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x2 : SMOD_2
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x3 : SMOD_3
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x4 : SMOD_4
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x5 : SMOD_5
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x6 : SMOD_6
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x7 : SMOD_7
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x8 : SMOD_8
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
0x9 : SMOD_9
This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x11E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x11E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x11E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_NBYTES
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DMLOE_0
The minor loop offset is not applied to the DADDR
0x1 : DMLOE_1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SMLOE_0
The minor loop offset is not applied to the SADDR
0x1 : SMLOE_1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x11EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x11F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x11F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x11F6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x11F6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_CITER_ELINK
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x11F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : DLASTSGA
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x11FC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_0
The channel is not explicitly started.
0x1 : START_1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INTMAJOR_0
The end-of-major loop interrupt is disabled.
0x1 : INTMAJOR_1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTHALF_0
The half-point interrupt is disabled.
0x1 : INTHALF_1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DREQ_0
The channel's ERQ bit is not affected.
0x1 : DREQ_1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ESG_0
The current channel's TCD is normal format.
0x1 : ESG_1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MAJORELINK_0
The channel-to-channel linking is disabled.
0x1 : MAJORELINK_1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-only
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 11 (4 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BWC_0
No eDMA engine stalls.
0x2 : BWC_2
eDMA engine stalls for 4 cycles after each R/W.
0x3 : BWC_3
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x11FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x11FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : TCD_BITER_ELINK
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 12 (4 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ELINK_0
The channel-to-channel linking is disabled
0x1 : ELINK_1
The channel-to-channel linking is enabled
End of enumeration elements list.
Enable Error Interrupt Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EEI0 : Enable Error Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EEI0_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI0_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI1 : Enable Error Interrupt 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : EEI1_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI1_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI2 : Enable Error Interrupt 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : EEI2_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI2_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI3 : Enable Error Interrupt 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : EEI3_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI3_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI4 : Enable Error Interrupt 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EEI4_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI4_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI5 : Enable Error Interrupt 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : EEI5_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI5_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI6 : Enable Error Interrupt 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : EEI6_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI6_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI7 : Enable Error Interrupt 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : EEI7_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI7_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI8 : Enable Error Interrupt 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : EEI8_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI8_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI9 : Enable Error Interrupt 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : EEI9_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI9_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI10 : Enable Error Interrupt 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : EEI10_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI10_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI11 : Enable Error Interrupt 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : EEI11_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI11_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI12 : Enable Error Interrupt 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : EEI12_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI12_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI13 : Enable Error Interrupt 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : EEI13_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI13_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI14 : Enable Error Interrupt 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : EEI14_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI14_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI15 : Enable Error Interrupt 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : EEI15_0
The error signal for corresponding channel does not generate an error interrupt
0x1 : EEI15_1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
Clear Enable Error Interrupt Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEEI : Clear Enable Error Interrupt
bits : 0 - 3 (4 bit)
access : read-write
CAEE : Clear All Enable Error Interrupts
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CAEE_0
Clear only the EEI bit specified in the CEEI field
0x1 : CAEE_1
Clear all bits in EEI
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOP_0
Normal operation
0x1 : NOP_1
No operation, ignore the other bits in this register
End of enumeration elements list.
Set Enable Error Interrupt Register
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEEI : Set Enable Error Interrupt
bits : 0 - 3 (4 bit)
access : read-write
SAEE : Sets All Enable Error Interrupts
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SAEE_0
Set only the EEI bit specified in the SEEI field.
0x1 : SAEE_1
Sets all bits in EEI
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOP_0
Normal operation
0x1 : NOP_1
No operation, ignore the other bits in this register
End of enumeration elements list.
Clear Enable Request Register
address_offset : 0x1A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CERQ : Clear Enable Request
bits : 0 - 3 (4 bit)
access : read-write
CAER : Clear All Enable Requests
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CAER_0
Clear only the ERQ bit specified in the CERQ field
0x1 : CAER_1
Clear all bits in ERQ
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOP_0
Normal operation
0x1 : NOP_1
No operation, ignore the other bits in this register
End of enumeration elements list.
Set Enable Request Register
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SERQ : Set Enable Request
bits : 0 - 3 (4 bit)
access : read-write
SAER : Set All Enable Requests
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SAER_0
Set only the ERQ bit specified in the SERQ field
0x1 : SAER_1
Set all bits in ERQ
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOP_0
Normal operation
0x1 : NOP_1
No operation, ignore the other bits in this register
End of enumeration elements list.
Clear DONE Status Bit Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDNE : Clear DONE Bit
bits : 0 - 3 (4 bit)
access : read-write
CADN : Clears All DONE Bits
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CADN_0
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
0x1 : CADN_1
Clears all bits in TCDn_CSR[DONE]
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOP_0
Normal operation
0x1 : NOP_1
No operation, ignore the other bits in this register
End of enumeration elements list.
Set START Bit Register
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSRT : Set START Bit
bits : 0 - 3 (4 bit)
access : read-write
SAST : Set All START Bits (activates all channels)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SAST_0
Set only the TCDn_CSR[START] bit specified in the SSRT field
0x1 : SAST_1
Set all bits in TCDn_CSR[START]
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOP_0
Normal operation
0x1 : NOP_1
No operation, ignore the other bits in this register
End of enumeration elements list.
Clear Error Register
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CERR : Clear Error Indicator
bits : 0 - 3 (4 bit)
access : read-write
CAEI : Clear All Error Indicators
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CAEI_0
Clear only the ERR bit specified in the CERR field
0x1 : CAEI_1
Clear all bits in ERR
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOP_0
Normal operation
0x1 : NOP_1
No operation, ignore the other bits in this register
End of enumeration elements list.
Clear Interrupt Request Register
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CINT : Clear Interrupt Request
bits : 0 - 3 (4 bit)
access : read-write
CAIR : Clear All Interrupt Requests
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CAIR_0
Clear only the INT bit specified in the CINT field
0x1 : CAIR_1
Clear all bits in INT
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOP_0
Normal operation
0x1 : NOP_1
No operation, ignore the other bits in this register
End of enumeration elements list.
Interrupt Request Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT0 : Interrupt Request 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : INT0_0
The interrupt request for corresponding channel is cleared
0x1 : INT0_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT1 : Interrupt Request 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INT1_0
The interrupt request for corresponding channel is cleared
0x1 : INT1_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT2 : Interrupt Request 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INT2_0
The interrupt request for corresponding channel is cleared
0x1 : INT2_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT3 : Interrupt Request 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : INT3_0
The interrupt request for corresponding channel is cleared
0x1 : INT3_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT4 : Interrupt Request 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : INT4_0
The interrupt request for corresponding channel is cleared
0x1 : INT4_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT5 : Interrupt Request 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INT5_0
The interrupt request for corresponding channel is cleared
0x1 : INT5_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT6 : Interrupt Request 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : INT6_0
The interrupt request for corresponding channel is cleared
0x1 : INT6_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT7 : Interrupt Request 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : INT7_0
The interrupt request for corresponding channel is cleared
0x1 : INT7_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT8 : Interrupt Request 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INT8_0
The interrupt request for corresponding channel is cleared
0x1 : INT8_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT9 : Interrupt Request 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : INT9_0
The interrupt request for corresponding channel is cleared
0x1 : INT9_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT10 : Interrupt Request 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : INT10_0
The interrupt request for corresponding channel is cleared
0x1 : INT10_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT11 : Interrupt Request 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : INT11_0
The interrupt request for corresponding channel is cleared
0x1 : INT11_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT12 : Interrupt Request 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : INT12_0
The interrupt request for corresponding channel is cleared
0x1 : INT12_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT13 : Interrupt Request 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : INT13_0
The interrupt request for corresponding channel is cleared
0x1 : INT13_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT14 : Interrupt Request 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : INT14_0
The interrupt request for corresponding channel is cleared
0x1 : INT14_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT15 : Interrupt Request 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : INT15_0
The interrupt request for corresponding channel is cleared
0x1 : INT15_1
The interrupt request for corresponding channel is active
End of enumeration elements list.
Error Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR0 : Error In Channel 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ERR0_0
An error in this channel has not occurred
0x1 : ERR0_1
An error in this channel has occurred
End of enumeration elements list.
ERR1 : Error In Channel 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ERR1_0
An error in this channel has not occurred
0x1 : ERR1_1
An error in this channel has occurred
End of enumeration elements list.
ERR2 : Error In Channel 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ERR2_0
An error in this channel has not occurred
0x1 : ERR2_1
An error in this channel has occurred
End of enumeration elements list.
ERR3 : Error In Channel 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ERR3_0
An error in this channel has not occurred
0x1 : ERR3_1
An error in this channel has occurred
End of enumeration elements list.
ERR4 : Error In Channel 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ERR4_0
An error in this channel has not occurred
0x1 : ERR4_1
An error in this channel has occurred
End of enumeration elements list.
ERR5 : Error In Channel 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ERR5_0
An error in this channel has not occurred
0x1 : ERR5_1
An error in this channel has occurred
End of enumeration elements list.
ERR6 : Error In Channel 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : ERR6_0
An error in this channel has not occurred
0x1 : ERR6_1
An error in this channel has occurred
End of enumeration elements list.
ERR7 : Error In Channel 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ERR7_0
An error in this channel has not occurred
0x1 : ERR7_1
An error in this channel has occurred
End of enumeration elements list.
ERR8 : Error In Channel 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : ERR8_0
An error in this channel has not occurred
0x1 : ERR8_1
An error in this channel has occurred
End of enumeration elements list.
ERR9 : Error In Channel 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : ERR9_0
An error in this channel has not occurred
0x1 : ERR9_1
An error in this channel has occurred
End of enumeration elements list.
ERR10 : Error In Channel 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : ERR10_0
An error in this channel has not occurred
0x1 : ERR10_1
An error in this channel has occurred
End of enumeration elements list.
ERR11 : Error In Channel 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ERR11_0
An error in this channel has not occurred
0x1 : ERR11_1
An error in this channel has occurred
End of enumeration elements list.
ERR12 : Error In Channel 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : ERR12_0
An error in this channel has not occurred
0x1 : ERR12_1
An error in this channel has occurred
End of enumeration elements list.
ERR13 : Error In Channel 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : ERR13_0
An error in this channel has not occurred
0x1 : ERR13_1
An error in this channel has occurred
End of enumeration elements list.
ERR14 : Error In Channel 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ERR14_0
An error in this channel has not occurred
0x1 : ERR14_1
An error in this channel has occurred
End of enumeration elements list.
ERR15 : Error In Channel 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ERR15_0
An error in this channel has not occurred
0x1 : ERR15_1
An error in this channel has occurred
End of enumeration elements list.
Hardware Request Status Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HRS0 : Hardware Request Status Channel 0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : HRS0_0
A hardware service request for channel 0 is not present
0x1 : HRS0_1
A hardware service request for channel 0 is present
End of enumeration elements list.
HRS1 : Hardware Request Status Channel 1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : HRS1_0
A hardware service request for channel 1 is not present
0x1 : HRS1_1
A hardware service request for channel 1 is present
End of enumeration elements list.
HRS2 : Hardware Request Status Channel 2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : HRS2_0
A hardware service request for channel 2 is not present
0x1 : HRS2_1
A hardware service request for channel 2 is present
End of enumeration elements list.
HRS3 : Hardware Request Status Channel 3
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : HRS3_0
A hardware service request for channel 3 is not present
0x1 : HRS3_1
A hardware service request for channel 3 is present
End of enumeration elements list.
HRS4 : Hardware Request Status Channel 4
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : HRS4_0
A hardware service request for channel 4 is not present
0x1 : HRS4_1
A hardware service request for channel 4 is present
End of enumeration elements list.
HRS5 : Hardware Request Status Channel 5
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : HRS5_0
A hardware service request for channel 5 is not present
0x1 : HRS5_1
A hardware service request for channel 5 is present
End of enumeration elements list.
HRS6 : Hardware Request Status Channel 6
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : HRS6_0
A hardware service request for channel 6 is not present
0x1 : HRS6_1
A hardware service request for channel 6 is present
End of enumeration elements list.
HRS7 : Hardware Request Status Channel 7
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : HRS7_0
A hardware service request for channel 7 is not present
0x1 : HRS7_1
A hardware service request for channel 7 is present
End of enumeration elements list.
HRS8 : Hardware Request Status Channel 8
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : HRS8_0
A hardware service request for channel 8 is not present
0x1 : HRS8_1
A hardware service request for channel 8 is present
End of enumeration elements list.
HRS9 : Hardware Request Status Channel 9
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : HRS9_0
A hardware service request for channel 9 is not present
0x1 : HRS9_1
A hardware service request for channel 9 is present
End of enumeration elements list.
HRS10 : Hardware Request Status Channel 10
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : HRS10_0
A hardware service request for channel 10 is not present
0x1 : HRS10_1
A hardware service request for channel 10 is present
End of enumeration elements list.
HRS11 : Hardware Request Status Channel 11
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : HRS11_0
A hardware service request for channel 11 is not present
0x1 : HRS11_1
A hardware service request for channel 11 is present
End of enumeration elements list.
HRS12 : Hardware Request Status Channel 12
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : HRS12_0
A hardware service request for channel 12 is not present
0x1 : HRS12_1
A hardware service request for channel 12 is present
End of enumeration elements list.
HRS13 : Hardware Request Status Channel 13
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : HRS13_0
A hardware service request for channel 13 is not present
0x1 : HRS13_1
A hardware service request for channel 13 is present
End of enumeration elements list.
HRS14 : Hardware Request Status Channel 14
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : HRS14_0
A hardware service request for channel 14 is not present
0x1 : HRS14_1
A hardware service request for channel 14 is present
End of enumeration elements list.
HRS15 : Hardware Request Status Channel 15
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : HRS15_0
A hardware service request for channel 15 is not present
0x1 : HRS15_1
A hardware service request for channel 15 is present
End of enumeration elements list.
Error Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DBE : Destination Bus Error
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : DBE_0
No destination bus error
0x1 : DBE_1
The last recorded error was a bus error on a destination write
End of enumeration elements list.
SBE : Source Bus Error
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : SBE_0
No source bus error
0x1 : SBE_1
The last recorded error was a bus error on a source read
End of enumeration elements list.
SGE : Scatter/Gather Configuration Error
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SGE_0
No scatter/gather configuration error
0x1 : SGE_1
The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
End of enumeration elements list.
NCE : NBYTES/CITER Configuration Error
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NCE_0
No NBYTES/CITER configuration error
0x1 : NCE_1
The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
End of enumeration elements list.
DOE : Destination Offset Error
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : DOE_0
No destination offset configuration error
0x1 : DOE_1
The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
End of enumeration elements list.
DAE : Destination Address Error
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : DAE_0
No destination address configuration error
0x1 : DAE_1
The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
End of enumeration elements list.
SOE : Source Offset Error
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : SOE_0
No source offset configuration error
0x1 : SOE_1
The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
End of enumeration elements list.
SAE : Source Address Error
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : SAE_0
No source address configuration error.
0x1 : SAE_1
The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
End of enumeration elements list.
ERRCHN : Error Channel Number or Canceled Channel Number
bits : 8 - 11 (4 bit)
access : read-only
CPE : Channel Priority Error
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : CPE_0
No channel priority error
0x1 : CPE_1
The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
End of enumeration elements list.
ECX : Transfer Canceled
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : ECX_0
No canceled transfers
0x1 : ECX_1
The last recorded entry was a canceled transfer by the error cancel transfer input
End of enumeration elements list.
VLD : VLD
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : VLD_0
No ERR bits are set.
0x1 : VLD_1
At least one ERR bit is set indicating a valid error exists that has not been cleared.
End of enumeration elements list.
Enable Asynchronous Request in Stop Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDREQ_0 : Enable asynchronous DMA request in stop mode for channel 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_0_0
Disable asynchronous DMA request for channel 0.
0x1 : EDREQ_0_1
Enable asynchronous DMA request for channel 0.
End of enumeration elements list.
EDREQ_1 : Enable asynchronous DMA request in stop mode for channel 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_1_0
Disable asynchronous DMA request for channel 1
0x1 : EDREQ_1_1
Enable asynchronous DMA request for channel 1.
End of enumeration elements list.
EDREQ_2 : Enable asynchronous DMA request in stop mode for channel 2.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_2_0
Disable asynchronous DMA request for channel 2.
0x1 : EDREQ_2_1
Enable asynchronous DMA request for channel 2.
End of enumeration elements list.
EDREQ_3 : Enable asynchronous DMA request in stop mode for channel 3.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_3_0
Disable asynchronous DMA request for channel 3.
0x1 : EDREQ_3_1
Enable asynchronous DMA request for channel 3.
End of enumeration elements list.
EDREQ_4 : Enable asynchronous DMA request in stop mode for channel 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_4_0
Disable asynchronous DMA request for channel 4.
0x1 : EDREQ_4_1
Enable asynchronous DMA request for channel 4.
End of enumeration elements list.
EDREQ_5 : Enable asynchronous DMA request in stop mode for channel 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_5_0
Disable asynchronous DMA request for channel 5.
0x1 : EDREQ_5_1
Enable asynchronous DMA request for channel 5.
End of enumeration elements list.
EDREQ_6 : Enable asynchronous DMA request in stop mode for channel 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_6_0
Disable asynchronous DMA request for channel 6.
0x1 : EDREQ_6_1
Enable asynchronous DMA request for channel 6.
End of enumeration elements list.
EDREQ_7 : Enable asynchronous DMA request in stop mode for channel 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_7_0
Disable asynchronous DMA request for channel 7.
0x1 : EDREQ_7_1
Enable asynchronous DMA request for channel 7.
End of enumeration elements list.
EDREQ_8 : Enable asynchronous DMA request in stop mode for channel 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_8_0
Disable asynchronous DMA request for channel 8.
0x1 : EDREQ_8_1
Enable asynchronous DMA request for channel 8.
End of enumeration elements list.
EDREQ_9 : Enable asynchronous DMA request in stop mode for channel 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_9_0
Disable asynchronous DMA request for channel 9.
0x1 : EDREQ_9_1
Enable asynchronous DMA request for channel 9.
End of enumeration elements list.
EDREQ_10 : Enable asynchronous DMA request in stop mode for channel 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_10_0
Disable asynchronous DMA request for channel 10.
0x1 : EDREQ_10_1
Enable asynchronous DMA request for channel 10.
End of enumeration elements list.
EDREQ_11 : Enable asynchronous DMA request in stop mode for channel 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_11_0
Disable asynchronous DMA request for channel 11.
0x1 : EDREQ_11_1
Enable asynchronous DMA request for channel 11.
End of enumeration elements list.
EDREQ_12 : Enable asynchronous DMA request in stop mode for channel 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_12_0
Disable asynchronous DMA request for channel 12.
0x1 : EDREQ_12_1
Enable asynchronous DMA request for channel 12.
End of enumeration elements list.
EDREQ_13 : Enable asynchronous DMA request in stop mode for channel 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_13_0
Disable asynchronous DMA request for channel 13.
0x1 : EDREQ_13_1
Enable asynchronous DMA request for channel 13.
End of enumeration elements list.
EDREQ_14 : Enable asynchronous DMA request in stop mode for channel 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_14_0
Disable asynchronous DMA request for channel 14.
0x1 : EDREQ_14_1
Enable asynchronous DMA request for channel 14.
End of enumeration elements list.
EDREQ_15 : Enable asynchronous DMA request in stop mode for channel 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : EDREQ_15_0
Disable asynchronous DMA request for channel 15.
0x1 : EDREQ_15_1
Enable asynchronous DMA request for channel 15.
End of enumeration elements list.
Enable Request Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERQ0 : Enable DMA Request 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ERQ0_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ0_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ1 : Enable DMA Request 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ERQ1_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ1_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ2 : Enable DMA Request 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ERQ2_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ2_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ3 : Enable DMA Request 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ERQ3_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ3_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ4 : Enable DMA Request 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ERQ4_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ4_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ5 : Enable DMA Request 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ERQ5_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ5_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ6 : Enable DMA Request 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : ERQ6_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ6_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ7 : Enable DMA Request 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ERQ7_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ7_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ8 : Enable DMA Request 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : ERQ8_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ8_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ9 : Enable DMA Request 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : ERQ9_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ9_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ10 : Enable DMA Request 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : ERQ10_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ10_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ11 : Enable DMA Request 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ERQ11_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ11_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ12 : Enable DMA Request 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : ERQ12_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ12_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ13 : Enable DMA Request 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : ERQ13_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ13_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ14 : Enable DMA Request 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ERQ14_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ14_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ15 : Enable DMA Request 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ERQ15_0
The DMA request signal for the corresponding channel is disabled
0x1 : ERQ15_1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
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