Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x78 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Module Identification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0x4 : FEATURE_4
Standard feature set supporting a 32-bit shift register.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEN : Module Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEN_0
Module is disabled
0x1 : MEN_1
Module is enabled
End of enumeration elements list.
RST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RST_0
Module is not reset
0x1 : RST_1
Module is reset
End of enumeration elements list.
DOZEN : Doze Mode Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DOZEN_0
LPSPI module is enabled in Doze mode
0x1 : DOZEN_1
LPSPI module is disabled in Doze mode
End of enumeration elements list.
DBGEN : Debug Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DBGEN_0
LPSPI module is disabled in debug mode
0x1 : DBGEN_1
LPSPI module is enabled in debug mode
End of enumeration elements list.
RTF : Reset Transmit FIFO
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
0 : RTF_0
No effect
0x1 : RTF_1
Transmit FIFO is reset
End of enumeration elements list.
RRF : Reset Receive FIFO
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
0 : RRF_0
No effect
0x1 : RRF_1
Receive FIFO is reset
End of enumeration elements list.
Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDF : Transmit Data Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : TDF_0
Transmit data not requested
0x1 : TDF_1
Transmit data is requested
End of enumeration elements list.
RDF : Receive Data Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : RDF_0
Receive Data is not ready
0x1 : RDF_1
Receive data is ready
End of enumeration elements list.
WCF : Word Complete Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WCF_0
Transfer of a received word has not yet completed
0x1 : WCF_1
Transfer of a received word has completed
End of enumeration elements list.
FCF : Frame Complete Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : FCF_0
Frame transfer has not completed
0x1 : FCF_1
Frame transfer has completed
End of enumeration elements list.
TCF : Transfer Complete Flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : TCF_0
All transfers have not completed
0x1 : TCF_1
All transfers have completed
End of enumeration elements list.
TEF : Transmit Error Flag
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : TEF_0
Transmit FIFO underrun has not occurred
0x1 : TEF_1
Transmit FIFO underrun has occurred
End of enumeration elements list.
REF : Receive Error Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : REF_0
Receive FIFO has not overflowed
0x1 : REF_1
Receive FIFO has overflowed
End of enumeration elements list.
DMF : Data Match Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DMF_0
Have not received matching data
0x1 : DMF_1
Have received matching data
End of enumeration elements list.
MBF : Module Busy Flag
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : MBF_0
LPSPI is idle
0x1 : MBF_1
LPSPI is busy
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIE : Transmit Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDIE_0
Disabled
0x1 : TDIE_1
Enabled
End of enumeration elements list.
RDIE : Receive Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RDIE_0
Disabled
0x1 : RDIE_1
Enabled
End of enumeration elements list.
WCIE : Word Complete Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WCIE_0
Disabled
0x1 : WCIE_1
Enabled
End of enumeration elements list.
FCIE : Frame Complete Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : FCIE_0
Disabled
0x1 : FCIE_1
Enabled
End of enumeration elements list.
TCIE : Transfer Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : TCIE_0
Disabled
0x1 : TCIE_1
Enabled
End of enumeration elements list.
TEIE : Transmit Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : TEIE_0
Disabled
0x1 : TEIE_1
Enabled
End of enumeration elements list.
REIE : Receive Error Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : REIE_0
Disabled
0x1 : REIE_1
Enabled
End of enumeration elements list.
DMIE : Data Match Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DMIE_0
Disabled
0x1 : DMIE_1
Enabled
End of enumeration elements list.
DMA Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDDE : Transmit Data DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDDE_0
DMA request is disabled
0x1 : TDDE_1
DMA request is enabled
End of enumeration elements list.
RDDE : Receive Data DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RDDE_0
DMA request is disabled
0x1 : RDDE_1
DMA request is enabled
End of enumeration elements list.
Configuration Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HREN : Host Request Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HREN_0
Host request is disabled
0x1 : HREN_1
Host request is enabled
End of enumeration elements list.
HRPOL : Host Request Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HRPOL_0
Active low
0x1 : HRPOL_1
Active high
End of enumeration elements list.
HRSEL : Host Request Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : HRSEL_0
Host request input is the LPSPI_HREQ pin
0x1 : HRSEL_1
Host request input is the input trigger
End of enumeration elements list.
CIRFIFO : Circular FIFO Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CIRFIFO_0
Circular FIFO is disabled
0x1 : CIRFIFO_1
Circular FIFO is enabled
End of enumeration elements list.
RDMO : Receive Data Match Only
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RDMO_0
Received data is stored in the receive FIFO as in normal operations
0x1 : RDMO_1
Received data is discarded unless the Data Match Flag (DMF) is set
End of enumeration elements list.
Configuration Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASTER : Master Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MASTER_0
Slave mode
0x1 : MASTER_1
Master mode
End of enumeration elements list.
SAMPLE : Sample Point
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SAMPLE_0
Input data is sampled on SCK edge
0x1 : SAMPLE_1
Input data is sampled on delayed SCK edge
End of enumeration elements list.
AUTOPCS : Automatic PCS
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : AUTOPCS_0
Automatic PCS generation is disabled
0x1 : AUTOPCS_1
Automatic PCS generation is enabled
End of enumeration elements list.
NOSTALL : No Stall
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOSTALL_0
Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
0x1 : NOSTALL_1
Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
End of enumeration elements list.
PCSPOL : Peripheral Chip Select Polarity
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : PCSPOL_0
The Peripheral Chip Select pin PCSx is active low
0x1 : PCSPOL_1
The Peripheral Chip Select pin PCSx is active high
End of enumeration elements list.
MATCFG : Match Configuration
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : MATCFG_0
Match is disabled
0x2 : MATCFG_2
010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
0x3 : MATCFG_3
011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
0x4 : MATCFG_4
100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]
0x5 : MATCFG_5
101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]
0x6 : MATCFG_6
110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
0x7 : MATCFG_7
111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
End of enumeration elements list.
PINCFG : Pin Configuration
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
SIN is used for input data and SOUT is used for output data
0x1 : PINCFG_1
SIN is used for both input and output data
0x2 : PINCFG_2
SOUT is used for both input and output data
0x3 : PINCFG_3
SOUT is used for input data and SIN is used for output data
End of enumeration elements list.
OUTCFG : Output Config
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : OUTCFG_0
Output data retains last value when chip select is negated
0x1 : OUTCFG_1
Output data is tristated when chip select is negated
End of enumeration elements list.
PCSCFG : Peripheral Chip Select Configuration
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : PCSCFG_0
PCS[3:2] are enabled
0x1 : PCSCFG_1
PCS[3:2] are disabled
End of enumeration elements list.
Data Match Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH0 : Match 0 Value
bits : 0 - 31 (32 bit)
access : read-write
Data Match Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH1 : Match 1 Value
bits : 0 - 31 (32 bit)
access : read-write
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFIFO : Transmit FIFO Size
bits : 0 - 7 (8 bit)
access : read-only
RXFIFO : Receive FIFO Size
bits : 8 - 15 (8 bit)
access : read-only
PCSNUM : PCS Number
bits : 16 - 23 (8 bit)
access : read-only
Clock Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCKDIV : SCK Divider
bits : 0 - 7 (8 bit)
access : read-write
DBT : Delay Between Transfers
bits : 8 - 15 (8 bit)
access : read-write
PCSSCK : PCS-to-SCK Delay
bits : 16 - 23 (8 bit)
access : read-write
SCKPCS : SCK-to-PCS Delay
bits : 24 - 31 (8 bit)
access : read-write
FIFO Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXWATER : Transmit FIFO Watermark
bits : 0 - 3 (4 bit)
access : read-write
RXWATER : Receive FIFO Watermark
bits : 16 - 19 (4 bit)
access : read-write
FIFO Status Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCOUNT : Transmit FIFO Count
bits : 0 - 4 (5 bit)
access : read-only
RXCOUNT : Receive FIFO Count
bits : 16 - 20 (5 bit)
access : read-only
Transmit Command Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAMESZ : Frame Size
bits : 0 - 11 (12 bit)
access : read-write
WIDTH : Transfer Width
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WIDTH_0
1 bit transfer
0x1 : WIDTH_1
2 bit transfer
0x2 : WIDTH_2
4 bit transfer
End of enumeration elements list.
TXMSK : Transmit Data Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : TXMSK_0
Normal transfer
0x1 : TXMSK_1
Mask transmit data
End of enumeration elements list.
RXMSK : Receive Data Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : RXMSK_0
Normal transfer
0x1 : RXMSK_1
Receive data is masked
End of enumeration elements list.
CONTC : Continuing Command
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : CONTC_0
Command word for start of new transfer
0x1 : CONTC_1
Command word for continuing transfer
End of enumeration elements list.
CONT : Continuous Transfer
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : CONT_0
Continuous transfer is disabled
0x1 : CONT_1
Continuous transfer is enabled
End of enumeration elements list.
BYSW : Byte Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : BYSW_0
Byte swap is disabled
0x1 : BYSW_1
Byte swap is enabled
End of enumeration elements list.
LSBF : LSB First
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : LSBF_0
Data is transferred MSB first
0x1 : LSBF_1
Data is transferred LSB first
End of enumeration elements list.
PCS : Peripheral Chip Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PCS_0
Transfer using LPSPI_PCS[0]
0x1 : PCS_1
Transfer using LPSPI_PCS[1]
0x2 : PCS_2
Transfer using LPSPI_PCS[2]
0x3 : PCS_3
Transfer using LPSPI_PCS[3]
End of enumeration elements list.
PRESCALE : Prescaler Value
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
0 : PRESCALE_0
Divide by 1
0x1 : PRESCALE_1
Divide by 2
0x2 : PRESCALE_2
Divide by 4
0x3 : PRESCALE_3
Divide by 8
0x4 : PRESCALE_4
Divide by 16
0x5 : PRESCALE_5
Divide by 32
0x6 : PRESCALE_6
Divide by 64
0x7 : PRESCALE_7
Divide by 128
End of enumeration elements list.
CPHA : Clock Phase
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CPHA_0
Data is captured on the leading edge of SCK and changed on the following edge of SCK
0x1 : CPHA_1
Data is changed on the leading edge of SCK and captured on the following edge of SCK
End of enumeration elements list.
CPOL : Clock Polarity
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : CPOL_0
The inactive state value of SCK is low
0x1 : CPOL_1
The inactive state value of SCK is high
End of enumeration elements list.
Transmit Data Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit Data
bits : 0 - 31 (32 bit)
access : write-only
Receive Status Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF : Start Of Frame
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : SOF_0
Subsequent data word received after LPSPI_PCS assertion
0x1 : SOF_1
First data word received after LPSPI_PCS assertion
End of enumeration elements list.
RXEMPTY : RX FIFO Empty
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : RXEMPTY_0
RX FIFO is not empty
0x1 : RXEMPTY_1
RX FIFO is empty
End of enumeration elements list.
Receive Data Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.