Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
GPT Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : GPT Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_0
GPT is disabled.
0x1 : EN_1
GPT is enabled.
End of enumeration elements list.
ENMOD : GPT Enable mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ENMOD_0
GPT counter will retain its value when it is disabled.
0x1 : ENMOD_1
GPT counter value is reset to 0 when it is disabled.
End of enumeration elements list.
DBGEN : GPT debug mode enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DBGEN_0
GPT is disabled in debug mode.
0x1 : DBGEN_1
GPT is enabled in debug mode.
End of enumeration elements list.
WAITEN : GPT Wait Mode enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : WAITEN_0
GPT is disabled in wait mode.
0x1 : WAITEN_1
GPT is enabled in wait mode.
End of enumeration elements list.
DOZEEN : GPT Doze Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DOZEEN_0
GPT is disabled in doze mode.
0x1 : DOZEEN_1
GPT is enabled in doze mode.
End of enumeration elements list.
STOPEN : GPT Stop Mode enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : STOPEN_0
GPT is disabled in Stop mode.
0x1 : STOPEN_1
GPT is enabled in Stop mode.
End of enumeration elements list.
CLKSRC : Clock Source select
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : CLKSRC_0
No clock
0x1 : CLKSRC_1
Peripheral Clock (ipg_clk)
0x2 : CLKSRC_2
High Frequency Reference Clock (ipg_clk_highfreq)
0x3 : CLKSRC_3
External Clock
0x4 : CLKSRC_4
Low Frequency Reference Clock (ipg_clk_32k)
0x5 : CLKSRC_5
Crystal oscillator as Reference Clock (ipg_clk_24M)
End of enumeration elements list.
FRR : Free-Run or Restart mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : FRR_0
Restart mode
0x1 : FRR_1
Free-Run mode
End of enumeration elements list.
EN_24M : Enable 24 MHz clock input from crystal
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : EN_24M_0
24M clock disabled
0x1 : EN_24M_1
24M clock enabled
End of enumeration elements list.
SWR : Software reset
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SWR_0
GPT is not in reset state
0x1 : SWR_1
GPT is in reset state
End of enumeration elements list.
IM1 : See IM2
bits : 16 - 17 (2 bit)
access : read-write
IM2 : IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : IM2_0
capture disabled
0x1 : IM2_1
capture on rising edge only
0x2 : IM2_2
capture on falling edge only
0x3 : IM2_3
capture on both edges
End of enumeration elements list.
OM1 : See OM3
bits : 20 - 22 (3 bit)
access : read-write
OM2 : See OM3
bits : 23 - 25 (3 bit)
access : read-write
OM3 : OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : OM3_0
Output disconnected. No response on pin.
0x1 : OM3_1
Toggle output pin
0x2 : OM3_2
Clear output pin
0x3 : OM3_3
Set output pin
#1xx : OM3_4
Generate an active low pulse (that is one input clock wide) on the output pin.
End of enumeration elements list.
FO1 : See F03
bits : 29 - 29 (1 bit)
access : read-write
FO2 : See F03
bits : 30 - 30 (1 bit)
access : read-write
FO3 : FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : FO3_0
Writing a 0 has no effect.
0x1 : FO3_1
Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
End of enumeration elements list.
GPT Output Compare Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Compare Value
bits : 0 - 31 (32 bit)
access : read-write
GPT Output Compare Register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Compare Value
bits : 0 - 31 (32 bit)
access : read-write
GPT Output Compare Register 3
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Compare Value
bits : 0 - 31 (32 bit)
access : read-write
GPT Input Capture Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPT : Capture Value
bits : 0 - 31 (32 bit)
access : read-only
GPT Input Capture Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPT : Capture Value
bits : 0 - 31 (32 bit)
access : read-only
GPT Counter Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value. The COUNT bits show the current count value of the GPT counter.
bits : 0 - 31 (32 bit)
access : read-only
GPT Prescaler Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALER : Prescaler bits
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
0 : PRESCALER_0
Divide by 1
0x1 : PRESCALER_1
Divide by 2
0xFFF : PRESCALER_4095
Divide by 4096
End of enumeration elements list.
PRESCALER24M : Prescaler bits
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : PRESCALER24M_0
Divide by 1
0x1 : PRESCALER24M_1
Divide by 2
0xF : PRESCALER24M_15
Divide by 16
End of enumeration elements list.
GPT Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OF1 : See OF3
bits : 0 - 0 (1 bit)
access : read-write
OF2 : See OF3
bits : 1 - 1 (1 bit)
access : read-write
OF3 : OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : OF3_0
Compare event has not occurred.
0x1 : OF3_1
Compare event has occurred.
End of enumeration elements list.
IF1 : See IF2
bits : 3 - 3 (1 bit)
access : read-write
IF2 : IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : IF2_0
Capture event has not occurred.
0x1 : IF2_1
Capture event has occurred.
End of enumeration elements list.
ROV : Rollover Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ROV_0
Rollover has not occurred.
0x1 : ROV_1
Rollover has occurred.
End of enumeration elements list.
GPT Interrupt Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OF1IE : See OF3IE
bits : 0 - 0 (1 bit)
access : read-write
OF2IE : See OF3IE
bits : 1 - 1 (1 bit)
access : read-write
OF3IE : OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : OF3IE_0
Output Compare Channel n interrupt is disabled.
0x1 : OF3IE_1
Output Compare Channel n interrupt is enabled.
End of enumeration elements list.
IF1IE : See IF2IE
bits : 3 - 3 (1 bit)
access : read-write
IF2IE : IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : IF2IE_0
IF2IE Input Capture n Interrupt Enable is disabled.
0x1 : IF2IE_1
IF2IE Input Capture n Interrupt Enable is enabled.
End of enumeration elements list.
ROVIE : Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ROVIE_0
Rollover interrupt is disabled.
0x1 : ROVIE_1
Rollover interrupt enabled.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.