Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x68 byte (0x0)
mem_usage : registers
protection : not protected
GPR0 General Purpose Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR4 General Purpose Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDMA_STOP_REQ : EDMA stop request.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EDMA_STOP_REQ_0
stop request off
0x1 : EDMA_STOP_REQ_1
stop request on
End of enumeration elements list.
TRNG_STOP_REQ : TRNG stop request.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TRNG_STOP_REQ_0
stop request off
0x1 : TRNG_STOP_REQ_1
stop request on
End of enumeration elements list.
SAI1_STOP_REQ : SAI1 stop request.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SAI1_STOP_REQ_0
stop request off
0x1 : SAI1_STOP_REQ_1
stop request on
End of enumeration elements list.
SAI2_STOP_REQ : SAI2 stop request.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SAI2_STOP_REQ_0
stop request off
0x1 : SAI2_STOP_REQ_1
stop request on
End of enumeration elements list.
SAI3_STOP_REQ : SAI3 stop request.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SAI3_STOP_REQ_0
stop request off
0x1 : SAI3_STOP_REQ_1
stop request on
End of enumeration elements list.
PIT_STOP_REQ : PIT stop request.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : PIT_STOP_REQ_0
stop request off
0x1 : PIT_STOP_REQ_1
stop request on
End of enumeration elements list.
FLEXSPI_STOP_REQ : FlexSPI stop request.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : FLEXSPI_STOP_REQ_0
stop request off
0x1 : FLEXSPI_STOP_REQ_1
stop request on
End of enumeration elements list.
FLEXIO1_STOP_REQ : FlexIO1 stop request.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : FLEXIO1_STOP_REQ_0
stop request off
0x1 : FLEXIO1_STOP_REQ_1
stop request on
End of enumeration elements list.
EDMA_STOP_ACK : EDMA stop acknowledge. This is a status (read-only) bit
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : EDMA_STOP_ACK_0
EDMA stop acknowledge is not asserted
0x1 : EDMA_STOP_ACK_1
EDMA stop acknowledge is asserted (EDMA is in STOP mode).
End of enumeration elements list.
TRNG_STOP_ACK : TRNG stop acknowledge
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : TRNG_STOP_ACK_0
TRNG stop acknowledge is not asserted
0x1 : TRNG_STOP_ACK_1
TRNG stop acknowledge is asserted
End of enumeration elements list.
SAI1_STOP_ACK : SAI1 stop acknowledge
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : SAI1_STOP_ACK_0
SAI1 stop acknowledge is not asserted
0x1 : SAI1_STOP_ACK_1
SAI1 stop acknowledge is asserted
End of enumeration elements list.
SAI2_STOP_ACK : SAI2 stop acknowledge
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : SAI2_STOP_ACK_0
SAI2 stop acknowledge is not asserted
0x1 : SAI2_STOP_ACK_1
SAI2 stop acknowledge is asserted
End of enumeration elements list.
SAI3_STOP_ACK : SAI3 stop acknowledge
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : SAI3_STOP_ACK_0
SAI3 stop acknowledge is not asserted
0x1 : SAI3_STOP_ACK_1
SAI3 stop acknowledge is asserted
End of enumeration elements list.
PIT_STOP_ACK : PIT stop acknowledge
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : PIT_STOP_ACK_0
PIT stop acknowledge is not asserted
0x1 : PIT_STOP_ACK_1
PIT stop acknowledge is asserted
End of enumeration elements list.
FLEXSPI_STOP_ACK : FLEXSPI stop acknowledge
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : FLEXSPI_STOP_ACK_0
FLEXSPI stop acknowledge is not asserted
0x1 : FLEXSPI_STOP_ACK_1
FLEXSPI stop acknowledge is asserted
End of enumeration elements list.
FLEXIO1_STOP_ACK : FLEXIO1 stop acknowledge
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : FLEXIO1_STOP_ACK_0
FLEXIO1 stop acknowledge is not asserted
0x1 : FLEXIO1_STOP_ACK_1
FLEXIO1 stop acknowledge is asserted
End of enumeration elements list.
GPR5 General Purpose Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDOG1_MASK : WDOG1 Timeout Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : WDOG1_MASK_0
WDOG1 Timeout behaves normally
0x1 : WDOG1_MASK_1
WDOG1 Timeout is masked
End of enumeration elements list.
WDOG2_MASK : WDOG2 Timeout Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : WDOG2_MASK_0
WDOG2 Timeout behaves normally
0x1 : WDOG2_MASK_1
WDOG2 Timeout is masked
End of enumeration elements list.
GPT2_CAPIN1_SEL : GPT2 input capture channel 1 source select
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : GPT2_CAPIN1_SEL_0
source from GPT2_CAPTURE1
0x1 : GPT2_CAPIN1_SEL_1
source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)
End of enumeration elements list.
VREF_1M_CLK_GPT1 : GPT1 1 MHz clock source select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : VREF_1M_CLK_GPT1_0
GPT1 ipg_clk_highfreq driven by IPG_PERCLK
0x1 : VREF_1M_CLK_GPT1_1
GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock
End of enumeration elements list.
VREF_1M_CLK_GPT2 : GPT2 1 MHz clock source select
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : VREF_1M_CLK_GPT2_0
GPT2 ipg_clk_highfreq driven by IPG_PERCLK
0x1 : VREF_1M_CLK_GPT2_1
GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock
End of enumeration elements list.
GPR6 General Purpose Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QTIMER1_TRM0_INPUT_SEL : QTIMER1 TMR0 input select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : QTIMER1_TRM0_INPUT_SEL_0
input from IOMUX
0x1 : QTIMER1_TRM0_INPUT_SEL_1
input from XBAR
End of enumeration elements list.
QTIMER1_TRM1_INPUT_SEL : QTIMER1 TMR1 input select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : QTIMER1_TRM1_INPUT_SEL_0
input from IOMUX
0x1 : QTIMER1_TRM1_INPUT_SEL_1
input from XBAR
End of enumeration elements list.
QTIMER1_TRM2_INPUT_SEL : QTIMER1 TMR2 input select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : QTIMER1_TRM2_INPUT_SEL_0
input from IOMUX
0x1 : QTIMER1_TRM2_INPUT_SEL_1
input from XBAR
End of enumeration elements list.
QTIMER1_TRM3_INPUT_SEL : QTIMER1 TMR3 input select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : QTIMER1_TRM3_INPUT_SEL_0
input from IOMUX
0x1 : QTIMER1_TRM3_INPUT_SEL_1
input from XBAR
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_4 : IOMUXC XBAR_INOUT4 function direction select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_4_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_4_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_5 : IOMUXC XBAR_INOUT5 function direction select
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_5_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_5_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_6 : IOMUXC XBAR_INOUT6 function direction select
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_6_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_6_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_7 : IOMUXC XBAR_INOUT7 function direction select
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_7_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_7_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_8 : IOMUXC XBAR_INOUT8 function direction select
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_8_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_8_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_9 : IOMUXC XBAR_INOUT9 function direction select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_9_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_9_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_10 : IOMUXC XBAR_INOUT10 function direction select
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_10_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_10_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_11 : IOMUXC XBAR_INOUT11 function direction select
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_11_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_11_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_12 : IOMUXC XBAR_INOUT12 function direction select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_12_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_12_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_13 : IOMUXC XBAR_INOUT13 function direction select
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_13_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_13_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_14 : IOMUXC XBAR_INOUT14 function direction select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_14_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_14_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_15 : IOMUXC XBAR_INOUT15 function direction select
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_15_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_15_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_16 : IOMUXC XBAR_INOUT16 function direction select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_16_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_16_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_17 : IOMUXC XBAR_INOUT17 function direction select
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_17_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_17_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_18 : IOMUXC XBAR_INOUT18 function direction select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_18_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_18_1
XBAR_INOUT as output
End of enumeration elements list.
IOMUXC_XBAR_DIR_SEL_19 : IOMUXC XBAR_INOUT19 function direction select
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : IOMUXC_XBAR_DIR_SEL_19_0
XBAR_INOUT as input
0x1 : IOMUXC_XBAR_DIR_SEL_19_1
XBAR_INOUT as output
End of enumeration elements list.
GPR7 General Purpose Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPI2C1_STOP_REQ : LPI2C1 stop request
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LPI2C1_STOP_REQ_0
stop request off
0x1 : LPI2C1_STOP_REQ_1
stop request on
End of enumeration elements list.
LPI2C2_STOP_REQ : LPI2C2 stop request
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : LPI2C2_STOP_REQ_0
stop request off
0x1 : LPI2C2_STOP_REQ_1
stop request on
End of enumeration elements list.
LPSPI1_STOP_REQ : LPSPI1 stop request
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : LPSPI1_STOP_REQ_0
stop request off
0x1 : LPSPI1_STOP_REQ_1
stop request on
End of enumeration elements list.
LPSPI2_STOP_REQ : LPSPI2 stop request
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPSPI2_STOP_REQ_0
stop request off
0x1 : LPSPI2_STOP_REQ_1
stop request on
End of enumeration elements list.
LPUART1_STOP_REQ : LPUART1 stop request
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LPUART1_STOP_REQ_0
stop request off
0x1 : LPUART1_STOP_REQ_1
stop request on
End of enumeration elements list.
LPUART2_STOP_REQ : LPUART1 stop request
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : LPUART2_STOP_REQ_0
stop request off
0x1 : LPUART2_STOP_REQ_1
stop request on
End of enumeration elements list.
LPUART3_STOP_REQ : LPUART3 stop request
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : LPUART3_STOP_REQ_0
stop request off
0x1 : LPUART3_STOP_REQ_1
stop request on
End of enumeration elements list.
LPUART4_STOP_REQ : LPUART4 stop request
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : LPUART4_STOP_REQ_0
stop request off
0x1 : LPUART4_STOP_REQ_1
stop request on
End of enumeration elements list.
LPI2C1_STOP_ACK : LPI2C1 stop acknowledge
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : LPI2C1_STOP_ACK_0
stop acknowledge is not asserted
0x1 : LPI2C1_STOP_ACK_1
stop acknowledge is asserted (the module is in Stop mode)
End of enumeration elements list.
LPI2C2_STOP_ACK : LPI2C2 stop acknowledge
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : LPI2C2_STOP_ACK_0
stop acknowledge is not asserted
0x1 : LPI2C2_STOP_ACK_1
stop acknowledge is asserted
End of enumeration elements list.
LPSPI1_STOP_ACK : LPSPI1 stop acknowledge
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : LPSPI1_STOP_ACK_0
stop acknowledge is not asserted
0x1 : LPSPI1_STOP_ACK_1
stop acknowledge is asserted
End of enumeration elements list.
LPSPI2_STOP_ACK : LPSPI2 stop acknowledge
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : LPSPI2_STOP_ACK_0
stop acknowledge is not asserted
0x1 : LPSPI2_STOP_ACK_1
stop acknowledge is asserted
End of enumeration elements list.
LPUART1_STOP_ACK : LPUART1 stop acknowledge
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : LPUART1_STOP_ACK_0
stop acknowledge is not asserted
0x1 : LPUART1_STOP_ACK_1
stop acknowledge is asserted
End of enumeration elements list.
LPUART2_STOP_ACK : LPUART1 stop acknowledge
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : LPUART2_STOP_ACK_0
stop acknowledge is not asserted
0x1 : LPUART2_STOP_ACK_1
stop acknowledge is asserted
End of enumeration elements list.
LPUART3_STOP_ACK : LPUART3 stop acknowledge
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : LPUART3_STOP_ACK_0
stop acknowledge is not asserted
0x1 : LPUART3_STOP_ACK_1
stop acknowledge is asserted
End of enumeration elements list.
LPUART4_STOP_ACK : LPUART4 stop acknowledge
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : LPUART4_STOP_ACK_0
stop acknowledge is not asserted
0x1 : LPUART4_STOP_ACK_1
stop acknowledge is asserted
End of enumeration elements list.
GPR8 General Purpose Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPI2C1_IPG_STOP_MODE : LPI2C1 stop mode selection, cannot change when ipg_stop is asserted.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LPI2C1_IPG_STOP_MODE_0
the module is functional in Stop mode
0x1 : LPI2C1_IPG_STOP_MODE_1
the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
End of enumeration elements list.
LPI2C1_IPG_DOZE : LPI2C1 ipg_doze mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : LPI2C1_IPG_DOZE_0
not in doze mode
0x1 : LPI2C1_IPG_DOZE_1
in doze mode
End of enumeration elements list.
LPI2C2_IPG_STOP_MODE : LPI2C2 stop mode selection, cannot change when ipg_stop is asserted.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LPI2C2_IPG_STOP_MODE_0
the module is functional in Stop mode
0x1 : LPI2C2_IPG_STOP_MODE_1
the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
End of enumeration elements list.
LPI2C2_IPG_DOZE : LPI2C2 ipg_doze mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : LPI2C2_IPG_DOZE_0
not in doze mode
0x1 : LPI2C2_IPG_DOZE_1
in doze mode
End of enumeration elements list.
LPSPI1_IPG_STOP_MODE : LPSPI1 stop mode selection, cannot change when ipg_stop is asserted.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LPSPI1_IPG_STOP_MODE_0
the module is functional in Stop mode
0x1 : LPSPI1_IPG_STOP_MODE_1
the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
End of enumeration elements list.
LPSPI1_IPG_DOZE : LPSPI1 ipg_doze mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : LPSPI1_IPG_DOZE_0
not in doze mode
0x1 : LPSPI1_IPG_DOZE_1
in doze mode
End of enumeration elements list.
LPSPI2_IPG_STOP_MODE : LPSPI2 stop mode selection, cannot change when ipg_stop is asserted.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : LPSPI2_IPG_STOP_MODE_0
the module is functional in Stop mode
0x1 : LPSPI2_IPG_STOP_MODE_1
the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
End of enumeration elements list.
LPSPI2_IPG_DOZE : LPSPI2 ipg_doze mode
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : LPSPI2_IPG_DOZE_0
not in doze mode
0x1 : LPSPI2_IPG_DOZE_1
in doze mode
End of enumeration elements list.
LPUART1_IPG_STOP_MODE : LPUART1 stop mode selection, cannot change when ipg_stop is asserted.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : LPUART1_IPG_STOP_MODE_0
the module is functional in Stop mode
0x1 : LPUART1_IPG_STOP_MODE_1
the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
End of enumeration elements list.
LPUART1_IPG_DOZE : LPUART1 ipg_doze mode
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : LPUART1_IPG_DOZE_0
not in doze mode
0x1 : LPUART1_IPG_DOZE_1
in doze mode
End of enumeration elements list.
LPUART2_IPG_STOP_MODE : LPUART2 stop mode selection, cannot change when ipg_stop is asserted.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : LPUART2_IPG_STOP_MODE_0
the module is functional in Stop mode
0x1 : LPUART2_IPG_STOP_MODE_1
the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
End of enumeration elements list.
LPUART2_IPG_DOZE : LPUART2 ipg_doze mode
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : LPUART2_IPG_DOZE_0
not in doze mode
0x1 : LPUART2_IPG_DOZE_1
in doze mode
End of enumeration elements list.
LPUART3_IPG_STOP_MODE : LPUART3 stop mode selection, cannot change when ipg_stop is asserted.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : LPUART3_IPG_STOP_MODE_0
the module is functional in Stop mode
0x1 : LPUART3_IPG_STOP_MODE_1
the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
End of enumeration elements list.
LPUART3_IPG_DOZE : LPUART3 ipg_doze mode
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : LPUART3_IPG_DOZE_0
not in doze mode
0x1 : LPUART3_IPG_DOZE_1
in doze mode
End of enumeration elements list.
LPUART4_IPG_STOP_MODE : LPUART4 stop mode selection, cannot change when ipg_stop is asserted.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : LPUART4_IPG_STOP_MODE_0
the module is functional in Stop mode
0x1 : LPUART4_IPG_STOP_MODE_1
the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
End of enumeration elements list.
LPUART4_IPG_DOZE : LPUART4 ipg_doze mode
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : LPUART4_IPG_DOZE_0
not in doze mode
0x1 : LPUART4_IPG_DOZE_1
in doze mode
End of enumeration elements list.
GPR9 General Purpose Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR10 General Purpose Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NIDEN : ARM non-secure (non-invasive) debug enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NIDEN_0
Debug turned off.
0x1 : NIDEN_1
Debug enabled (default).
End of enumeration elements list.
DBG_EN : ARM invasive debug enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DBG_EN_0
Debug turned off.
0x1 : DBG_EN_1
Debug enabled (default).
End of enumeration elements list.
SEC_ERR_RESP : Security error response enable for all security gaskets (on both AHB and AXI buses)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SEC_ERR_RESP_0
OKEY response
0x1 : SEC_ERR_RESP_1
SLVError (default)
End of enumeration elements list.
DCPKEY_OCOTP_OR_KEYMUX : DCP Key selection bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DCPKEY_OCOTP_OR_KEYMUX_0
Select key from Key MUX (SNVS/OTPMK).
0x1 : DCPKEY_OCOTP_OR_KEYMUX_1
Select key from OCOTP (SW_GP2).
End of enumeration elements list.
OCRAM_TZ_EN : OCRAM TrustZone (TZ) enable.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OCRAM_TZ_EN_0
The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor).
0x1 : OCRAM_TZ_EN_1
The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.
End of enumeration elements list.
OCRAM_TZ_ADDR : OCRAM TrustZone (TZ) start address
bits : 9 - 14 (6 bit)
access : read-write
LOCK_NIDEN : Lock NIDEN field for changes
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : LOCK_NIDEN_0
Field is not locked
0x1 : LOCK_NIDEN_1
Field is locked (read access only)
End of enumeration elements list.
LOCK_DBG_EN : Lock DBG_EN field for changes
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : LOCK_DBG_EN_0
Field is not locked
0x1 : LOCK_DBG_EN_1
Field is locked (read access only)
End of enumeration elements list.
LOCK_SEC_ERR_RESP : Lock SEC_ERR_RESP field for changes
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : LOCK_SEC_ERR_RESP_0
Field is not locked
0x1 : LOCK_SEC_ERR_RESP_1
Field is locked (read access only)
End of enumeration elements list.
LOCK_DCPKEY_OCOTP_OR_KEYMUX : Lock DCP Key OCOTP/Key MUX selection bit
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : LOCK_DCPKEY_OCOTP_OR_KEYMUX_0
Field is not locked
0x1 : LOCK_DCPKEY_OCOTP_OR_KEYMUX_1
Field is locked (read access only)
End of enumeration elements list.
LOCK_OCRAM_TZ_EN : Lock OCRAM_TZ_EN field for changes
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : LOCK_OCRAM_TZ_EN_0
Field is not locked
0x1 : LOCK_OCRAM_TZ_EN_1
Field is locked (read access only)
End of enumeration elements list.
LOCK_OCRAM_TZ_ADDR : Lock OCRAM_TZ_ADDR field for changes
bits : 25 - 31 (7 bit)
access : read-write
Enumeration:
0 : LOCK_OCRAM_TZ_ADDR_0
Field is not locked
0x1 : LOCK_OCRAM_TZ_ADDR_1
Field is locked (read access only)
End of enumeration elements list.
GPR11 General Purpose Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M7_APC_AC_R0_CTRL : Access control of memory region-0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : M7_APC_AC_R0_CTRL_0
No access protection
0x1 : M7_APC_AC_R0_CTRL_1
M7 debug protection enabled
End of enumeration elements list.
M7_APC_AC_R1_CTRL : Access control of memory region-1
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : M7_APC_AC_R1_CTRL_0
No access protection
0x1 : M7_APC_AC_R1_CTRL_1
M7 debug protection enabled
End of enumeration elements list.
M7_APC_AC_R2_CTRL : Access control of memory region-2
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : M7_APC_AC_R2_CTRL_0
No access protection
0x1 : M7_APC_AC_R2_CTRL_1
M7 debug protection enabled
End of enumeration elements list.
M7_APC_AC_R3_CTRL : Access control of memory region-3
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : M7_APC_AC_R3_CTRL_0
No access protection
0x1 : M7_APC_AC_R3_CTRL_1
M7 debug protection enabled
End of enumeration elements list.
BEE_DE_RX_EN : BEE data decryption of memory region-n (n = 3 to 0)
bits : 8 - 11 (4 bit)
access : read-write
LOCK_M7_APC_AC_R0_CTRL : Lock M7_APC_AC_R0_CTRL field for changes
bits : 16 - 17 (2 bit)
access : read-write
LOCK_M7_APC_AC_R1_CTRL : Lock M7_APC_AC_R1_CTRL field for changes
bits : 18 - 19 (2 bit)
access : read-write
LOCK_M7_APC_AC_R2_CTRL : Lock M7_APC_AC_R2_CTRL field for changes
bits : 20 - 21 (2 bit)
access : read-write
LOCK_M7_APC_AC_R3_CTRL : Lock M7_APC_AC_R3_CTRL field for changes
bits : 22 - 23 (2 bit)
access : read-write
LOCK_BEE_DE_RX_EN : Lock BEE_DE_RX_EN[n] (n = 3 to 0) field for changes
bits : 24 - 27 (4 bit)
access : read-write
GPR12 General Purpose Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXIO1_IPG_STOP_MODE : FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FLEXIO1_IPG_STOP_MODE_0
FlexIO1 is functional in Stop mode.
0x1 : FLEXIO1_IPG_STOP_MODE_1
When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode.
End of enumeration elements list.
FLEXIO1_IPG_DOZE : FLEXIO1 ipg_doze mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FLEXIO1_IPG_DOZE_0
FLEXIO1 is not in doze mode
0x1 : FLEXIO1_IPG_DOZE_1
FLEXIO1 is in doze mode
End of enumeration elements list.
GPR13 General Purpose Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCACHE_USDHC : uSDHC block cacheable attribute value of AXI read transactions
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ARCACHE_USDHC_0
Cacheable attribute is off for read transactions.
0x1 : ARCACHE_USDHC_1
Cacheable attribute is on for read transactions.
End of enumeration elements list.
AWCACHE_USDHC : uSDHC block cacheable attribute value of AXI write transactions
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : AWCACHE_USDHC_0
Cacheable attribute is off for write transactions.
0x1 : AWCACHE_USDHC_1
Cacheable attribute is on for write transactions.
End of enumeration elements list.
CACHE_USB : USB block cacheable attribute value of AXI transactions
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : CACHE_USB_0
Cacheable attribute is off for read/write transactions.
0x1 : CACHE_USB_1
Cacheable attribute is on for read/write transactions.
End of enumeration elements list.
GPR14 General Purpose Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM7_CFGITCMSZ : ITCM total size configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : CM7_CFGITCMSZ_0
0 KB (No ITCM)
0x3 : CM7_CFGITCMSZ_3
4 KB
0x4 : CM7_CFGITCMSZ_4
8 KB
0x5 : CM7_CFGITCMSZ_5
16 KB
0x6 : CM7_CFGITCMSZ_6
32 KB
0x7 : CM7_CFGITCMSZ_7
64 KB
0x8 : CM7_CFGITCMSZ_8
128 KB
0x9 : CM7_CFGITCMSZ_9
256 KB
End of enumeration elements list.
CM7_CFGDTCMSZ : DTCM total size configuration
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : CM7_CFGDTCMSZ_0
0 KB (No DTCM)
0x3 : CM7_CFGDTCMSZ_3
4 KB
0x4 : CM7_CFGDTCMSZ_4
8 KB
0x5 : CM7_CFGDTCMSZ_5
16 KB
0x6 : CM7_CFGDTCMSZ_6
32 KB
0x7 : CM7_CFGDTCMSZ_7
64 KB
0x8 : CM7_CFGDTCMSZ_8
128 KB
0x9 : CM7_CFGDTCMSZ_9
256 KB
End of enumeration elements list.
GPR15 General Purpose Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPR1 General Purpose Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI1_MCLK1_SEL : SAI1 MCLK1 source select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SAI1_MCLK1_SEL_0
ccm.ssi1_clk_root
0x1 : SAI1_MCLK1_SEL_1
ccm.ssi2_clk_root
0x2 : SAI1_MCLK1_SEL_2
ccm.ssi3_clk_root
0x3 : SAI1_MCLK1_SEL_3
iomux.sai1_ipg_clk_sai_mclk
0x4 : SAI1_MCLK1_SEL_4
iomux.sai2_ipg_clk_sai_mclk
0x5 : SAI1_MCLK1_SEL_5
iomux.sai3_ipg_clk_sai_mclk
End of enumeration elements list.
SAI1_MCLK2_SEL : SAI1 MCLK2 source select
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : SAI1_MCLK2_SEL_0
ccm.ssi1_clk_root
0x1 : SAI1_MCLK2_SEL_1
ccm.ssi2_clk_root
0x2 : SAI1_MCLK2_SEL_2
ccm.ssi3_clk_root
0x3 : SAI1_MCLK2_SEL_3
iomux.sai1_ipg_clk_sai_mclk
0x4 : SAI1_MCLK2_SEL_4
iomux.sai2_ipg_clk_sai_mclk
0x5 : SAI1_MCLK2_SEL_5
iomux.sai3_ipg_clk_sai_mclk
End of enumeration elements list.
SAI1_MCLK3_SEL : SAI1 MCLK3 source select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SAI1_MCLK3_SEL_0
ccm.spdif0_clk_root
0x1 : SAI1_MCLK3_SEL_1
SPDIF_EXT_CLK
0x2 : SAI1_MCLK3_SEL_2
spdif.spdif_srclk
0x3 : SAI1_MCLK3_SEL_3
spdif.spdif_outclock
End of enumeration elements list.
SAI2_MCLK3_SEL : SAI2 MCLK3 source select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : SAI2_MCLK3_SEL_0
ccm.spdif0_clk_root
0x1 : SAI2_MCLK3_SEL_1
SPDIF_EXT_CLK
0x2 : SAI2_MCLK3_SEL_2
spdif.spdif_srclk
0x3 : SAI2_MCLK3_SEL_3
spdif.spdif_outclock
End of enumeration elements list.
SAI3_MCLK3_SEL : SAI3 MCLK3 source select
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : SAI3_MCLK3_SEL_0
ccm.spdif0_clk_root
0x1 : SAI3_MCLK3_SEL_1
SPDIF_EXT_CLK
0x2 : SAI3_MCLK3_SEL_2
spdif.spdif_srclk
0x3 : SAI3_MCLK3_SEL_3
spdif.spdif_outclock
End of enumeration elements list.
GINT : Global Interrupt
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : GINT_0
Global interrupt request is not asserted.
0x1 : GINT_1
Global interrupt request is asserted.
End of enumeration elements list.
SAI1_MCLK_DIR : sai1.MCLK signal direction control
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SAI1_MCLK_DIR_0
sai1.MCLK is input signal
0x1 : SAI1_MCLK_DIR_1
sai1.MCLK is output signal
End of enumeration elements list.
SAI2_MCLK_DIR : sai2.MCLK signal direction control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SAI2_MCLK_DIR_0
sai2.MCLK is input signal
0x1 : SAI2_MCLK_DIR_1
sai2.MCLK is output signal
End of enumeration elements list.
SAI3_MCLK_DIR : sai3.MCLK signal direction control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SAI3_MCLK_DIR_0
sai3.MCLK is input signal
0x1 : SAI3_MCLK_DIR_1
sai3.MCLK is output signal
End of enumeration elements list.
EXC_MON : Exclusive monitor response select of illegal command
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : EXC_MON_0
OKAY response
0x1 : EXC_MON_1
SLVError response
End of enumeration elements list.
CM7_FORCE_HCLK_EN : ARM CM7 platform AHB clock enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : CM7_FORCE_HCLK_EN_0
AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible.
0x1 : CM7_FORCE_HCLK_EN_1
AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible.
End of enumeration elements list.
GPR16 General Purpose Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_ITCM_EN : ITCM enable initialization out of reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : INIT_ITCM_EN_0
ITCM is disabled
0x1 : INIT_ITCM_EN_1
ITCM is enabled
End of enumeration elements list.
INIT_DTCM_EN : DTCM enable initialization out of reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INIT_DTCM_EN_0
DTCM is disabled
0x1 : INIT_DTCM_EN_1
DTCM is enabled
End of enumeration elements list.
FLEXRAM_BANK_CFG_SEL : FlexRAM bank config source select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FLEXRAM_BANK_CFG_SEL_0
use fuse value to config
0x1 : FLEXRAM_BANK_CFG_SEL_1
use FLEXRAM_BANK_CFG to config
End of enumeration elements list.
GPR17 General Purpose Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXRAM_BANK_CFG : FlexRAM bank config value
bits : 0 - 7 (8 bit)
access : read-write
GPR18 General Purpose Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_M7_APC_AC_R0_BOT : lock M7_APC_AC_R0_BOT field for changes
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_M7_APC_AC_R0_BOT_0
Register field [31:1] is not locked
0x1 : LOCK_M7_APC_AC_R0_BOT_1
Register field [31:1] is locked (read access only)
End of enumeration elements list.
M7_APC_AC_R0_BOT : APC end address of memory region-0
bits : 3 - 31 (29 bit)
access : read-write
GPR19 General Purpose Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_M7_APC_AC_R0_TOP : lock M7_APC_AC_R0_TOP field for changes
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_M7_APC_AC_R0_TOP_0
Register field [31:1] is not locked
0x1 : LOCK_M7_APC_AC_R0_TOP_1
Register field [31:1] is locked (read access only)
End of enumeration elements list.
M7_APC_AC_R0_TOP : APC start address of memory region-0
bits : 3 - 31 (29 bit)
access : read-write
GPR20 General Purpose Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_M7_APC_AC_R1_BOT : lock M7_APC_AC_R1_BOT field for changes
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_M7_APC_AC_R1_BOT_0
Register field [31:1] is not locked
0x1 : LOCK_M7_APC_AC_R1_BOT_1
Register field [31:1] is locked (read access only)
End of enumeration elements list.
M7_APC_AC_R1_BOT : APC end address of memory region-1
bits : 3 - 31 (29 bit)
access : read-write
GPR21 General Purpose Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_M7_APC_AC_R1_TOP : lock M7_APC_AC_R1_TOP field for changes
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_M7_APC_AC_R1_TOP_0
Register field [31:1] is not locked
0x1 : LOCK_M7_APC_AC_R1_TOP_1
Register field [31:1] is locked (read access only)
End of enumeration elements list.
M7_APC_AC_R1_TOP : APC start address of memory region-1
bits : 3 - 31 (29 bit)
access : read-write
GPR22 General Purpose Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_M7_APC_AC_R2_BOT : lock M7_APC_AC_R2_BOT field for changes
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_M7_APC_AC_R2_BOT_0
Register field [31:1] is not locked
0x1 : LOCK_M7_APC_AC_R2_BOT_1
Register field [31:1] is locked (read access only)
End of enumeration elements list.
M7_APC_AC_R2_BOT : APC end address of memory region-2
bits : 3 - 31 (29 bit)
access : read-write
GPR23 General Purpose Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_M7_APC_AC_R2_TOP : lock M7_APC_AC_R2_TOP field for changes
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_M7_APC_AC_R2_TOP_0
Register field [31:1] is not locked
0x1 : LOCK_M7_APC_AC_R2_TOP_1
Register field [31:1] is locked (read access only)
End of enumeration elements list.
M7_APC_AC_R2_TOP : APC start address of memory region-2
bits : 3 - 31 (29 bit)
access : read-write
GPR24 General Purpose Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_M7_APC_AC_R3_BOT : lock M7_APC_AC_R3_BOT field for changes
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_M7_APC_AC_R3_BOT_0
Register field [31:1] is not locked
0x1 : LOCK_M7_APC_AC_R3_BOT_1
Register field [31:1] is locked (read access only)
End of enumeration elements list.
M7_APC_AC_R3_BOT : APC end address of memory region-3
bits : 3 - 31 (29 bit)
access : read-write
GPR25 General Purpose Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_M7_APC_AC_R3_TOP : lock M7_APC_AC_R3_TOP field for changes
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCK_M7_APC_AC_R3_TOP_0
Register field [31:1] is not locked
0x1 : LOCK_M7_APC_AC_R3_TOP_1
Register field [31:1] is locked (read access only)
End of enumeration elements list.
M7_APC_AC_R3_TOP : APC start address of memory region-3
bits : 3 - 31 (29 bit)
access : read-write
GPR2 General Purpose Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L2_MEM_EN_POWERSAVING : Enable power saving features on L2 memory
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : L2_MEM_EN_POWERSAVING_0
Enters power saving mode only when chip is in SUSPEND mode
0x1 : L2_MEM_EN_POWERSAVING_1
Controlled by L2_MEM_DEEPSLEEP bitfield
End of enumeration elements list.
RAM_AUTO_CLK_GATING_EN : Automatically gate off RAM clock when RAM is not accessed.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : RAM_AUTO_CLK_GATING_EN_0
disable automatically gate off RAM clock
0x1 : RAM_AUTO_CLK_GATING_EN_1
enable automatically gate off RAM clock
End of enumeration elements list.
L2_MEM_DEEPSLEEP : This bit controls how memory (OCRAM) enters Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : L2_MEM_DEEPSLEEP_0
No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode)
0x1 : L2_MEM_DEEPSLEEP_1
Force memory into deep sleep mode (OCRAM in power saving mode)
End of enumeration elements list.
MQS_CLK_DIV : Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency.
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : DIVIDE_1
mclk frequency = 1/1 * hmclk frequency
0x1 : DIVIDE_2
mclk frequency = 1/2 * hmclk frequency
0x2 : DIVIDE_3
mclk frequency = 1/3 * hmclk frequency
0x3 : DIVIDE_4
mclk frequency = 1/4 * hmclk frequency
0x4 : DIVIDE_5
mclk frequency = 1/5 * hmclk frequency
0x5 : DIVIDE_6
mclk frequency = 1/6 * hmclk frequency
0x6 : DIVIDE_7
mclk frequency = 1/7 * hmclk frequency
0x7 : DIVIDE_8
mclk frequency = 1/8 * hmclk frequency
0x8 : DIVIDE_9
mclk frequency = 1/9 * hmclk frequency
0x9 : DIVIDE_10
mclk frequency = 1/10 * hmclk frequency
0xA : DIVIDE_11
mclk frequency = 1/11 * hmclk frequency
0xB : DIVIDE_12
mclk frequency = 1/12 * hmclk frequency
0xC : DIVIDE_13
mclk frequency = 1/13 * hmclk frequency
0xD : DIVIDE_14
mclk frequency = 1/14 * hmclk frequency
0xE : DIVIDE_15
mclk frequency = 1/15 * hmclk frequency
0xF : DIVIDE_16
mclk frequency = 1/16 * hmclk frequency
0x10 : DIVIDE_17
mclk frequency = 1/17 * hmclk frequency
0x11 : DIVIDE_18
mclk frequency = 1/18 * hmclk frequency
0x12 : DIVIDE_19
mclk frequency = 1/19 * hmclk frequency
0x13 : DIVIDE_20
mclk frequency = 1/20 * hmclk frequency
0x14 : DIVIDE_21
mclk frequency = 1/21 * hmclk frequency
0x15 : DIVIDE_22
mclk frequency = 1/22 * hmclk frequency
0x16 : DIVIDE_23
mclk frequency = 1/23 * hmclk frequency
0x17 : DIVIDE_24
mclk frequency = 1/24 * hmclk frequency
0x18 : DIVIDE_25
mclk frequency = 1/25 * hmclk frequency
0x19 : DIVIDE_26
mclk frequency = 1/26 * hmclk frequency
0x1A : DIVIDE_27
mclk frequency = 1/27 * hmclk frequency
0x1B : DIVIDE_28
mclk frequency = 1/28 * hmclk frequency
0x1C : DIVIDE_29
mclk frequency = 1/29 * hmclk frequency
0x1D : DIVIDE_30
mclk frequency = 1/30 * hmclk frequency
0x1E : DIVIDE_31
mclk frequency = 1/31 * hmclk frequency
0x1F : DIVIDE_32
mclk frequency = 1/32 * hmclk frequency
0x20 : DIVIDE_33
mclk frequency = 1/33 * hmclk frequency
0x21 : DIVIDE_34
mclk frequency = 1/34 * hmclk frequency
0x22 : DIVIDE_35
mclk frequency = 1/35 * hmclk frequency
0x23 : DIVIDE_36
mclk frequency = 1/36 * hmclk frequency
0x24 : DIVIDE_37
mclk frequency = 1/37 * hmclk frequency
0x25 : DIVIDE_38
mclk frequency = 1/38 * hmclk frequency
0x26 : DIVIDE_39
mclk frequency = 1/39 * hmclk frequency
0x27 : DIVIDE_40
mclk frequency = 1/40 * hmclk frequency
0x28 : DIVIDE_41
mclk frequency = 1/41 * hmclk frequency
0x29 : DIVIDE_42
mclk frequency = 1/42 * hmclk frequency
0x2A : DIVIDE_43
mclk frequency = 1/43 * hmclk frequency
0x2B : DIVIDE_44
mclk frequency = 1/44 * hmclk frequency
0x2C : DIVIDE_45
mclk frequency = 1/45 * hmclk frequency
0x2D : DIVIDE_46
mclk frequency = 1/46 * hmclk frequency
0x2E : DIVIDE_47
mclk frequency = 1/47 * hmclk frequency
0x2F : DIVIDE_48
mclk frequency = 1/48 * hmclk frequency
0x30 : DIVIDE_49
mclk frequency = 1/49 * hmclk frequency
0x31 : DIVIDE_50
mclk frequency = 1/50 * hmclk frequency
0x32 : DIVIDE_51
mclk frequency = 1/51 * hmclk frequency
0x33 : DIVIDE_52
mclk frequency = 1/52 * hmclk frequency
0x34 : DIVIDE_53
mclk frequency = 1/53 * hmclk frequency
0x35 : DIVIDE_54
mclk frequency = 1/54 * hmclk frequency
0x36 : DIVIDE_55
mclk frequency = 1/55 * hmclk frequency
0x37 : DIVIDE_56
mclk frequency = 1/56 * hmclk frequency
0x38 : DIVIDE_57
mclk frequency = 1/57 * hmclk frequency
0x39 : DIVIDE_58
mclk frequency = 1/58 * hmclk frequency
0x3A : DIVIDE_59
mclk frequency = 1/59 * hmclk frequency
0x3B : DIVIDE_60
mclk frequency = 1/60 * hmclk frequency
0x3C : DIVIDE_61
mclk frequency = 1/61 * hmclk frequency
0x3D : DIVIDE_62
mclk frequency = 1/62 * hmclk frequency
0x3E : DIVIDE_63
mclk frequency = 1/63 * hmclk frequency
0x3F : DIVIDE_64
mclk frequency = 1/64 * hmclk frequency
0x40 : DIVIDE_65
mclk frequency = 1/65 * hmclk frequency
0x41 : DIVIDE_66
mclk frequency = 1/66 * hmclk frequency
0x42 : DIVIDE_67
mclk frequency = 1/67 * hmclk frequency
0x43 : DIVIDE_68
mclk frequency = 1/68 * hmclk frequency
0x44 : DIVIDE_69
mclk frequency = 1/69 * hmclk frequency
0x45 : DIVIDE_70
mclk frequency = 1/70 * hmclk frequency
0x46 : DIVIDE_71
mclk frequency = 1/71 * hmclk frequency
0x47 : DIVIDE_72
mclk frequency = 1/72 * hmclk frequency
0x48 : DIVIDE_73
mclk frequency = 1/73 * hmclk frequency
0x49 : DIVIDE_74
mclk frequency = 1/74 * hmclk frequency
0x4A : DIVIDE_75
mclk frequency = 1/75 * hmclk frequency
0x4B : DIVIDE_76
mclk frequency = 1/76 * hmclk frequency
0x4C : DIVIDE_77
mclk frequency = 1/77 * hmclk frequency
0x4D : DIVIDE_78
mclk frequency = 1/78 * hmclk frequency
0x4E : DIVIDE_79
mclk frequency = 1/79 * hmclk frequency
0x4F : DIVIDE_80
mclk frequency = 1/80 * hmclk frequency
0x50 : DIVIDE_81
mclk frequency = 1/81 * hmclk frequency
0x51 : DIVIDE_82
mclk frequency = 1/82 * hmclk frequency
0x52 : DIVIDE_83
mclk frequency = 1/83 * hmclk frequency
0x53 : DIVIDE_84
mclk frequency = 1/84 * hmclk frequency
0x54 : DIVIDE_85
mclk frequency = 1/85 * hmclk frequency
0x55 : DIVIDE_86
mclk frequency = 1/86 * hmclk frequency
0x56 : DIVIDE_87
mclk frequency = 1/87 * hmclk frequency
0x57 : DIVIDE_88
mclk frequency = 1/88 * hmclk frequency
0x58 : DIVIDE_89
mclk frequency = 1/89 * hmclk frequency
0x59 : DIVIDE_90
mclk frequency = 1/90 * hmclk frequency
0x5A : DIVIDE_91
mclk frequency = 1/91 * hmclk frequency
0x5B : DIVIDE_92
mclk frequency = 1/92 * hmclk frequency
0x5C : DIVIDE_93
mclk frequency = 1/93 * hmclk frequency
0x5D : DIVIDE_94
mclk frequency = 1/94 * hmclk frequency
0x5E : DIVIDE_95
mclk frequency = 1/95 * hmclk frequency
0x5F : DIVIDE_96
mclk frequency = 1/96 * hmclk frequency
0x60 : DIVIDE_97
mclk frequency = 1/97 * hmclk frequency
0x61 : DIVIDE_98
mclk frequency = 1/98 * hmclk frequency
0x62 : DIVIDE_99
mclk frequency = 1/99 * hmclk frequency
0x63 : DIVIDE_100
mclk frequency = 1/100 * hmclk frequency
0x64 : DIVIDE_101
mclk frequency = 1/101 * hmclk frequency
0x65 : DIVIDE_102
mclk frequency = 1/102 * hmclk frequency
0x66 : DIVIDE_103
mclk frequency = 1/103 * hmclk frequency
0x67 : DIVIDE_104
mclk frequency = 1/104 * hmclk frequency
0x68 : DIVIDE_105
mclk frequency = 1/105 * hmclk frequency
0x69 : DIVIDE_106
mclk frequency = 1/106 * hmclk frequency
0x6A : DIVIDE_107
mclk frequency = 1/107 * hmclk frequency
0x6B : DIVIDE_108
mclk frequency = 1/108 * hmclk frequency
0x6C : DIVIDE_109
mclk frequency = 1/109 * hmclk frequency
0x6D : DIVIDE_110
mclk frequency = 1/110 * hmclk frequency
0x6E : DIVIDE_111
mclk frequency = 1/111 * hmclk frequency
0x6F : DIVIDE_112
mclk frequency = 1/112 * hmclk frequency
0x70 : DIVIDE_113
mclk frequency = 1/113 * hmclk frequency
0x71 : DIVIDE_114
mclk frequency = 1/114 * hmclk frequency
0x72 : DIVIDE_115
mclk frequency = 1/115 * hmclk frequency
0x73 : DIVIDE_116
mclk frequency = 1/116 * hmclk frequency
0x74 : DIVIDE_117
mclk frequency = 1/117 * hmclk frequency
0x75 : DIVIDE_118
mclk frequency = 1/118 * hmclk frequency
0x76 : DIVIDE_119
mclk frequency = 1/119 * hmclk frequency
0x77 : DIVIDE_120
mclk frequency = 1/120 * hmclk frequency
0x78 : DIVIDE_121
mclk frequency = 1/121 * hmclk frequency
0x79 : DIVIDE_122
mclk frequency = 1/122 * hmclk frequency
0x7A : DIVIDE_123
mclk frequency = 1/123 * hmclk frequency
0x7B : DIVIDE_124
mclk frequency = 1/124 * hmclk frequency
0x7C : DIVIDE_125
mclk frequency = 1/125 * hmclk frequency
0x7D : DIVIDE_126
mclk frequency = 1/126 * hmclk frequency
0x7E : DIVIDE_127
mclk frequency = 1/127 * hmclk frequency
0x7F : DIVIDE_128
mclk frequency = 1/128 * hmclk frequency
0x80 : DIVIDE_129
mclk frequency = 1/129 * hmclk frequency
0x81 : DIVIDE_130
mclk frequency = 1/130 * hmclk frequency
0x82 : DIVIDE_131
mclk frequency = 1/131 * hmclk frequency
0x83 : DIVIDE_132
mclk frequency = 1/132 * hmclk frequency
0x84 : DIVIDE_133
mclk frequency = 1/133 * hmclk frequency
0x85 : DIVIDE_134
mclk frequency = 1/134 * hmclk frequency
0x86 : DIVIDE_135
mclk frequency = 1/135 * hmclk frequency
0x87 : DIVIDE_136
mclk frequency = 1/136 * hmclk frequency
0x88 : DIVIDE_137
mclk frequency = 1/137 * hmclk frequency
0x89 : DIVIDE_138
mclk frequency = 1/138 * hmclk frequency
0x8A : DIVIDE_139
mclk frequency = 1/139 * hmclk frequency
0x8B : DIVIDE_140
mclk frequency = 1/140 * hmclk frequency
0x8C : DIVIDE_141
mclk frequency = 1/141 * hmclk frequency
0x8D : DIVIDE_142
mclk frequency = 1/142 * hmclk frequency
0x8E : DIVIDE_143
mclk frequency = 1/143 * hmclk frequency
0x8F : DIVIDE_144
mclk frequency = 1/144 * hmclk frequency
0x90 : DIVIDE_145
mclk frequency = 1/145 * hmclk frequency
0x91 : DIVIDE_146
mclk frequency = 1/146 * hmclk frequency
0x92 : DIVIDE_147
mclk frequency = 1/147 * hmclk frequency
0x93 : DIVIDE_148
mclk frequency = 1/148 * hmclk frequency
0x94 : DIVIDE_149
mclk frequency = 1/149 * hmclk frequency
0x95 : DIVIDE_150
mclk frequency = 1/150 * hmclk frequency
0x96 : DIVIDE_151
mclk frequency = 1/151 * hmclk frequency
0x97 : DIVIDE_152
mclk frequency = 1/152 * hmclk frequency
0x98 : DIVIDE_153
mclk frequency = 1/153 * hmclk frequency
0x99 : DIVIDE_154
mclk frequency = 1/154 * hmclk frequency
0x9A : DIVIDE_155
mclk frequency = 1/155 * hmclk frequency
0x9B : DIVIDE_156
mclk frequency = 1/156 * hmclk frequency
0x9C : DIVIDE_157
mclk frequency = 1/157 * hmclk frequency
0x9D : DIVIDE_158
mclk frequency = 1/158 * hmclk frequency
0x9E : DIVIDE_159
mclk frequency = 1/159 * hmclk frequency
0x9F : DIVIDE_160
mclk frequency = 1/160 * hmclk frequency
0xA0 : DIVIDE_161
mclk frequency = 1/161 * hmclk frequency
0xA1 : DIVIDE_162
mclk frequency = 1/162 * hmclk frequency
0xA2 : DIVIDE_163
mclk frequency = 1/163 * hmclk frequency
0xA3 : DIVIDE_164
mclk frequency = 1/164 * hmclk frequency
0xA4 : DIVIDE_165
mclk frequency = 1/165 * hmclk frequency
0xA5 : DIVIDE_166
mclk frequency = 1/166 * hmclk frequency
0xA6 : DIVIDE_167
mclk frequency = 1/167 * hmclk frequency
0xA7 : DIVIDE_168
mclk frequency = 1/168 * hmclk frequency
0xA8 : DIVIDE_169
mclk frequency = 1/169 * hmclk frequency
0xA9 : DIVIDE_170
mclk frequency = 1/170 * hmclk frequency
0xAA : DIVIDE_171
mclk frequency = 1/171 * hmclk frequency
0xAB : DIVIDE_172
mclk frequency = 1/172 * hmclk frequency
0xAC : DIVIDE_173
mclk frequency = 1/173 * hmclk frequency
0xAD : DIVIDE_174
mclk frequency = 1/174 * hmclk frequency
0xAE : DIVIDE_175
mclk frequency = 1/175 * hmclk frequency
0xAF : DIVIDE_176
mclk frequency = 1/176 * hmclk frequency
0xB0 : DIVIDE_177
mclk frequency = 1/177 * hmclk frequency
0xB1 : DIVIDE_178
mclk frequency = 1/178 * hmclk frequency
0xB2 : DIVIDE_179
mclk frequency = 1/179 * hmclk frequency
0xB3 : DIVIDE_180
mclk frequency = 1/180 * hmclk frequency
0xB4 : DIVIDE_181
mclk frequency = 1/181 * hmclk frequency
0xB5 : DIVIDE_182
mclk frequency = 1/182 * hmclk frequency
0xB6 : DIVIDE_183
mclk frequency = 1/183 * hmclk frequency
0xB7 : DIVIDE_184
mclk frequency = 1/184 * hmclk frequency
0xB8 : DIVIDE_185
mclk frequency = 1/185 * hmclk frequency
0xB9 : DIVIDE_186
mclk frequency = 1/186 * hmclk frequency
0xBA : DIVIDE_187
mclk frequency = 1/187 * hmclk frequency
0xBB : DIVIDE_188
mclk frequency = 1/188 * hmclk frequency
0xBC : DIVIDE_189
mclk frequency = 1/189 * hmclk frequency
0xBD : DIVIDE_190
mclk frequency = 1/190 * hmclk frequency
0xBE : DIVIDE_191
mclk frequency = 1/191 * hmclk frequency
0xBF : DIVIDE_192
mclk frequency = 1/192 * hmclk frequency
0xC0 : DIVIDE_193
mclk frequency = 1/193 * hmclk frequency
0xC1 : DIVIDE_194
mclk frequency = 1/194 * hmclk frequency
0xC2 : DIVIDE_195
mclk frequency = 1/195 * hmclk frequency
0xC3 : DIVIDE_196
mclk frequency = 1/196 * hmclk frequency
0xC4 : DIVIDE_197
mclk frequency = 1/197 * hmclk frequency
0xC5 : DIVIDE_198
mclk frequency = 1/198 * hmclk frequency
0xC6 : DIVIDE_199
mclk frequency = 1/199 * hmclk frequency
0xC7 : DIVIDE_200
mclk frequency = 1/200 * hmclk frequency
0xC8 : DIVIDE_201
mclk frequency = 1/201 * hmclk frequency
0xC9 : DIVIDE_202
mclk frequency = 1/202 * hmclk frequency
0xCA : DIVIDE_203
mclk frequency = 1/203 * hmclk frequency
0xCB : DIVIDE_204
mclk frequency = 1/204 * hmclk frequency
0xCC : DIVIDE_205
mclk frequency = 1/205 * hmclk frequency
0xCD : DIVIDE_206
mclk frequency = 1/206 * hmclk frequency
0xCE : DIVIDE_207
mclk frequency = 1/207 * hmclk frequency
0xCF : DIVIDE_208
mclk frequency = 1/208 * hmclk frequency
0xD0 : DIVIDE_209
mclk frequency = 1/209 * hmclk frequency
0xD1 : DIVIDE_210
mclk frequency = 1/210 * hmclk frequency
0xD2 : DIVIDE_211
mclk frequency = 1/211 * hmclk frequency
0xD3 : DIVIDE_212
mclk frequency = 1/212 * hmclk frequency
0xD4 : DIVIDE_213
mclk frequency = 1/213 * hmclk frequency
0xD5 : DIVIDE_214
mclk frequency = 1/214 * hmclk frequency
0xD6 : DIVIDE_215
mclk frequency = 1/215 * hmclk frequency
0xD7 : DIVIDE_216
mclk frequency = 1/216 * hmclk frequency
0xD8 : DIVIDE_217
mclk frequency = 1/217 * hmclk frequency
0xD9 : DIVIDE_218
mclk frequency = 1/218 * hmclk frequency
0xDA : DIVIDE_219
mclk frequency = 1/219 * hmclk frequency
0xDB : DIVIDE_220
mclk frequency = 1/220 * hmclk frequency
0xDC : DIVIDE_221
mclk frequency = 1/221 * hmclk frequency
0xDD : DIVIDE_222
mclk frequency = 1/222 * hmclk frequency
0xDE : DIVIDE_223
mclk frequency = 1/223 * hmclk frequency
0xDF : DIVIDE_224
mclk frequency = 1/224 * hmclk frequency
0xE0 : DIVIDE_225
mclk frequency = 1/225 * hmclk frequency
0xE1 : DIVIDE_226
mclk frequency = 1/226 * hmclk frequency
0xE2 : DIVIDE_227
mclk frequency = 1/227 * hmclk frequency
0xE3 : DIVIDE_228
mclk frequency = 1/228 * hmclk frequency
0xE4 : DIVIDE_229
mclk frequency = 1/229 * hmclk frequency
0xE5 : DIVIDE_230
mclk frequency = 1/230 * hmclk frequency
0xE6 : DIVIDE_231
mclk frequency = 1/231 * hmclk frequency
0xE7 : DIVIDE_232
mclk frequency = 1/232 * hmclk frequency
0xE8 : DIVIDE_233
mclk frequency = 1/233 * hmclk frequency
0xE9 : DIVIDE_234
mclk frequency = 1/234 * hmclk frequency
0xEA : DIVIDE_235
mclk frequency = 1/235 * hmclk frequency
0xEB : DIVIDE_236
mclk frequency = 1/236 * hmclk frequency
0xEC : DIVIDE_237
mclk frequency = 1/237 * hmclk frequency
0xED : DIVIDE_238
mclk frequency = 1/238 * hmclk frequency
0xEE : DIVIDE_239
mclk frequency = 1/239 * hmclk frequency
0xEF : DIVIDE_240
mclk frequency = 1/240 * hmclk frequency
0xF0 : DIVIDE_241
mclk frequency = 1/241 * hmclk frequency
0xF1 : DIVIDE_242
mclk frequency = 1/242 * hmclk frequency
0xF2 : DIVIDE_243
mclk frequency = 1/243 * hmclk frequency
0xF3 : DIVIDE_244
mclk frequency = 1/244 * hmclk frequency
0xF4 : DIVIDE_245
mclk frequency = 1/245 * hmclk frequency
0xF5 : DIVIDE_246
mclk frequency = 1/246 * hmclk frequency
0xF6 : DIVIDE_247
mclk frequency = 1/247 * hmclk frequency
0xF7 : DIVIDE_248
mclk frequency = 1/248 * hmclk frequency
0xF8 : DIVIDE_249
mclk frequency = 1/249 * hmclk frequency
0xF9 : DIVIDE_250
mclk frequency = 1/250 * hmclk frequency
0xFA : DIVIDE_251
mclk frequency = 1/251 * hmclk frequency
0xFB : DIVIDE_252
mclk frequency = 1/252 * hmclk frequency
0xFC : DIVIDE_253
mclk frequency = 1/253 * hmclk frequency
0xFD : DIVIDE_254
mclk frequency = 1/254 * hmclk frequency
0xFE : DIVIDE_255
mclk frequency = 1/255 * hmclk frequency
0xFF : DIVIDE_256
mclk frequency = 1/256 * hmclk frequency
End of enumeration elements list.
MQS_SW_RST : MQS software reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : MQS_SW_RST_0
Exit software reset for MQS
0x1 : MQS_SW_RST_1
Enable software reset for MQS
End of enumeration elements list.
MQS_EN : MQS enable.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : MQS_EN_0
Disable MQS
0x1 : MQS_EN_1
Enable MQS
End of enumeration elements list.
MQS_OVERSAMPLE : Medium Quality Sound (MQS) Oversample
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : MQS_OVERSAMPLE_0
32
0x1 : MQS_OVERSAMPLE_1
64
End of enumeration elements list.
QTIMER1_TMR_CNTS_FREEZE : QTIMER1 timer counter freeze
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : QTIMER1_TMR_CNTS_FREEZE_0
Timer counter works normally
0x1 : QTIMER1_TMR_CNTS_FREEZE_1
Reset counter and ouput flags
End of enumeration elements list.
GPR3 General Purpose Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCP_KEY_SEL : Select 128-bit DCP key from 256-bit key from SNVS/OCOTP
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DCP_KEY_SEL_0
Select [127:0] from SNVS/OCOTP key as DCP key
0x1 : DCP_KEY_SEL_1
Select [255:128] from SNVS/OCOTP key as DCP key
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.