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Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

LPOS

UPOSH

LPOSH

UINIT

LINIT

IMR

TST

CTRL2

FILT

UMOD

LMOD

UCOMP

LCOMP

WTR

POSD

POSDH

REV

REVH

UPOS


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPIE CMPIRQ WDE DIE DIRQ XNE XIP XIE XIRQ PH1 REV SWIP HNE HIP HIE HIRQ

CMPIE : Compare Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CMPIE_0

Compare interrupt is disabled

0x1 : CMPIE_1

Compare interrupt is enabled

End of enumeration elements list.

CMPIRQ : Compare Interrupt Request
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : CMPIRQ_0

No match has occurred

0x1 : CMPIRQ_1

COMP match has occurred

End of enumeration elements list.

WDE : Watchdog Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : WDE_0

Watchdog timer is disabled

0x1 : WDE_1

Watchdog timer is enabled

End of enumeration elements list.

DIE : Watchdog Timeout Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DIE_0

Watchdog timer interrupt is disabled

0x1 : DIE_1

Watchdog timer interrupt is enabled

End of enumeration elements list.

DIRQ : Watchdog Timeout Interrupt Request
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DIRQ_0

No interrupt has occurred

0x1 : DIRQ_1

Watchdog timeout interrupt has occurred

End of enumeration elements list.

XNE : Use Negative Edge of INDEX Pulse
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : XNE_0

Use positive transition edge of INDEX pulse

0x1 : XNE_1

Use negative transition edge of INDEX pulse

End of enumeration elements list.

XIP : INDEX Triggered Initialization of Position Counters UPOS and LPOS
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : XIP_0

No action

0x1 : XIP_1

INDEX pulse initializes the position counter

End of enumeration elements list.

XIE : INDEX Pulse Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : XIE_0

INDEX pulse interrupt is disabled

0x1 : XIE_1

INDEX pulse interrupt is enabled

End of enumeration elements list.

XIRQ : INDEX Pulse Interrupt Request
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : XIRQ_0

No interrupt has occurred

0x1 : XIRQ_1

INDEX pulse interrupt has occurred

End of enumeration elements list.

PH1 : Enable Signal Phase Count Mode
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : PH1_0

Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal.

0x1 : PH1_1

Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up

End of enumeration elements list.

REV : Enable Reverse Direction Counting
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : REV_0

Count normally

0x1 : REV_1

Count in the reverse direction

End of enumeration elements list.

SWIP : Software Triggered Initialization of Position Counters UPOS and LPOS
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SWIP_0

No action

0x1 : SWIP_1

Initialize position counter

End of enumeration elements list.

HNE : Use Negative Edge of HOME Input
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : HNE_0

Use positive going edge-to-trigger initialization of position counters UPOS and LPOS

0x1 : HNE_1

Use negative going edge-to-trigger initialization of position counters UPOS and LPOS

End of enumeration elements list.

HIP : Enable HOME to Initialize Position Counters UPOS and LPOS
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : HIP_0

No action

0x1 : HIP_1

HOME signal initializes the position counter

End of enumeration elements list.

HIE : HOME Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : HIE_0

Disable HOME interrupts

0x1 : HIE_1

Enable HOME interrupts

End of enumeration elements list.

HIRQ : HOME Signal Transition Interrupt Request
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : HIRQ_0

No interrupt

0x1 : HIRQ_1

HOME signal transition interrupt request

End of enumeration elements list.


LPOS

Lower Position Counter Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPOS LPOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POS

POS : This read/write register contains the lower (least significant) half of the position counter
bits : 0 - 15 (16 bit)
access : read-write


UPOSH

Upper Position Hold Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPOSH UPOSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSH

POSH : This read-only register contains a snapshot of the UPOS register.
bits : 0 - 15 (16 bit)
access : read-only


LPOSH

Lower Position Hold Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPOSH LPOSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSH

POSH : This read-only register contains a snapshot of the LPOS register.
bits : 0 - 15 (16 bit)
access : read-only


UINIT

Upper Initialization Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UINIT UINIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT

INIT : This read/write register contains the value to be used to initialize the upper half of the position counter (UPOS)
bits : 0 - 15 (16 bit)
access : read-write


LINIT

Lower Initialization Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LINIT LINIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT

INIT : This read/write register contains the value to be used to initialize the lower half of the position counter (LPOS)
bits : 0 - 15 (16 bit)
access : read-write


IMR

Input Monitor Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOME INDEX PHB PHA FHOM FIND FPHB FPHA

HOME : This is the raw HOME input.
bits : 0 - 0 (1 bit)
access : read-only

INDEX : This is the raw INDEX input.
bits : 1 - 1 (1 bit)
access : read-only

PHB : This is the raw PHASEB input.
bits : 2 - 2 (1 bit)
access : read-only

PHA : This is the raw PHASEA input.
bits : 3 - 3 (1 bit)
access : read-only

FHOM : This is the filtered version of HOME input.
bits : 4 - 4 (1 bit)
access : read-only

FIND : This is the filtered version of INDEX input.
bits : 5 - 5 (1 bit)
access : read-only

FPHB : This is the filtered version of PHASEB input.
bits : 6 - 6 (1 bit)
access : read-only

FPHA : This is the filtered version of PHASEA input.
bits : 7 - 7 (1 bit)
access : read-only


TST

Test Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TST TST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEST_COUNT TEST_PERIOD QDN TCE TEN

TEST_COUNT : These bits hold the number of quadrature advances to generate.
bits : 0 - 7 (8 bit)
access : read-write

TEST_PERIOD : These bits hold the period of quadrature phase in IPBus clock cycles.
bits : 8 - 12 (5 bit)
access : read-write

QDN : Quadrature Decoder Negative Signal
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : QDN_0

Leaves quadrature decoder signal in a positive direction

0x1 : QDN_1

Generates a negative quadrature decoder signal

End of enumeration elements list.

TCE : Test Counter Enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : TCE_0

Test count is not enabled

0x1 : TCE_1

Test count is enabled

End of enumeration elements list.

TEN : Test Mode Enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : TEN_0

Test module is not enabled

0x1 : TEN_1

Test module is enabled

End of enumeration elements list.


CTRL2

Control 2 Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDHLD UPDPOS MOD DIR RUIE RUIRQ ROIE ROIRQ REVMOD OUTCTL SABIE SABIRQ

UPDHLD : Update Hold Registers
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : UPDHLD_0

Disable updates of hold registers on rising edge of TRIGGER

0x1 : UPDHLD_1

Enable updates of hold registers on rising edge of TRIGGER

End of enumeration elements list.

UPDPOS : Update Position Registers
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : UPDPOS_0

No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER

0x1 : UPDPOS_1

Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER

End of enumeration elements list.

MOD : Enable Modulo Counting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : MOD_0

Disable modulo counting

0x1 : MOD_1

Enable modulo counting

End of enumeration elements list.

DIR : Count Direction Flag
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : DIR_0

Last count was in the down direction

0x1 : DIR_1

Last count was in the up direction

End of enumeration elements list.

RUIE : Roll-under Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : RUIE_0

Roll-under interrupt is disabled

0x1 : RUIE_1

Roll-under interrupt is enabled

End of enumeration elements list.

RUIRQ : Roll-under Interrupt Request
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : RUIRQ_0

No roll-under has occurred

0x1 : RUIRQ_1

Roll-under has occurred

End of enumeration elements list.

ROIE : Roll-over Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : ROIE_0

Roll-over interrupt is disabled

0x1 : ROIE_1

Roll-over interrupt is enabled

End of enumeration elements list.

ROIRQ : Roll-over Interrupt Request
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : ROIRQ_0

No roll-over has occurred

0x1 : ROIRQ_1

Roll-over has occurred

End of enumeration elements list.

REVMOD : Revolution Counter Modulus Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : REVMOD_0

Use INDEX pulse to increment/decrement revolution counter (REV).

0x1 : REVMOD_1

Use modulus counting roll-over/under to increment/decrement revolution counter (REV).

End of enumeration elements list.

OUTCTL : Output Control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : OUTCTL_0

POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP).

0x1 : OUTCTL_1

POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.

End of enumeration elements list.

SABIE : Simultaneous PHASEA and PHASEB Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SABIE_0

Simultaneous PHASEA and PHASEB change interrupt disabled.

0x1 : SABIE_1

Simultaneous PHASEA and PHASEB change interrupt enabled.

End of enumeration elements list.

SABIRQ : Simultaneous PHASEA and PHASEB Change Interrupt Request
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SABIRQ_0

No simultaneous change of PHASEA and PHASEB has occurred.

0x1 : SABIRQ_1

A simultaneous change of PHASEA and PHASEB has occurred.

End of enumeration elements list.


FILT

Input Filter Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILT FILT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILT_PER FILT_CNT

FILT_PER : Input Filter Sample Period
bits : 0 - 7 (8 bit)
access : read-write

FILT_CNT : Input Filter Sample Count
bits : 8 - 10 (3 bit)
access : read-write


UMOD

Upper Modulus Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UMOD UMOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD

MOD : This read/write register contains the upper (most significant) half of the modulus register
bits : 0 - 15 (16 bit)
access : read-write


LMOD

Lower Modulus Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMOD LMOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD

MOD : This read/write register contains the lower (least significant) half of the modulus register
bits : 0 - 15 (16 bit)
access : read-write


UCOMP

Upper Position Compare Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UCOMP UCOMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : This read/write register contains the upper (most significant) half of the position compare register
bits : 0 - 15 (16 bit)
access : read-write


LCOMP

Lower Position Compare Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCOMP LCOMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : This read/write register contains the lower (least significant) half of the position compare register
bits : 0 - 15 (16 bit)
access : read-write


WTR

Watchdog Timeout Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTR WTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG

WDOG : WDOG[15:0] is a binary representation of the number of clock cycles plus one that the watchdog timer counts before timing out and optionally generating an interrupt
bits : 0 - 15 (16 bit)
access : read-write


POSD

Position Difference Counter Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POSD POSD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSD

POSD : This read/write register contains the position change in value occurring between each read of the position register
bits : 0 - 15 (16 bit)
access : read-write


POSDH

Position Difference Hold Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

POSDH POSDH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSDH

POSDH : This read-only register contains a snapshot of the value of the POSD register
bits : 0 - 15 (16 bit)
access : read-only


REV

Revolution Counter Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REV REV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV

REV : This read/write register contains the current value of the revolution counter.
bits : 0 - 15 (16 bit)
access : read-write


REVH

Revolution Hold Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REVH REVH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REVH

REVH : This read-only register contains a snapshot of the value of the REV register.
bits : 0 - 15 (16 bit)
access : read-only


UPOS

Upper Position Counter Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPOS UPOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POS

POS : This read/write register contains the upper (most significant) half of the position counter
bits : 0 - 15 (16 bit)
access : read-write



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