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GPC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CNTR

IMR3

IMR4

ISR1

ISR2

ISR3

ISR4

IMR5

ISR5

IMR1

IMR2


CNTR

GPC Interface control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEGA_PDN_REQ MEGA_PUP_REQ PDRAM0_PGE

MEGA_PDN_REQ : MEGA domain power down request
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : MEGA_PDN_REQ_0

No Request

0x1 : MEGA_PDN_REQ_1

Request power down sequence

End of enumeration elements list.

MEGA_PUP_REQ : MEGA domain power up request
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : MEGA_PUP_REQ_0

No Request

0x1 : MEGA_PUP_REQ_1

Request power up sequence

End of enumeration elements list.

PDRAM0_PGE : FlexRAM PDRAM0 Power Gate Enable
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : PDRAM0_PGE_0

FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down.

0x1 : PDRAM0_PGE_1

FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down.

End of enumeration elements list.


IMR3

IRQ masking register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR3 IMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR3

IMR3 : IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write


IMR4

IRQ masking register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR4 IMR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR4

IMR4 : IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write


ISR1

IRQ status resister 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR1 ISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR1

ISR1 : IRQ[31:0] status, read only
bits : 0 - 31 (32 bit)
access : read-only


ISR2

IRQ status resister 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR2 ISR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR2

ISR2 : IRQ[63:32] status, read only
bits : 0 - 31 (32 bit)
access : read-only


ISR3

IRQ status resister 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR3 ISR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR3

ISR3 : IRQ[95:64] status, read only
bits : 0 - 31 (32 bit)
access : read-only


ISR4

IRQ status resister 4
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR4 ISR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR4

ISR4 : IRQ[127:96] status, read only
bits : 0 - 31 (32 bit)
access : read-only


IMR5

IRQ masking register 5
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR5 IMR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR5

IMR5 : IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write


ISR5

IRQ status resister 5
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR5 ISR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR4

ISR4 : IRQ[159:128] status, read only
bits : 0 - 31 (32 bit)
access : read-only


IMR1

IRQ masking register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR1 IMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR1

IMR1 : IRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write


IMR2

IRQ masking register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR2 IMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR2

IMR2 : IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write



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