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FLEXRAM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TCM_CTRL

INT_STATUS

INT_STAT_EN

INT_SIG_EN


TCM_CTRL

TCM CRTL Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCM_CTRL TCM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCM_WWAIT_EN TCM_RWAIT_EN FORCE_CLK_ON

TCM_WWAIT_EN : TCM Write Wait Mode Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TCM_WWAIT_EN_0

TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.

0x1 : TCM_WWAIT_EN_1

TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.

End of enumeration elements list.

TCM_RWAIT_EN : TCM Read Wait Mode Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : TCM_RWAIT_EN_0

TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.

0x1 : TCM_RWAIT_EN_1

TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.

End of enumeration elements list.

FORCE_CLK_ON : Force RAM Clock Always On
bits : 2 - 2 (1 bit)
access : read-write


INT_STATUS

Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS INT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITCM_ERR_STATUS DTCM_ERR_STATUS OCRAM_ERR_STATUS

ITCM_ERR_STATUS : ITCM Access Error Status
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : ITCM_ERR_STATUS_0

ITCM access error does not happen

0x1 : ITCM_ERR_STATUS_1

ITCM access error happens.

End of enumeration elements list.

DTCM_ERR_STATUS : DTCM Access Error Status
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DTCM_ERR_STATUS_0

DTCM access error does not happen

0x1 : DTCM_ERR_STATUS_1

DTCM access error happens.

End of enumeration elements list.

OCRAM_ERR_STATUS : OCRAM Access Error Status
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : OCRAM_ERR_STATUS_0

OCRAM access error does not happen

0x1 : OCRAM_ERR_STATUS_1

OCRAM access error happens.

End of enumeration elements list.


INT_STAT_EN

Interrupt Status Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STAT_EN INT_STAT_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITCM_ERR_STAT_EN DTCM_ERR_STAT_EN OCRAM_ERR_STAT_EN

ITCM_ERR_STAT_EN : ITCM Access Error Status Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : ITCM_ERR_STAT_EN_0

Masked

0x1 : ITCM_ERR_STAT_EN_1

Enabled

End of enumeration elements list.

DTCM_ERR_STAT_EN : DTCM Access Error Status Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DTCM_ERR_STAT_EN_0

Masked

0x1 : DTCM_ERR_STAT_EN_1

Enabled

End of enumeration elements list.

OCRAM_ERR_STAT_EN : OCRAM Access Error Status Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : OCRAM_ERR_STAT_EN_0

Masked

0x1 : OCRAM_ERR_STAT_EN_1

Enabled

End of enumeration elements list.


INT_SIG_EN

Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_SIG_EN INT_SIG_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITCM_ERR_SIG_EN DTCM_ERR_SIG_EN OCRAM_ERR_SIG_EN

ITCM_ERR_SIG_EN : ITCM Access Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : ITCM_ERR_SIG_EN_0

Masked

0x1 : ITCM_ERR_SIG_EN_1

Enabled

End of enumeration elements list.

DTCM_ERR_SIG_EN : DTCM Access Error Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DTCM_ERR_SIG_EN_0

Masked

0x1 : DTCM_ERR_SIG_EN_1

Enabled

End of enumeration elements list.

OCRAM_ERR_SIG_EN : OCRAM Access Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : OCRAM_ERR_SIG_EN_0

Masked

0x1 : OCRAM_ERR_SIG_EN_1

Enabled

End of enumeration elements list.



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