\n
address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
SRC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mask_wdog_rst : Mask wdog_rst_b source
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
0x5 : mask_wdog_rst_5
wdog_rst_b is masked
0xA : mask_wdog_rst_10
wdog_rst_b is not masked (default)
End of enumeration elements list.
core0_rst : Software reset for core0 only
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : core0_rst_0
do not assert core0 reset
0x1 : core0_rst_1
assert core0 reset
End of enumeration elements list.
core0_dbg_rst : Software reset for core0 debug only
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : core0_dbg_rst_0
do not assert core0 debug reset
0x1 : core0_dbg_rst_1
assert core0 debug reset
End of enumeration elements list.
dbg_rst_msk_pg : Do not assert debug resets after power gating event of core
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : dbg_rst_msk_pg_0
do not mask core debug resets (debug resets will be asserted after power gating event)
0x1 : dbg_rst_msk_pg_1
mask core debug resets (debug resets won't be asserted after power gating event)
End of enumeration elements list.
mask_wdog3_rst : Mask wdog3_rst_b source
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0x5 : mask_wdog3_rst_5
wdog3_rst_b is masked
0xA : mask_wdog3_rst_10
wdog3_rst_b is not masked
End of enumeration elements list.
SRC Boot Mode Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_CONFIG : SECONFIG[1] shows the state of the SECONFIG[1] fuse
bits : 0 - 1 (2 bit)
access : read-only
DIR_BT_DIS : DIR_BT_DIS shows the state of the DIR_BT_DIS fuse
bits : 3 - 3 (1 bit)
access : read-only
BT_FUSE_SEL : BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse
bits : 4 - 4 (1 bit)
access : read-only
BMOD : BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B
bits : 24 - 25 (2 bit)
access : read-only
SRC General Purpose Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERSISTENT_ENTRY0 : Holds entry function for core0 for waking-up from low power mode
bits : 0 - 31 (32 bit)
access : read-write
SRC General Purpose Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERSISTENT_ARG0 : Holds argument of entry function for core0 for waking-up from low power mode
bits : 0 - 31 (32 bit)
access : read-write
SRC General Purpose Register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 4
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 5
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 6
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 7
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 8
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC Boot Mode Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOOT_CFG1 : Refer to fusemap.
bits : 0 - 7 (8 bit)
access : read-only
BOOT_CFG2 : Refer to fusemap.
bits : 8 - 15 (8 bit)
access : read-only
BOOT_CFG3 : Refer to fusemap.
bits : 16 - 23 (8 bit)
access : read-only
BOOT_CFG4 : Refer to fusemap.
bits : 24 - 31 (8 bit)
access : read-only
SRC General Purpose Register 9
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 10
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC Reset Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ipp_reset_b : Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ipp_reset_b_0
Reset is not a result of ipp_reset_b pin.
0x1 : ipp_reset_b_1
Reset is a result of ipp_reset_b pin.
End of enumeration elements list.
lockup_sysresetreq : Indicates a reset has been caused by CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : lockup_sysresetreq_0
Reset is not a result of the mentioned case.
0x1 : lockup_sysresetreq_1
Reset is a result of the mentioned case.
End of enumeration elements list.
csu_reset_b : Indicates whether the reset was the result of the csu_reset_b input.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : csu_reset_b_0
Reset is not a result of the csu_reset_b event.
0x1 : csu_reset_b_1
Reset is a result of the csu_reset_b event.
End of enumeration elements list.
ipp_user_reset_b : Indicates whether the reset was the result of the ipp_user_reset_b qualified reset.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ipp_user_reset_b_0
Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
0x1 : ipp_user_reset_b_1
Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
End of enumeration elements list.
wdog_rst_b : IC Watchdog Time-out reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : wdog_rst_b_0
Reset is not a result of the watchdog time-out event.
0x1 : wdog_rst_b_1
Reset is a result of the watchdog time-out event.
End of enumeration elements list.
jtag_rst_b : HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : jtag_rst_b_0
Reset is not a result of HIGH-Z reset from JTAG.
0x1 : jtag_rst_b_1
Reset is a result of HIGH-Z reset from JTAG.
End of enumeration elements list.
jtag_sw_rst : JTAG software reset. Indicates whether the reset was the result of software reset from JTAG.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : jtag_sw_rst_0
Reset is not a result of software reset from JTAG.
0x1 : jtag_sw_rst_1
Reset is a result of software reset from JTAG.
End of enumeration elements list.
wdog3_rst_b : IC Watchdog3 Time-out reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : wdog3_rst_b_0
Reset is not a result of the watchdog3 time-out event.
0x1 : wdog3_rst_b_1
Reset is a result of the watchdog3 time-out event.
End of enumeration elements list.
tempsense_rst_b : Temper Sensor software reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : tempsense_rst_b_0
Reset is not a result of software reset from Temperature Sensor.
0x1 : tempsense_rst_b_1
Reset is a result of software reset from Temperature Sensor.
End of enumeration elements list.
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