Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Identification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0x1 : FEATURE_1
Standard feature set.
0x3 : FEATURE_3
Standard feature set with MODEM/IrDA support.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
LPUART Baud Rate Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBR : Baud Rate Modulo Divisor.
bits : 0 - 12 (13 bit)
access : read-write
SBNS : Stop Bit Number Select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SBNS_0
One stop bit.
0x1 : SBNS_1
Two stop bits.
End of enumeration elements list.
RXEDGIE : RX Input Active Edge Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : RXEDGIE_0
Hardware interrupts from STAT[RXEDGIF] are disabled.
0x1 : RXEDGIE_1
Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
End of enumeration elements list.
LBKDIE : LIN Break Detect Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LBKDIE_0
Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
0x1 : LBKDIE_1
Hardware interrupt requested when STAT[LBKDIF] flag is 1.
End of enumeration elements list.
RESYNCDIS : Resynchronization Disable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : RESYNCDIS_0
Resynchronization during received data word is supported
0x1 : RESYNCDIS_1
Resynchronization during received data word is disabled
End of enumeration elements list.
BOTHEDGE : Both Edge Sampling
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : BOTHEDGE_0
Receiver samples input data using the rising edge of the baud rate clock.
0x1 : BOTHEDGE_1
Receiver samples input data using the rising and falling edge of the baud rate clock.
End of enumeration elements list.
MATCFG : Match Configuration
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : MATCFG_0
Address Match Wakeup
0x1 : MATCFG_1
Idle Match Wakeup
0x2 : MATCFG_2
Match On and Match Off
0x3 : MATCFG_3
Enables RWU on Data Match and Match On/Off for transmitter CTS input
End of enumeration elements list.
RIDMAE : Receiver Idle DMA Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : RIDMAE_0
DMA request disabled.
0x1 : RIDMAE_1
DMA request enabled.
End of enumeration elements list.
RDMAE : Receiver Full DMA Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : RDMAE_0
DMA request disabled.
0x1 : RDMAE_1
DMA request enabled.
End of enumeration elements list.
TDMAE : Transmitter DMA Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TDMAE_0
DMA request disabled.
0x1 : TDMAE_1
DMA request enabled.
End of enumeration elements list.
OSR : Oversampling Ratio
bits : 24 - 28 (5 bit)
access : read-write
Enumeration:
0 : OSR_0
Writing 0 to this field will result in an oversampling ratio of 16
0x3 : OSR_3
Oversampling ratio of 4, requires BOTHEDGE to be set.
0x4 : OSR_4
Oversampling ratio of 5, requires BOTHEDGE to be set.
0x5 : OSR_5
Oversampling ratio of 6, requires BOTHEDGE to be set.
0x6 : OSR_6
Oversampling ratio of 7, requires BOTHEDGE to be set.
0x7 : OSR_7
Oversampling ratio of 8.
0x8 : OSR_8
Oversampling ratio of 9.
0x9 : OSR_9
Oversampling ratio of 10.
0xA : OSR_10
Oversampling ratio of 11.
0xB : OSR_11
Oversampling ratio of 12.
0xC : OSR_12
Oversampling ratio of 13.
0xD : OSR_13
Oversampling ratio of 14.
0xE : OSR_14
Oversampling ratio of 15.
0xF : OSR_15
Oversampling ratio of 16.
0x10 : OSR_16
Oversampling ratio of 17.
0x11 : OSR_17
Oversampling ratio of 18.
0x12 : OSR_18
Oversampling ratio of 19.
0x13 : OSR_19
Oversampling ratio of 20.
0x14 : OSR_20
Oversampling ratio of 21.
0x15 : OSR_21
Oversampling ratio of 22.
0x16 : OSR_22
Oversampling ratio of 23.
0x17 : OSR_23
Oversampling ratio of 24.
0x18 : OSR_24
Oversampling ratio of 25.
0x19 : OSR_25
Oversampling ratio of 26.
0x1A : OSR_26
Oversampling ratio of 27.
0x1B : OSR_27
Oversampling ratio of 28.
0x1C : OSR_28
Oversampling ratio of 29.
0x1D : OSR_29
Oversampling ratio of 30.
0x1E : OSR_30
Oversampling ratio of 31.
0x1F : OSR_31
Oversampling ratio of 32.
End of enumeration elements list.
M10 : 10-bit Mode select
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : M10_0
Receiver and transmitter use 7-bit to 9-bit data characters.
0x1 : M10_1
Receiver and transmitter use 10-bit data characters.
End of enumeration elements list.
MAEN2 : Match Address Mode Enable 2
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : MAEN2_0
Normal operation.
0x1 : MAEN2_1
Enables automatic address matching or data matching mode for MATCH[MA2].
End of enumeration elements list.
MAEN1 : Match Address Mode Enable 1
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : MAEN1_0
Normal operation.
0x1 : MAEN1_1
Enables automatic address matching or data matching mode for MATCH[MA1].
End of enumeration elements list.
LPUART Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA2F : Match 2 Flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : MA2F_0
Received data is not equal to MA2
0x1 : MA2F_1
Received data is equal to MA2
End of enumeration elements list.
MA1F : Match 1 Flag
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : MA1F_0
Received data is not equal to MA1
0x1 : MA1F_1
Received data is equal to MA1
End of enumeration elements list.
PF : Parity Error Flag
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : PF_0
No parity error.
0x1 : PF_1
Parity error.
End of enumeration elements list.
FE : Framing Error Flag
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : FE_0
No framing error detected. This does not guarantee the framing is correct.
0x1 : FE_1
Framing error.
End of enumeration elements list.
NF : Noise Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NF_0
No noise detected.
0x1 : NF_1
Noise detected in the received character in the DATA register.
End of enumeration elements list.
OR : Receiver Overrun Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : OR_0
No overrun.
0x1 : OR_1
Receive overrun (new LPUART data lost).
End of enumeration elements list.
IDLE : Idle Line Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : IDLE_0
No idle line detected.
0x1 : IDLE_1
Idle line was detected.
End of enumeration elements list.
RDRF : Receive Data Register Full Flag
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : RDRF_0
Receive data buffer empty.
0x1 : RDRF_1
Receive data buffer full.
End of enumeration elements list.
TC : Transmission Complete Flag
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : TC_0
Transmitter active (sending data, a preamble, or a break).
0x1 : TC_1
Transmitter idle (transmission activity complete).
End of enumeration elements list.
TDRE : Transmit Data Register Empty Flag
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : TDRE_0
Transmit data buffer full.
0x1 : TDRE_1
Transmit data buffer empty.
End of enumeration elements list.
RAF : Receiver Active Flag
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : RAF_0
LPUART receiver idle waiting for a start bit.
0x1 : RAF_1
LPUART receiver active (RXD input not idle).
End of enumeration elements list.
LBKDE : LIN Break Detection Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : LBKDE_0
LIN break detect is disabled, normal break character can be detected.
0x1 : LBKDE_1
LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
End of enumeration elements list.
BRK13 : Break Character Generation Length
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : BRK13_0
Break character is transmitted with length of 9 to 13 bit times.
0x1 : BRK13_1
Break character is transmitted with length of 12 to 15 bit times.
End of enumeration elements list.
RWUID : Receive Wake Up Idle Detect
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : RWUID_0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match.
0x1 : RWUID_1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.
End of enumeration elements list.
RXINV : Receive Data Inversion
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : RXINV_0
Receive data not inverted.
0x1 : RXINV_1
Receive data inverted.
End of enumeration elements list.
MSBF : MSB First
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : MSBF_0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
0x1 : MSBF_1
MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
End of enumeration elements list.
RXEDGIF : RXD Pin Active Edge Interrupt Flag
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RXEDGIF_0
No active edge on the receive pin has occurred.
0x1 : RXEDGIF_1
An active edge on the receive pin has occurred.
End of enumeration elements list.
LBKDIF : LIN Break Detect Interrupt Flag
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LBKDIF_0
No LIN break character has been detected.
0x1 : LBKDIF_1
LIN break character has been detected.
End of enumeration elements list.
LPUART Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT : Parity Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PT_0
Even parity.
0x1 : PT_1
Odd parity.
End of enumeration elements list.
PE : Parity Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
No hardware parity generation or checking.
0x1 : PE_1
Parity enabled.
End of enumeration elements list.
ILT : Idle Line Type Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ILT_0
Idle character bit count starts after start bit.
0x1 : ILT_1
Idle character bit count starts after stop bit.
End of enumeration elements list.
WAKE : Receiver Wakeup Method Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : WAKE_0
Configures RWU for idle-line wakeup.
0x1 : WAKE_1
Configures RWU with address-mark wakeup.
End of enumeration elements list.
M : 9-Bit or 8-Bit Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : M_0
Receiver and transmitter use 8-bit data characters.
0x1 : M_1
Receiver and transmitter use 9-bit data characters.
End of enumeration elements list.
RSRC : Receiver Source Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RSRC_0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
0x1 : RSRC_1
Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
End of enumeration elements list.
DOZEEN : Doze Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DOZEEN_0
LPUART is enabled in Doze mode.
0x1 : DOZEEN_1
LPUART is disabled in Doze mode.
End of enumeration elements list.
LOOPS : Loop Mode Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LOOPS_0
Normal operation - RXD and TXD use separate pins.
0x1 : LOOPS_1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
End of enumeration elements list.
IDLECFG : Idle Configuration
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : IDLECFG_0
1 idle character
0x1 : IDLECFG_1
2 idle characters
0x2 : IDLECFG_2
4 idle characters
0x3 : IDLECFG_3
8 idle characters
0x4 : IDLECFG_4
16 idle characters
0x5 : IDLECFG_5
32 idle characters
0x6 : IDLECFG_6
64 idle characters
0x7 : IDLECFG_7
128 idle characters
End of enumeration elements list.
M7 : 7-Bit Mode Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : M7_0
Receiver and transmitter use 8-bit to 10-bit data characters.
0x1 : M7_1
Receiver and transmitter use 7-bit data characters.
End of enumeration elements list.
MA2IE : Match 2 Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : MA2IE_0
MA2F interrupt disabled
0x1 : MA2IE_1
MA2F interrupt enabled
End of enumeration elements list.
MA1IE : Match 1 Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : MA1IE_0
MA1F interrupt disabled
0x1 : MA1IE_1
MA1F interrupt enabled
End of enumeration elements list.
SBK : Send Break
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SBK_0
Normal transmitter operation.
0x1 : SBK_1
Queue break character(s) to be sent.
End of enumeration elements list.
RWU : Receiver Wakeup Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : RWU_0
Normal receiver operation.
0x1 : RWU_1
LPUART receiver in standby waiting for wakeup condition.
End of enumeration elements list.
RE : Receiver Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : RE_0
Receiver disabled.
0x1 : RE_1
Receiver enabled.
End of enumeration elements list.
TE : Transmitter Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : TE_0
Transmitter disabled.
0x1 : TE_1
Transmitter enabled.
End of enumeration elements list.
ILIE : Idle Line Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : ILIE_0
Hardware interrupts from IDLE disabled; use polling.
0x1 : ILIE_1
Hardware interrupt requested when IDLE flag is 1.
End of enumeration elements list.
RIE : Receiver Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : RIE_0
Hardware interrupts from RDRF disabled; use polling.
0x1 : RIE_1
Hardware interrupt requested when RDRF flag is 1.
End of enumeration elements list.
TCIE : Transmission Complete Interrupt Enable for
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TCIE_0
Hardware interrupts from TC disabled; use polling.
0x1 : TCIE_1
Hardware interrupt requested when TC flag is 1.
End of enumeration elements list.
TIE : Transmit Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIE_0
Hardware interrupts from TDRE disabled; use polling.
0x1 : TIE_1
Hardware interrupt requested when TDRE flag is 1.
End of enumeration elements list.
PEIE : Parity Error Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : PEIE_0
PF interrupts disabled; use polling).
0x1 : PEIE_1
Hardware interrupt requested when PF is set.
End of enumeration elements list.
FEIE : Framing Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : FEIE_0
FE interrupts disabled; use polling.
0x1 : FEIE_1
Hardware interrupt requested when FE is set.
End of enumeration elements list.
NEIE : Noise Error Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NEIE_0
NF interrupts disabled; use polling.
0x1 : NEIE_1
Hardware interrupt requested when NF is set.
End of enumeration elements list.
ORIE : Overrun Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : ORIE_0
OR interrupts disabled; use polling.
0x1 : ORIE_1
Hardware interrupt requested when OR is set.
End of enumeration elements list.
TXINV : Transmit Data Inversion
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : TXINV_0
Transmit data not inverted.
0x1 : TXINV_1
Transmit data inverted.
End of enumeration elements list.
TXDIR : TXD Pin Direction in Single-Wire Mode
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : TXDIR_0
TXD pin is an input in single-wire mode.
0x1 : TXDIR_1
TXD pin is an output in single-wire mode.
End of enumeration elements list.
R9T8 : Receive Bit 9 / Transmit Bit 8
bits : 30 - 30 (1 bit)
access : read-write
R8T9 : Receive Bit 8 / Transmit Bit 9
bits : 31 - 31 (1 bit)
access : read-write
LPUART Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R0T0 : R0T0
bits : 0 - 0 (1 bit)
access : read-write
R1T1 : R1T1
bits : 1 - 1 (1 bit)
access : read-write
R2T2 : R2T2
bits : 2 - 2 (1 bit)
access : read-write
R3T3 : R3T3
bits : 3 - 3 (1 bit)
access : read-write
R4T4 : R4T4
bits : 4 - 4 (1 bit)
access : read-write
R5T5 : R5T5
bits : 5 - 5 (1 bit)
access : read-write
R6T6 : R6T6
bits : 6 - 6 (1 bit)
access : read-write
R7T7 : R7T7
bits : 7 - 7 (1 bit)
access : read-write
R8T8 : R8T8
bits : 8 - 8 (1 bit)
access : read-write
R9T9 : R9T9
bits : 9 - 9 (1 bit)
access : read-write
IDLINE : Idle Line
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : IDLINE_0
Receiver was not idle before receiving this character.
0x1 : IDLINE_1
Receiver was idle before receiving this character.
End of enumeration elements list.
RXEMPT : Receive Buffer Empty
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : RXEMPT_0
Receive buffer contains valid data.
0x1 : RXEMPT_1
Receive buffer is empty, data returned on read is not valid.
End of enumeration elements list.
FRETSC : Frame Error / Transmit Special Character
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : FRETSC_0
The dataword was received without a frame error on read, or transmit a normal character on write.
0x1 : FRETSC_1
The dataword was received with a frame error, or transmit an idle or break character on transmit.
End of enumeration elements list.
PARITYE : PARITYE
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : PARITYE_0
The dataword was received without a parity error.
0x1 : PARITYE_1
The dataword was received with a parity error.
End of enumeration elements list.
NOISY : NOISY
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : NOISY_0
The dataword was received without noise.
0x1 : NOISY_1
The data was received with noise.
End of enumeration elements list.
LPUART Match Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA1 : Match Address 1
bits : 0 - 9 (10 bit)
access : read-write
MA2 : Match Address 2
bits : 16 - 25 (10 bit)
access : read-write
LPUART Modem IrDA Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTSE : Transmitter clear-to-send enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TXCTSE_0
CTS has no effect on the transmitter.
0x1 : TXCTSE_1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
End of enumeration elements list.
TXRTSE : Transmitter request-to-send enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TXRTSE_0
The transmitter has no effect on RTS.
0x1 : TXRTSE_1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
End of enumeration elements list.
TXRTSPOL : Transmitter request-to-send polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TXRTSPOL_0
Transmitter RTS is active low.
0x1 : TXRTSPOL_1
Transmitter RTS is active high.
End of enumeration elements list.
RXRTSE : Receiver request-to-send enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RXRTSE_0
The receiver has no effect on RTS.
0x1 : RXRTSE_1
RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
End of enumeration elements list.
TXCTSC : Transmit CTS Configuration
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : TXCTSC_0
CTS input is sampled at the start of each character.
0x1 : TXCTSC_1
CTS input is sampled when the transmitter is idle.
End of enumeration elements list.
TXCTSSRC : Transmit CTS Source
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : TXCTSSRC_0
CTS input is the CTS_B pin.
0x1 : TXCTSSRC_1
CTS input is the inverted Receiver Match result.
End of enumeration elements list.
RTSWATER : Receive RTS Configuration
bits : 8 - 9 (2 bit)
access : read-write
TNP : Transmitter narrow pulse
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : TNP_0
1/OSR.
0x1 : TNP_1
2/OSR.
0x2 : TNP_2
3/OSR.
0x3 : TNP_3
4/OSR.
End of enumeration elements list.
IREN : Infrared enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : IREN_0
IR disabled.
0x1 : IREN_1
IR enabled.
End of enumeration elements list.
LPUART FIFO Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFIFOSIZE : Receive FIFO Buffer Depth
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : RXFIFOSIZE_0
Receive FIFO/Buffer depth = 1 dataword.
0x1 : RXFIFOSIZE_1
Receive FIFO/Buffer depth = 4 datawords.
0x2 : RXFIFOSIZE_2
Receive FIFO/Buffer depth = 8 datawords.
0x3 : RXFIFOSIZE_3
Receive FIFO/Buffer depth = 16 datawords.
0x4 : RXFIFOSIZE_4
Receive FIFO/Buffer depth = 32 datawords.
0x5 : RXFIFOSIZE_5
Receive FIFO/Buffer depth = 64 datawords.
0x6 : RXFIFOSIZE_6
Receive FIFO/Buffer depth = 128 datawords.
0x7 : RXFIFOSIZE_7
Receive FIFO/Buffer depth = 256 datawords.
End of enumeration elements list.
RXFE : Receive FIFO Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RXFE_0
Receive FIFO is not enabled. Buffer is depth 1.
0x1 : RXFE_1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
End of enumeration elements list.
TXFIFOSIZE : Transmit FIFO Buffer Depth
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
0 : TXFIFOSIZE_0
Transmit FIFO/Buffer depth = 1 dataword.
0x1 : TXFIFOSIZE_1
Transmit FIFO/Buffer depth = 4 datawords.
0x2 : TXFIFOSIZE_2
Transmit FIFO/Buffer depth = 8 datawords.
0x3 : TXFIFOSIZE_3
Transmit FIFO/Buffer depth = 16 datawords.
0x4 : TXFIFOSIZE_4
Transmit FIFO/Buffer depth = 32 datawords.
0x5 : TXFIFOSIZE_5
Transmit FIFO/Buffer depth = 64 datawords.
0x6 : TXFIFOSIZE_6
Transmit FIFO/Buffer depth = 128 datawords.
0x7 : TXFIFOSIZE_7
Transmit FIFO/Buffer depth = 256 datawords
End of enumeration elements list.
TXFE : Transmit FIFO Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TXFE_0
Transmit FIFO is not enabled. Buffer is depth 1.
0x1 : TXFE_1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
End of enumeration elements list.
RXUFE : Receive FIFO Underflow Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RXUFE_0
RXUF flag does not generate an interrupt to the host.
0x1 : RXUFE_1
RXUF flag generates an interrupt to the host.
End of enumeration elements list.
TXOFE : Transmit FIFO Overflow Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : TXOFE_0
TXOF flag does not generate an interrupt to the host.
0x1 : TXOFE_1
TXOF flag generates an interrupt to the host.
End of enumeration elements list.
RXIDEN : Receiver Idle Empty Enable
bits : 10 - 12 (3 bit)
access : read-write
Enumeration:
0 : RXIDEN_0
Disable RDRF assertion due to partially filled FIFO when receiver is idle.
0x1 : RXIDEN_1
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
0x2 : RXIDEN_2
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
0x3 : RXIDEN_3
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
0x4 : RXIDEN_4
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
0x5 : RXIDEN_5
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
0x6 : RXIDEN_6
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
0x7 : RXIDEN_7
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
End of enumeration elements list.
RXFLUSH : Receive FIFO/Buffer Flush
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : RXFLUSH_0
No flush operation occurs.
0x1 : RXFLUSH_1
All data in the receive FIFO/buffer is cleared out.
End of enumeration elements list.
TXFLUSH : Transmit FIFO/Buffer Flush
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : TXFLUSH_0
No flush operation occurs.
0x1 : TXFLUSH_1
All data in the transmit FIFO/Buffer is cleared out.
End of enumeration elements list.
RXUF : Receiver Buffer Underflow Flag
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : RXUF_0
No receive buffer underflow has occurred since the last time the flag was cleared.
0x1 : RXUF_1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
TXOF : Transmitter Buffer Overflow Flag
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : TXOF_0
No transmit buffer overflow has occurred since the last time the flag was cleared.
0x1 : TXOF_1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
RXEMPT : Receive Buffer/FIFO Empty
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : RXEMPT_0
Receive buffer is not empty.
0x1 : RXEMPT_1
Receive buffer is empty.
End of enumeration elements list.
TXEMPT : Transmit Buffer/FIFO Empty
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : TXEMPT_0
Transmit buffer is not empty.
0x1 : TXEMPT_1
Transmit buffer is empty.
End of enumeration elements list.
LPUART Watermark Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXWATER : Transmit Watermark
bits : 0 - 1 (2 bit)
access : read-write
TXCOUNT : Transmit Counter
bits : 8 - 10 (3 bit)
access : read-only
RXWATER : Receive Watermark
bits : 16 - 17 (2 bit)
access : read-write
RXCOUNT : Receive Counter
bits : 24 - 26 (3 bit)
access : read-only
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFIFO : Transmit FIFO Size
bits : 0 - 7 (8 bit)
access : read-only
RXFIFO : Receive FIFO Size
bits : 8 - 15 (8 bit)
access : read-only
LPUART Global Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RST_0
Module is not reset.
0x1 : RST_1
Module is reset.
End of enumeration elements list.
LPUART Pin Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : Trigger Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRGSEL_0
Input trigger is disabled.
0x1 : TRGSEL_1
Input trigger is used instead of RXD pin input.
0x2 : TRGSEL_2
Input trigger is used instead of CTS_B pin input.
0x3 : TRGSEL_3
Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.