Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Module Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : read-write
MDIS : Module Disable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : MDIS_0
Module enabled
0x1 : MDIS_1
Module disabled.
End of enumeration elements list.
DQSMD : DQS (read strobe) mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DQSMD_0
Dummy read strobe loopbacked internally
0x1 : DQSMD_1
Dummy read strobe loopbacked from DQS pad
End of enumeration elements list.
WPOL0 : WAIT/RDY# polarity for NOR/PSRAM
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : WPOL0_0
Low active
0x1 : WPOL0_1
High active
End of enumeration elements list.
WPOL1 : WAIT/RDY# polarity for NAND
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : WPOL1_0
Low active
0x1 : WPOL1_1
High active
End of enumeration elements list.
CTO : Command Execution timeout cycles
bits : 16 - 23 (8 bit)
access : read-write
BTO : Bus timeout cycles
bits : 24 - 28 (5 bit)
access : read-write
Enumeration:
0 : BTO_0
255*1
0x1 : BTO_1
255*2 - 255*2^30
0x2 : BTO_2
255*2 - 255*2^30
0x3 : BTO_3
255*2 - 255*2^30
0x4 : BTO_4
255*2 - 255*2^30
0x5 : BTO_5
255*2 - 255*2^30
0x6 : BTO_6
255*2 - 255*2^30
0x7 : BTO_7
255*2 - 255*2^30
0x8 : BTO_8
255*2 - 255*2^30
0x9 : BTO_9
255*2 - 255*2^30
0x1F : BTO_31
255*2^31
End of enumeration elements list.
Base Register 0 (For SDRAM CS0 device)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Base Register 1 (For SDRAM CS1 device)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Base Register 2 (For SDRAM CS2 device)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Base Register 3 (For SDRAM CS3 device)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Base Register 4 (For NAND device)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Base Register 5 (For NOR device)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Base Register 6 (For PSRAM device)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Base Register 8 (For NAND device)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
MS : Memory size
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : MS_0
4KB
0x1 : MS_1
8KB
0x2 : MS_2
16KB
0x3 : MS_3
32KB
0x4 : MS_4
64KB
0x5 : MS_5
128KB
0x6 : MS_6
256KB
0x7 : MS_7
512KB
0x8 : MS_8
1MB
0x9 : MS_9
2MB
0xA : MS_10
4MB
0xB : MS_11
8MB
0xC : MS_12
16MB
0xD : MS_13
32MB
0xE : MS_14
64MB
0xF : MS_15
128MB
0x10 : MS_16
256MB
0x11 : MS_17
512MB
0x12 : MS_18
1GB
0x13 : MS_19
2GB
0x14 : MS_20
4GB
0x15 : MS_21
4GB
0x16 : MS_22
4GB
0x17 : MS_23
4GB
0x18 : MS_24
4GB
0x19 : MS_25
4GB
0x1A : MS_26
4GB
0x1B : MS_27
4GB
0x1C : MS_28
4GB
0x1D : MS_29
4GB
0x1E : MS_30
4GB
0x1F : MS_31
4GB
End of enumeration elements list.
BA : Base Address
bits : 12 - 31 (20 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPCMDDONEEN : IP command done interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
IPCMDERREN : IP command error interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
AXICMDERREN : AXI command error interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
AXIBUSERREN : AXI bus error interrupt enable
bits : 3 - 3 (1 bit)
access : read-write
NDPAGEENDEN : This bit enable/disable the NDPAGEEND interrupt generation.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NDPAGEENDEN_0
Disable
0x1 : NDPAGEENDEN_1
Enable
End of enumeration elements list.
NDNOPENDEN : This bit enable/disable the NDNOPEND interrupt generation.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NDNOPENDEN_0
Disable
0x1 : NDNOPENDEN_1
Enable
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPCMDDONE : IP command normal done interrupt
bits : 0 - 0 (1 bit)
access : read-write
IPCMDERR : IP command error done interrupt
bits : 1 - 1 (1 bit)
access : read-write
AXICMDERR : AXI command error interrupt
bits : 2 - 2 (1 bit)
access : read-write
AXIBUSERR : AXI bus error interrupt
bits : 3 - 3 (1 bit)
access : read-write
NDPAGEEND : This interrupt is generated when the last address of one page in NAND device is written by AXI command
bits : 4 - 4 (1 bit)
access : read-write
NDNOPEND : This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface.
bits : 5 - 5 (1 bit)
access : read-write
IO Mux Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_A8 : SEMC_A8 output selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : MUX_A8_0
SDRAM Address bit (A8)
0x1 : MUX_A8_1
NAND CE#
0x2 : MUX_A8_2
NOR CE#
0x3 : MUX_A8_3
PSRAM CE#
0x4 : MUX_A8_4
DBI CSX
0x5 : MUX_A8_5
SDRAM Address bit (A8)
0x6 : MUX_A8_6
SDRAM Address bit (A8)
0x7 : MUX_A8_7
SDRAM Address bit (A8)
End of enumeration elements list.
MUX_CSX0 : SEMC_CSX0 output selection
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : MUX_CSX0_0
NOR/PSRAM Address bit 24 (A24)
0x1 : MUX_CSX0_1
SDRAM CS1
0x2 : MUX_CSX0_2
SDRAM CS2
0x3 : MUX_CSX0_3
SDRAM CS3
0x4 : MUX_CSX0_4
NAND CE#
0x5 : MUX_CSX0_5
NOR CE#
0x6 : MUX_CSX0_6
PSRAM CE#
0x7 : MUX_CSX0_7
DBI CSX
End of enumeration elements list.
MUX_CSX1 : SEMC_CSX1 output selection
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : MUX_CSX1_0
NOR/PSRAM Address bit 25 (A25)
0x1 : MUX_CSX1_1
SDRAM CS1
0x2 : MUX_CSX1_2
SDRAM CS2
0x3 : MUX_CSX1_3
SDRAM CS3
0x4 : MUX_CSX1_4
NAND CE#
0x5 : MUX_CSX1_5
NOR CE#
0x6 : MUX_CSX1_6
PSRAM CE#
0x7 : MUX_CSX1_7
DBI CSX
End of enumeration elements list.
MUX_CSX2 : SEMC_CSX2 output selection
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : MUX_CSX2_0
NOR/PSRAM Address bit 26 (A26)
0x1 : MUX_CSX2_1
SDRAM CS1
0x2 : MUX_CSX2_2
SDRAM CS2
0x3 : MUX_CSX2_3
SDRAM CS3
0x4 : MUX_CSX2_4
NAND CE#
0x5 : MUX_CSX2_5
NOR CE#
0x6 : MUX_CSX2_6
PSRAM CE#
0x7 : MUX_CSX2_7
DBI CSX
End of enumeration elements list.
MUX_CSX3 : SEMC_CSX3 output selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : MUX_CSX3_0
NOR/PSRAM Address bit 27 (A27)
0x1 : MUX_CSX3_1
SDRAM CS1
0x2 : MUX_CSX3_2
SDRAM CS2
0x3 : MUX_CSX3_3
SDRAM CS3
0x4 : MUX_CSX3_4
NAND CE#
0x5 : MUX_CSX3_5
NOR CE#
0x6 : MUX_CSX3_6
PSRAM CE#
0x7 : MUX_CSX3_7
DBI CSX
End of enumeration elements list.
MUX_RDY : SEMC_RDY function selection
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : MUX_RDY_0
NAND Ready/Wait# input
0x1 : MUX_RDY_1
SDRAM CS1
0x2 : MUX_RDY_2
SDRAM CS2
0x3 : MUX_RDY_3
SDRAM CS3
0x4 : MUX_RDY_4
NOR CE#
0x5 : MUX_RDY_5
PSRAM CE#
0x6 : MUX_RDY_6
DBI CSX
0x7 : MUX_RDY_7
NOR/PSRAM Address bit 27
End of enumeration elements list.
SDRAM control register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Port Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
8bit
0x1 : PS_1
16bit
End of enumeration elements list.
BL : Burst Length
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : BL_0
1
0x1 : BL_1
2
0x2 : BL_2
4
0x3 : BL_3
8
0x4 : BL_4
8
0x5 : BL_5
8
0x6 : BL_6
8
0x7 : BL_7
8
End of enumeration elements list.
COL : Column address bit number
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : COL_0
12 bit
0x1 : COL_1
11 bit
0x2 : COL_2
10 bit
0x3 : COL_3
9 bit
End of enumeration elements list.
CL : CAS Latency
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : CL_0
1
0x1 : CL_1
1
0x2 : CL_2
2
0x3 : CL_3
3
End of enumeration elements list.
SDRAM control register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE2ACT : PRECHARGE to ACT/Refresh wait time
bits : 0 - 3 (4 bit)
access : read-write
ACT2RW : ACT to Read/Write wait time
bits : 4 - 7 (4 bit)
access : read-write
RFRC : Refresh recovery time
bits : 8 - 12 (5 bit)
access : read-write
WRC : Write recovery time
bits : 13 - 15 (3 bit)
access : read-write
CKEOFF : CKE OFF minimum time
bits : 16 - 19 (4 bit)
access : read-write
ACT2PRE : ACT to Precharge minimum time
bits : 20 - 23 (4 bit)
access : read-write
SDRAM control register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRRC : Self Refresh Recovery time
bits : 0 - 7 (8 bit)
access : read-write
REF2REF : Refresh to Refresh wait time
bits : 8 - 15 (8 bit)
access : read-write
ACT2ACT : ACT to ACT wait time
bits : 16 - 23 (8 bit)
access : read-write
ITO : SDRAM Idle timeout
bits : 24 - 31 (8 bit)
access : read-write
Enumeration:
0 : ITO_0
IDLE timeout period is 256*Prescale period.
0x1 : ITO_1
IDLE timeout period is ITO*Prescale period.
0x2 : ITO_2
IDLE timeout period is ITO*Prescale period.
0x3 : ITO_3
IDLE timeout period is ITO*Prescale period.
0x4 : ITO_4
IDLE timeout period is ITO*Prescale period.
0x5 : ITO_5
IDLE timeout period is ITO*Prescale period.
0x6 : ITO_6
IDLE timeout period is ITO*Prescale period.
0x7 : ITO_7
IDLE timeout period is ITO*Prescale period.
0x8 : ITO_8
IDLE timeout period is ITO*Prescale period.
0x9 : ITO_9
IDLE timeout period is ITO*Prescale period.
End of enumeration elements list.
SDRAM control register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REN : Refresh enable
bits : 0 - 0 (1 bit)
access : read-write
REBL : Refresh burst length
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0 : REBL_0
1
0x1 : REBL_1
2
0x2 : REBL_2
3
0x3 : REBL_3
4
0x4 : REBL_4
5
0x5 : REBL_5
6
0x6 : REBL_6
7
0x7 : REBL_7
8
End of enumeration elements list.
PRESCALE : Prescaler timer period
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0 : PRESCALE_0
256*16 cycle
0x1 : PRESCALE_1
PRESCALE*16 cycle
0x2 : PRESCALE_2
PRESCALE*16 cycle
0x3 : PRESCALE_3
PRESCALE*16 cycle
0x4 : PRESCALE_4
PRESCALE*16 cycle
0x5 : PRESCALE_5
PRESCALE*16 cycle
0x6 : PRESCALE_6
PRESCALE*16 cycle
0x7 : PRESCALE_7
PRESCALE*16 cycle
0x8 : PRESCALE_8
PRESCALE*16 cycle
0x9 : PRESCALE_9
PRESCALE*16 cycle
End of enumeration elements list.
RT : Refresh timer period
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : RT_0
256*Prescaler period
0x1 : RT_1
RT*Prescaler period
0x2 : RT_2
RT*Prescaler period
0x3 : RT_3
RT*Prescaler period
0x4 : RT_4
RT*Prescaler period
0x5 : RT_5
RT*Prescaler period
0x6 : RT_6
RT*Prescaler period
0x7 : RT_7
RT*Prescaler period
0x8 : RT_8
RT*Prescaler period
0x9 : RT_9
RT*Prescaler period
End of enumeration elements list.
UT : Refresh urgent threshold
bits : 24 - 31 (8 bit)
access : read-write
Enumeration:
0 : UT_0
256*Prescaler period
0x1 : UT_1
UT*Prescaler period
0x2 : UT_2
UT*Prescaler period
0x3 : UT_3
UT*Prescaler period
0x4 : UT_4
UT*Prescaler period
0x5 : UT_5
UT*Prescaler period
0x6 : UT_6
UT*Prescaler period
0x7 : UT_7
UT*Prescaler period
0x8 : UT_8
UT*Prescaler period
0x9 : UT_9
UT*Prescaler period
End of enumeration elements list.
NAND control register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Port Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
8bit
0x1 : PS_1
16bit
End of enumeration elements list.
BL : Burst Length
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : BL_0
1
0x1 : BL_1
2
0x2 : BL_2
4
0x3 : BL_3
8
0x4 : BL_4
16
0x5 : BL_5
32
0x6 : BL_6
64
0x7 : BL_7
64
End of enumeration elements list.
EDO : EDO mode enabled
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : EDO_0
EDO mode disabled
0x1 : EDO_1
EDO mode enabled
End of enumeration elements list.
COL : Column address bit number
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : COL_0
16
0x1 : COL_1
15
0x2 : COL_2
14
0x3 : COL_3
13
0x4 : COL_4
12
0x5 : COL_5
11
0x6 : COL_6
10
0x7 : COL_7
9
End of enumeration elements list.
NAND control register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CES : CE setup time
bits : 0 - 3 (4 bit)
access : read-write
CEH : CE hold time
bits : 4 - 7 (4 bit)
access : read-write
WEL : WE# LOW time
bits : 8 - 11 (4 bit)
access : read-write
WEH : WE# HIGH time
bits : 12 - 15 (4 bit)
access : read-write
REL : RE# LOW time
bits : 16 - 19 (4 bit)
access : read-write
REH : RE# HIGH time
bits : 20 - 23 (4 bit)
access : read-write
TA : Turnaround time
bits : 24 - 27 (4 bit)
access : read-write
CEITV : CE# interval time
bits : 28 - 31 (4 bit)
access : read-write
NAND control register 2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWHR : WE# HIGH to RE# LOW wait time
bits : 0 - 5 (6 bit)
access : read-write
TRHW : RE# HIGH to WE# LOW wait time
bits : 6 - 11 (6 bit)
access : read-write
TADL : ALE to WRITE Data start wait time
bits : 12 - 17 (6 bit)
access : read-write
TRR : Ready to RE# LOW min wait time
bits : 18 - 23 (6 bit)
access : read-write
TWB : WE# HIGH to busy wait time
bits : 24 - 29 (6 bit)
access : read-write
NAND control register 3
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDOPT1 : NAND option bit 1
bits : 0 - 0 (1 bit)
access : read-write
NDOPT2 : NAND option bit 2
bits : 1 - 1 (1 bit)
access : read-write
NDOPT3 : NAND option bit 3
bits : 2 - 2 (1 bit)
access : read-write
NOR control register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Port Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
8bit
0x1 : PS_1
16bit
End of enumeration elements list.
BL : Burst Length
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : BL_0
1
0x1 : BL_1
2
0x2 : BL_2
4
0x3 : BL_3
8
0x4 : BL_4
16
0x5 : BL_5
32
0x6 : BL_6
64
0x7 : BL_7
64
End of enumeration elements list.
AM : Address Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : AM_0
Address/Data MUX mode
0x1 : AM_1
Advanced Address/Data MUX mode
0x2 : AM_2
Address/Data non-MUX mode
0x3 : AM_3
Address/Data non-MUX mode
End of enumeration elements list.
ADVP : ADV# polarity
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : ADVP_0
ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW.
0x1 : ADVP_1
ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.
End of enumeration elements list.
COL : Column Address bit width
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : COL_0
12 Bits
0x1 : COL_1
11 Bits
0x2 : COL_2
10 Bits
0x3 : COL_3
9 Bits
0x4 : COL_4
8 Bits
0x5 : COL_5
7 Bits
0x6 : COL_6
6 Bits
0x7 : COL_7
5 Bits
0x8 : COL_8
4 Bits
0x9 : COL_9
3 Bits
0xA : COL_10
2 Bits
0xB : COL_11
12 Bits
0xC : COL_12
12 Bits
0xD : COL_13
12 Bits
0xE : COL_14
12 Bits
0xF : COL_15
12 Bits
End of enumeration elements list.
NOR control register 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CES : CE setup time cycle
bits : 0 - 3 (4 bit)
access : read-write
CEH : CE hold min time (CEH+1) cycle
bits : 4 - 7 (4 bit)
access : read-write
AS : Address setup time
bits : 8 - 11 (4 bit)
access : read-write
AH : Address hold time
bits : 12 - 15 (4 bit)
access : read-write
WEL : WE LOW time (WEL+1) cycle
bits : 16 - 19 (4 bit)
access : read-write
WEH : WE HIGH time (WEH+1) cycle
bits : 20 - 23 (4 bit)
access : read-write
REL : RE LOW time (REL+1) cycle
bits : 24 - 27 (4 bit)
access : read-write
REH : RE HIGH time (REH+1) cycle
bits : 28 - 31 (4 bit)
access : read-write
NOR control register 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDS : Write Data setup time (WDS+1) cycle
bits : 0 - 3 (4 bit)
access : read-write
WDH : Write Data hold time (WDH+1) cycle
bits : 4 - 7 (4 bit)
access : read-write
TA : Turnaround time cycle
bits : 8 - 11 (4 bit)
access : read-write
AWDH : Address to write data hold time cycle
bits : 12 - 15 (4 bit)
access : read-write
LC : Latency count
bits : 16 - 19 (4 bit)
access : read-write
RD : Read cycle time
bits : 20 - 23 (4 bit)
access : read-write
CEITV : CE# interval min time
bits : 24 - 27 (4 bit)
access : read-write
NOR control register 3
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM control register 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Port Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
8bit
0x1 : PS_1
16bit
End of enumeration elements list.
BL : Burst Length
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : BL_0
1
0x1 : BL_1
2
0x2 : BL_2
4
0x3 : BL_3
8
0x4 : BL_4
16
0x5 : BL_5
32
0x6 : BL_6
64
0x7 : BL_7
64
End of enumeration elements list.
AM : Address Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : AM_0
Address/Data MUX mode
0x1 : AM_1
Advanced Address/Data MUX mode
0x2 : AM_2
Address/Data non-MUX mode
0x3 : AM_3
Address/Data non-MUX mode
End of enumeration elements list.
ADVP : ADV# polarity
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : ADVP_0
ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW.
0x1 : ADVP_1
ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.
End of enumeration elements list.
COL : Column Address bit width
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : COL_0
12 Bits
0x1 : COL_1
11 Bits
0x2 : COL_2
10 Bits
0x3 : COL_3
9 Bits
0x4 : COL_4
8 Bits
0x5 : COL_5
7 Bits
0x6 : COL_6
6 Bits
0x7 : COL_7
5 Bits
0x8 : COL_8
4 Bits
0x9 : COL_9
3 Bits
0xA : COL_10
2 Bits
0xB : COL_11
12 Bits
0xC : COL_12
12 Bits
0xD : COL_13
12 Bits
0xE : COL_14
12 Bits
0xF : COL_15
12 Bits
End of enumeration elements list.
SRAM control register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CES : CE setup time cycle
bits : 0 - 3 (4 bit)
access : read-write
CEH : CE hold min time (CEH+1) cycle
bits : 4 - 7 (4 bit)
access : read-write
AS : Address setup time
bits : 8 - 11 (4 bit)
access : read-write
AH : Address hold time
bits : 12 - 15 (4 bit)
access : read-write
WEL : WE LOW time (WEL+1) cycle
bits : 16 - 19 (4 bit)
access : read-write
WEH : WE HIGH time (WEH+1) cycle
bits : 20 - 23 (4 bit)
access : read-write
REL : RE LOW time (REL+1) cycle
bits : 24 - 27 (4 bit)
access : read-write
REH : RE HIGH time (REH+1) cycle
bits : 28 - 31 (4 bit)
access : read-write
SRAM control register 2
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDS : Write Data setup time (WDS+1) cycle
bits : 0 - 3 (4 bit)
access : read-write
WDH : Write Data hold time (WDH+1) cycle
bits : 4 - 7 (4 bit)
access : read-write
TA : Turnaround time cycle
bits : 8 - 11 (4 bit)
access : read-write
AWDH : Address to write data hold time cycle
bits : 12 - 15 (4 bit)
access : read-write
LC : Latency count
bits : 16 - 19 (4 bit)
access : read-write
RD : Read cycle time
bits : 20 - 23 (4 bit)
access : read-write
CEITV : CE# interval min time
bits : 24 - 27 (4 bit)
access : read-write
SRAM control register 3
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Master Bus (AXI) Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WQOS : Weight of QoS
bits : 0 - 3 (4 bit)
access : read-write
WAGE : Weight of Aging
bits : 4 - 7 (4 bit)
access : read-write
WSH : Weight of Slave Hit (no read/write switch)
bits : 8 - 15 (8 bit)
access : read-write
WRWS : Weight of Slave Hit (Read/Write switch)
bits : 16 - 23 (8 bit)
access : read-write
DBI-B control register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Port Size
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
8bit
0x1 : PS_1
16bit
End of enumeration elements list.
BL : Burst Length
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : BL_0
1
0x1 : BL_1
2
0x2 : BL_2
4
0x3 : BL_3
8
0x4 : BL_4
16
0x5 : BL_5
32
0x6 : BL_6
64
0x7 : BL_7
64
End of enumeration elements list.
COL : Column Address bit width
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : COL_0
12 Bits
0x1 : COL_1
11 Bits
0x2 : COL_2
10 Bits
0x3 : COL_3
9 Bits
0x4 : COL_4
8 Bits
0x5 : COL_5
7 Bits
0x6 : COL_6
6 Bits
0x7 : COL_7
5 Bits
0x8 : COL_8
4 Bits
0x9 : COL_9
3 Bits
0xA : COL_10
2 Bits
0xB : COL_11
12 Bits
0xC : COL_12
12 Bits
0xD : COL_13
12 Bits
0xE : COL_14
12 Bits
0xF : COL_15
12 Bits
End of enumeration elements list.
DBI-B control register 1
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CES : CSX Setup Time
bits : 0 - 3 (4 bit)
access : read-write
CEH : CSX Hold Time
bits : 4 - 7 (4 bit)
access : read-write
WEL : WRX Low Time
bits : 8 - 11 (4 bit)
access : read-write
WEH : WRX High Time
bits : 12 - 15 (4 bit)
access : read-write
REL : RDX Low Time bit [3:0]
bits : 16 - 19 (4 bit)
access : read-write
REH : RDX High Time bit [3:0]
bits : 20 - 23 (4 bit)
access : read-write
CEITV : CSX interval min time
bits : 24 - 27 (4 bit)
access : read-write
REL2 : RDX Low Time bit [5:4]
bits : 28 - 29 (2 bit)
access : read-write
REH2 : RDX High Time bit [5:4]
bits : 30 - 31 (2 bit)
access : read-write
IP Command control register 0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Slave address
bits : 0 - 31 (32 bit)
access : read-write
IP Command control register 1
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATSZ : Data Size in Byte
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DATSZ_0
4
0x1 : DATSZ_1
1
0x2 : DATSZ_2
2
0x3 : DATSZ_3
3
0x4 : DATSZ_4
4
0x5 : DATSZ_5
4
0x6 : DATSZ_6
4
0x7 : DATSZ_7
4
End of enumeration elements list.
IP Command control register 2
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BM0 : Byte Mask for Byte 0 (IPTXD bit 7:0)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : BM0_0
Byte Unmasked
0x1 : BM0_1
Byte Masked
End of enumeration elements list.
BM1 : Byte Mask for Byte 1 (IPTXD bit 15:8)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : BM1_0
Byte Unmasked
0x1 : BM1_1
Byte Masked
End of enumeration elements list.
BM2 : Byte Mask for Byte 2 (IPTXD bit 23:16)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : BM2_0
Byte Unmasked
0x1 : BM2_1
Byte Masked
End of enumeration elements list.
BM3 : Byte Mask for Byte 3 (IPTXD bit 31:24)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BM3_0
Byte Unmasked
0x1 : BM3_1
Byte Masked
End of enumeration elements list.
IP Command register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : SDRAM Commands: 0x8: READ 0x9: WRITE 0xA: MODESET 0xB: ACTIVE 0xC: AUTO REFRESH 0xD: SELF REFRESH 0xE: PRECHARGE 0xF: PRECHARGE ALL Others: RSVD SELF REFRESH will be sent to all SDRAM devices because they shared same SEMC_CLK pin
bits : 0 - 15 (16 bit)
access : read-write
KEY : This field should be written with 0xA55A when trigging an IP command.
bits : 16 - 31 (16 bit)
access : write-only
TX DATA register (for IP Command)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : no description available
bits : 0 - 31 (32 bit)
access : read-write
RX DATA register (for IP Command)
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAT : no description available
bits : 0 - 31 (32 bit)
access : read-only
Master Bus (AXI) Control Register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WQOS : Weight of QoS
bits : 0 - 3 (4 bit)
access : read-write
WAGE : Weight of Aging
bits : 4 - 7 (4 bit)
access : read-write
WPH : Weight of Page Hit
bits : 8 - 15 (8 bit)
access : read-write
WRWS : Weight of Read/Write switch
bits : 16 - 23 (8 bit)
access : read-write
WBR : Weight of Bank Rotation
bits : 24 - 31 (8 bit)
access : read-write
Status register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDLE : Indicating whether SEMC is in IDLE state.
bits : 0 - 0 (1 bit)
access : read-only
NARDY : Indicating NAND device Ready/WAIT# pin level.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : NARDY_0
NAND device is not ready
0x1 : NARDY_1
NAND device is ready
End of enumeration elements list.
Status register 1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 2
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NDWRPEND : This field indicating whether there is pending AXI command (write) to NAND device.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NDWRPEND_0
No pending
0x1 : NDWRPEND_1
Pending
End of enumeration elements list.
Status register 3
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 4
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 5
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 6
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 7
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 8
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 9
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 10
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 11
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 12
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NDADDR : This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).
bits : 0 - 31 (32 bit)
access : read-only
Status register 13
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 14
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Status register 15
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.