Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
SNVS_HP Lock Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK_WSL : Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ZMK_WSL_0
Write access is allowed
0x1 : ZMK_WSL_1
Write access is not allowed
End of enumeration elements list.
ZMK_RSL : Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ZMK_RSL_0
Read access is allowed (only in software Programming mode)
0x1 : ZMK_RSL_1
Read access is not allowed
End of enumeration elements list.
SRTC_SL : Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRTC_SL_0
Write access is allowed
0x1 : SRTC_SL_1
Write access is not allowed
End of enumeration elements list.
LPCALB_SL : LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : LPCALB_SL_0
Write access is allowed
0x1 : LPCALB_SL_1
Write access is not allowed
End of enumeration elements list.
MC_SL : Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MC_SL_0
Write access (increment) is allowed
0x1 : MC_SL_1
Write access (increment) is not allowed
End of enumeration elements list.
GPR_SL : General Purpose Register Soft Lock When set, prevents any writes to the GPR
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : GPR_SL_0
Write access is allowed
0x1 : GPR_SL_1
Write access is not allowed
End of enumeration elements list.
LPSVCR_SL : LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : LPSVCR_SL_0
Write access is allowed
0x1 : LPSVCR_SL_1
Write access is not allowed
End of enumeration elements list.
LPTDCR_SL : LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LPTDCR_SL_0
Write access is allowed
0x1 : LPTDCR_SL_1
Write access is not allowed
End of enumeration elements list.
MKS_SL : Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : MKS_SL_0
Write access is allowed
0x1 : MKS_SL_1
Write access is not allowed
End of enumeration elements list.
HPSVCR_L : HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HPSVCR_L_0
Write access is allowed
0x1 : HPSVCR_L_1
Write access is not allowed
End of enumeration elements list.
HPSICR_L : HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : HPSICR_L_0
Write access is allowed
0x1 : HPSICR_L_1
Write access is not allowed
End of enumeration elements list.
HAC_L : High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : HAC_L_0
Write access is allowed
0x1 : HAC_L_1
Write access is not allowed
End of enumeration elements list.
SNVS_HP Security Violation Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SV0_CFG : Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SV0_CFG_0
Security Violation 0 is a non-fatal violation
0x1 : SV0_CFG_1
Security Violation 0 is a fatal violation
End of enumeration elements list.
SV1_CFG : Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SV1_CFG_0
Security Violation 1 is a non-fatal violation
0x1 : SV1_CFG_1
Security Violation 1 is a fatal violation
End of enumeration elements list.
SV2_CFG : Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SV2_CFG_0
Security Violation 2 is a non-fatal violation
0x1 : SV2_CFG_1
Security Violation 2 is a fatal violation
End of enumeration elements list.
SV3_CFG : Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SV3_CFG_0
Security Violation 3 is a non-fatal violation
0x1 : SV3_CFG_1
Security Violation 3 is a fatal violation
End of enumeration elements list.
SV4_CFG : Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SV4_CFG_0
Security Violation 4 is a non-fatal violation
0x1 : SV4_CFG_1
Security Violation 4 is a fatal violation
End of enumeration elements list.
SV5_CFG : Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : SV5_CFG_0
Security Violation 5 is disabled
0x1 : SV5_CFG_1
Security Violation 5 is a non-fatal violation
#1x : SV5_CFG_2
Security Violation 5 is a fatal violation
End of enumeration elements list.
LPSV_CFG : LP Security Violation Configuration This field configures the LP security violation source.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : LPSV_CFG_0
LP security violation is disabled
0x1 : LPSV_CFG_1
LP security violation is a non-fatal violation
#1x : LPSV_CFG_2
LP security violation is a fatal violation
End of enumeration elements list.
SNVS_LP General Purpose Registers 0 .. 3
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPTA : HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HPTA_0
No time alarm interrupt occurred.
0x1 : HPTA_1
A time alarm interrupt occurred.
End of enumeration elements list.
PI : Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PI_0
No periodic interrupt occurred.
0x1 : PI_1
A periodic interrupt occurred.
End of enumeration elements list.
LPDIS : Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS
bits : 4 - 4 (1 bit)
access : read-only
BTN : Button Value of the BTN input
bits : 6 - 6 (1 bit)
access : read-only
BI : Button Interrupt Signal ipi_snvs_btn_int_b was asserted.
bits : 7 - 7 (1 bit)
access : read-write
SSM_STATE : System Security Monitor State This field contains the encoded state of the SSM's state machine
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : SSM_STATE_0
Init
0x1 : SSM_STATE_1
Hard Fail
0x3 : SSM_STATE_3
Soft Fail
0x8 : SSM_STATE_8
Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
0x9 : SSM_STATE_9
Check
0xB : SSM_STATE_11
Non-Secure
0xD : SSM_STATE_13
Trusted
0xF : SSM_STATE_15
Secure
End of enumeration elements list.
SECURITY_CONFIG : Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : FAB_CONFIG
FAB configuration
0x1 : OPEN_CONFIG
OPEN configuration
0x2 : OPEN_CONFIG
OPEN configuration
0x3 : OPEN_CONFIG
OPEN configuration
#x1xx : FIELD_RETURN_CONFIG
FIELD RETURN configuration
0x8 : FAB_CONFIG
FAB configuration
0x9 : CLOSED_CONFIG
CLOSED configuration
0xA : CLOSED_CONFIG
CLOSED configuration
0xB : CLOSED_CONFIG
CLOSED configuration
End of enumeration elements list.
OTPMK_SYNDROME : One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location
bits : 16 - 24 (9 bit)
access : read-only
OTPMK_ZERO : One Time Programmable Master Key is Equal to Zero
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : OTPMK_ZERO_0
The OTPMK is not zero.
0x1 : OTPMK_ZERO_1
The OTPMK is zero.
End of enumeration elements list.
ZMK_ZERO : Zeroizable Master Key is Equal to Zero
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ZMK_ZERO_0
The ZMK is not zero.
0x1 : ZMK_ZERO_1
The ZMK is zero.
End of enumeration elements list.
SNVS_LP Zeroizable Master Key Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK : Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Security Violation Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SV0 : Security Violation 0 security violation was detected.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SV0_0
No Security Violation 0 security violation was detected.
0x1 : SV0_1
Security Violation 0 security violation was detected.
End of enumeration elements list.
SV1 : Security Violation 1 security violation was detected.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SV1_0
No Security Violation 1 security violation was detected.
0x1 : SV1_1
Security Violation 1 security violation was detected.
End of enumeration elements list.
SV2 : Security Violation 2 security violation was detected.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SV2_0
No Security Violation 2 security violation was detected.
0x1 : SV2_1
Security Violation 2 security violation was detected.
End of enumeration elements list.
SV3 : Security Violation 3 security violation was detected.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SV3_0
No Security Violation 3 security violation was detected.
0x1 : SV3_1
Security Violation 3 security violation was detected.
End of enumeration elements list.
SV4 : Security Violation 4 security violation was detected.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SV4_0
No Security Violation 4 security violation was detected.
0x1 : SV4_1
Security Violation 4 security violation was detected.
End of enumeration elements list.
SV5 : Security Violation 5 security violation was detected.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SV5_0
No Security Violation 5 security violation was detected.
0x1 : SV5_1
Security Violation 5 security violation was detected.
End of enumeration elements list.
SW_SV : Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register
bits : 13 - 13 (1 bit)
access : read-only
SW_FSV : Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register
bits : 14 - 14 (1 bit)
access : read-only
SW_LPSV : LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register
bits : 15 - 15 (1 bit)
access : read-only
ZMK_SYNDROME : Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register
bits : 16 - 24 (9 bit)
access : read-only
ZMK_ECC_FAIL : Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : ZMK_ECC_FAIL_0
ZMK ECC Failure was not detected.
0x1 : ZMK_ECC_FAIL_1
ZMK ECC Failure was detected.
End of enumeration elements list.
LP_SEC_VIO : LP Security Violation A security volation was detected in the SNVS low power section.
bits : 31 - 31 (1 bit)
access : read-only
SNVS_LP General Purpose Registers 0 .. 3
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Zeroizable Master Key Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK : Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP High Assurance Counter IV Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HAC_COUNTER_IV : High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP High Assurance Counter Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HAC_COUNTER : High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock
bits : 0 - 31 (32 bit)
access : read-only
SNVS_LP General Purpose Registers 0 .. 7
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Zeroizable Master Key Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK : Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Real Time Counter MSB Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : HP Real Time Counter The most-significant 15 bits of the RTC
bits : 0 - 14 (15 bit)
access : read-write
SNVS_LP General Purpose Registers 0 .. 3
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Real Time Counter LSB Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : HP Real Time Counter least-significant 32 bits
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Zeroizable Master Key Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK : Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Time Alarm MSB Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPTA_MS : HP Time Alarm, most-significant 15 bits
bits : 0 - 14 (15 bit)
access : read-write
SNVS_LP General Purpose Registers 0 .. 3
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Time Alarm LSB Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPTA_LS : HP Time Alarm, 32 least-significant bits
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP General Purpose Registers 0 .. 7
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Zeroizable Master Key Register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK : Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Lock Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK_WHL : Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ZMK_WHL_0
Write access is allowed.
0x1 : ZMK_WHL_1
Write access is not allowed.
End of enumeration elements list.
ZMK_RHL : Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ZMK_RHL_0
Read access is allowed (only in software programming mode).
0x1 : ZMK_RHL_1
Read access is not allowed.
End of enumeration elements list.
SRTC_HL : Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRTC_HL_0
Write access is allowed.
0x1 : SRTC_HL_1
Write access is not allowed.
End of enumeration elements list.
LPCALB_HL : LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : LPCALB_HL_0
Write access is allowed.
0x1 : LPCALB_HL_1
Write access is not allowed.
End of enumeration elements list.
MC_HL : Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MC_HL_0
Write access (increment) is allowed.
0x1 : MC_HL_1
Write access (increment) is not allowed.
End of enumeration elements list.
GPR_HL : General Purpose Register Hard Lock When set, prevents any writes to the GPR
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : GPR_HL_0
Write access is allowed.
0x1 : GPR_HL_1
Write access is not allowed.
End of enumeration elements list.
LPSVCR_HL : LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : LPSVCR_HL_0
Write access is allowed.
0x1 : LPSVCR_HL_1
Write access is not allowed.
End of enumeration elements list.
LPTDCR_HL : LP Tamper Detectors Configuration Register Hard Lock When set, prevents any writes to the LPTDCR
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LPTDCR_HL_0
Write access is allowed.
0x1 : LPTDCR_HL_1
Write access is not allowed.
End of enumeration elements list.
MKS_HL : Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : MKS_HL_0
Write access is allowed.
0x1 : MKS_HL_1
Write access is not allowed.
End of enumeration elements list.
SNVS_LP Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTC_ENV : Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRTC_ENV_0
SRTC is disabled or invalid.
0x1 : SRTC_ENV_1
SRTC is enabled and valid.
End of enumeration elements list.
LPTA_EN : LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : LPTA_EN_0
LP time alarm interrupt is disabled.
0x1 : LPTA_EN_1
LP time alarm interrupt is enabled.
End of enumeration elements list.
MC_ENV : Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MC_ENV_0
MC is disabled or invalid.
0x1 : MC_ENV_1
MC is enabled and valid.
End of enumeration elements list.
LPWUI_EN : LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm )
bits : 3 - 3 (1 bit)
access : read-write
SRTC_INV_EN : If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SRTC_INV_EN_0
SRTC stays valid in the case of security violation.
0x1 : SRTC_INV_EN_1
SRTC is invalidated in the case of security violation.
End of enumeration elements list.
DP_EN : Dumb PMIC Enabled When set, software can control the system power
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DP_EN_0
Smart PMIC enabled.
0x1 : DP_EN_1
Dumb PMIC enabled.
End of enumeration elements list.
TOP : Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TOP_0
Leave system power on.
0x1 : TOP_1
Turn off system power.
End of enumeration elements list.
PWR_GLITCH_EN : Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted
bits : 7 - 7 (1 bit)
access : read-write
LPCALB_EN : LP Calibration Enable When set, enables the SRTC calibration mechanism
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LPCALB_EN_0
SRTC Time calibration is disabled.
0x1 : LPCALB_EN_1
SRTC Time calibration is enabled.
End of enumeration elements list.
LPCALB_VAL : LP Calibration Value Defines signed calibration value for SRTC
bits : 10 - 14 (5 bit)
access : read-write
Enumeration:
0 : LPCALB_VAL_0
+0 counts per each 32768 ticks of the counter clock
0x1 : LPCALB_VAL_1
+1 counts per each 32768 ticks of the counter clock
0x2 : LPCALB_VAL_2
+2 counts per each 32768 ticks of the counter clock
0xF : LPCALB_VAL_15
+15 counts per each 32768 ticks of the counter clock
0x10 : LPCALB_VAL_16
-16 counts per each 32768 ticks of the counter clock
0x11 : LPCALB_VAL_17
-15 counts per each 32768 ticks of the counter clock
0x1E : LPCALB_VAL_30
-2 counts per each 32768 ticks of the counter clock
0x1F : LPCALB_VAL_31
-1 counts per each 32768 ticks of the counter clock
End of enumeration elements list.
BTN_PRESS_TIME : This field configures the button press time out values for the PMIC Logic
bits : 16 - 17 (2 bit)
access : read-write
DEBOUNCE : This field configures the amount of debounce time for the BTN input signal
bits : 18 - 19 (2 bit)
access : read-write
ON_TIME : The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power
bits : 20 - 21 (2 bit)
access : read-write
PK_EN : PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en
bits : 22 - 22 (1 bit)
access : read-write
PK_OVERRIDE : PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override
bits : 23 - 23 (1 bit)
access : read-write
GPR_Z_DIS : General Purpose Registers Zeroization Disable
bits : 24 - 24 (1 bit)
access : read-write
SNVS_LP Zeroizable Master Key Register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK : Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Master Key Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASTER_KEY_SEL : Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#0x : MASTER_KEY_SEL_0
Select one time programmable master key.
0x2 : MASTER_KEY_SEL_2
Select zeroizable master key when MKS_EN bit is set .
0x3 : MASTER_KEY_SEL_3
Select combined master key when MKS_EN bit is set .
End of enumeration elements list.
ZMK_HWP : Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ZMK_HWP_0
ZMK is in the software programming mode.
0x1 : ZMK_HWP_1
ZMK is in the hardware programming mode.
End of enumeration elements list.
ZMK_VAL : Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ZMK_VAL_0
ZMK is not valid.
0x1 : ZMK_VAL_1
ZMK is valid.
End of enumeration elements list.
ZMK_ECC_EN : Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ZMK_ECC_EN_0
ZMK ECC check is disabled.
0x1 : ZMK_ECC_EN_1
ZMK ECC check is enabled.
End of enumeration elements list.
ZMK_ECC_VALUE : Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register
bits : 7 - 15 (9 bit)
access : read-only
SNVS_HP Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSM_ST : SSM State Transition Transition state of the system security monitor
bits : 0 - 0 (1 bit)
access : write-only
SSM_ST_DIS : SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SSM_ST_DIS_0
Secure to Trusted State transition is enabled
0x1 : SSM_ST_DIS_1
Secure to Trusted State transition is disabled
End of enumeration elements list.
SSM_SFNS_DIS : SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SSM_SFNS_DIS_0
Soft Fail to Non-Secure State transition is enabled
0x1 : SSM_SFNS_DIS_1
Soft Fail to Non-Secure State transition is disabled
End of enumeration elements list.
LP_SWR : LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
0 : LP_SWR_0
No Action
0x1 : LP_SWR_1
Reset LP section
End of enumeration elements list.
LP_SWR_DIS : LP Software Reset Disable When set, disables the LP software reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LP_SWR_DIS_0
LP software reset is enabled
0x1 : LP_SWR_DIS_1
LP software reset is disabled
End of enumeration elements list.
SW_SV : Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation
bits : 8 - 8 (1 bit)
access : read-write
SW_FSV : Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation
bits : 9 - 9 (1 bit)
access : read-write
SW_LPSV : LP Software Security Violation When set, SNVS_LP treats this bit as a security violation
bits : 10 - 10 (1 bit)
access : read-write
PROG_ZMK : Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism
bits : 12 - 12 (1 bit)
access : write-only
Enumeration:
0 : PROG_ZMK_0
No Action
0x1 : PROG_ZMK_1
Activate hardware key programming mechanism
End of enumeration elements list.
MKS_EN : Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : MKS_EN_0
OTP master key is selected as an SNVS master key
0x1 : MKS_EN_1
SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
End of enumeration elements list.
HAC_EN : High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HAC_EN_0
High Assurance Counter is disabled
0x1 : HAC_EN_1
High Assurance Counter is enabled
End of enumeration elements list.
HAC_LOAD : High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register
bits : 17 - 17 (1 bit)
access : write-only
Enumeration:
0 : HAC_LOAD_0
No Action
0x1 : HAC_LOAD_1
Load the HAC
End of enumeration elements list.
HAC_CLEAR : High Assurance Counter Clear When set, it clears the High Assurance Counter Register
bits : 18 - 18 (1 bit)
access : write-only
Enumeration:
0 : HAC_CLEAR_0
No Action
0x1 : HAC_CLEAR_1
Clear the HAC
End of enumeration elements list.
HAC_STOP : High Assurance Counter Stop This bit can be set only when SSM is in soft fail state
bits : 19 - 19 (1 bit)
access : read-write
NPSWA_EN : Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only
bits : 31 - 31 (1 bit)
access : read-write
SNVS_LP Security Violation Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SV0_EN : Security Violation 0 Enable This bit enables Security Violation 0 Input
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SV0_EN_0
Security Violation 0 is disabled in the LP domain.
0x1 : SV0_EN_1
Security Violation 0 is enabled in the LP domain.
End of enumeration elements list.
SV1_EN : Security Violation 1 Enable This bit enables Security Violation 1 Input
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SV1_EN_0
Security Violation 1 is disabled in the LP domain.
0x1 : SV1_EN_1
Security Violation 1 is enabled in the LP domain.
End of enumeration elements list.
SV2_EN : Security Violation 2 Enable This bit enables Security Violation 2 Input
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SV2_EN_0
Security Violation 2 is disabled in the LP domain.
0x1 : SV2_EN_1
Security Violation 2 is enabled in the LP domain.
End of enumeration elements list.
SV3_EN : Security Violation 3 Enable This bit enables Security Violation 3 Input
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SV3_EN_0
Security Violation 3 is disabled in the LP domain.
0x1 : SV3_EN_1
Security Violation 3 is enabled in the LP domain.
End of enumeration elements list.
SV4_EN : Security Violation 4 Enable This bit enables Security Violation 4 Input
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SV4_EN_0
Security Violation 4 is disabled in the LP domain.
0x1 : SV4_EN_1
Security Violation 4 is enabled in the LP domain.
End of enumeration elements list.
SV5_EN : Security Violation 5 Enable This bit enables Security Violation 5 Input
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SV5_EN_0
Security Violation 5 is disabled in the LP domain.
0x1 : SV5_EN_1
Security Violation 5 is enabled in the LP domain.
End of enumeration elements list.
SNVS_LP General Purpose Registers 0 .. 7
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Zeroizable Master Key Register
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK : Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Tamper Detectors Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTCR_EN : SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRTCR_EN_0
SRTC rollover is disabled.
0x1 : SRTCR_EN_1
SRTC rollover is enabled.
End of enumeration elements list.
MCR_EN : MC Rollover Enable When set, an MC Rollover event generates an LP security violation.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MCR_EN_0
MC rollover is disabled.
0x1 : MCR_EN_1
MC rollover is enabled.
End of enumeration elements list.
ET1_EN : External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : ET1_EN_0
External tamper 1 is disabled.
0x1 : ET1_EN_1
External tamper 1 is enabled.
End of enumeration elements list.
ET1P : External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ET1P_0
External tamper 1 is active low.
0x1 : ET1P_1
External tamper 1 is active high.
End of enumeration elements list.
PFD_OBSERV : System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block)
bits : 14 - 14 (1 bit)
access : read-write
POR_OBSERV : Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS
bits : 15 - 15 (1 bit)
access : read-write
OSCB : Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : OSCB_0
Normal SRTC clock oscillator not bypassed.
0x1 : OSCB_1
Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
End of enumeration elements list.
SNVS_LP Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTA : LP Time Alarm
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LPTA_0
No time alarm interrupt occurred.
0x1 : LPTA_1
A time alarm interrupt occurred.
End of enumeration elements list.
SRTCR : Secure Real Time Counter Rollover
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRTCR_0
SRTC has not reached its maximum value.
0x1 : SRTCR_1
SRTC has reached its maximum value.
End of enumeration elements list.
MCR : Monotonic Counter Rollover
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MCR_0
MC has not reached its maximum value.
0x1 : MCR_1
MC has reached its maximum value.
End of enumeration elements list.
PGD : Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected.
bits : 3 - 3 (1 bit)
access : read-write
ET1D : External Tampering 1 Detected
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : ET1D_0
External tampering 1 not detected.
0x1 : ET1D_1
External tampering 1 detected.
End of enumeration elements list.
ESVD : External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : ESVD_0
No external security violation.
0x1 : ESVD_1
External security violation is detected.
End of enumeration elements list.
EO : Emergency Off This bit is set when a power off is requested.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : EO_0
Emergency off was not detected.
0x1 : EO_1
Emergency off was detected.
End of enumeration elements list.
SPO : Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SPO_0
Set Power Off was not detected.
0x1 : SPO_1
Set Power Off was detected.
End of enumeration elements list.
SED : Scan Exit Detected
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SED_0
Scan exit was not detected.
0x1 : SED_1
Scan exit was detected.
End of enumeration elements list.
LPNS : LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : LPNS_0
LP section was not programmed in the non-secure state.
0x1 : LPNS_1
LP section was programmed in the non-secure state.
End of enumeration elements list.
LPS : LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : LPS_0
LP section was not programmed in secure or trusted state.
0x1 : LPS_1
LP section was programmed in secure or trusted state.
End of enumeration elements list.
SNVS_LP Secure Real Time Counter MSB Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTC : LP Secure Real Time Counter The most-significant 15 bits of the SRTC
bits : 0 - 14 (15 bit)
access : read-write
SNVS_LP General Purpose Registers 0 .. 7
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Secure Real Time Counter LSB Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTC : LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Time Alarm Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTA : LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set)
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Secure Monotonic Counter MSB Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MON_COUNTER : Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected
bits : 0 - 15 (16 bit)
access : read-only
MC_ERA_BITS : Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses
bits : 16 - 31 (16 bit)
access : read-only
SNVS_LP Secure Monotonic Counter LSB Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MON_COUNTER : Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected
bits : 0 - 31 (32 bit)
access : read-only
SNVS_LP General Purpose Registers 0 .. 7
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Power Glitch Detector Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PGD : Power Glitch Detector Value
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP General Purpose Register 0 (legacy alias)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP General Purpose Registers 0 .. 7
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC_EN : HP Real Time Counter Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RTC_EN_0
RTC is disabled
0x1 : RTC_EN_1
RTC is enabled
End of enumeration elements list.
HPTA_EN : HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HPTA_EN_0
HP Time Alarm Interrupt is disabled
0x1 : HPTA_EN_1
HP Time Alarm Interrupt is enabled
End of enumeration elements list.
DIS_PI : Disable periodic interrupt in the functional interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DIS_PI_0
Periodic interrupt will trigger a functional interrupt
0x1 : DIS_PI_1
Disable periodic interrupt in the function interrupt
End of enumeration elements list.
PI_EN : HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PI_EN_0
HP Periodic Interrupt is disabled
0x1 : PI_EN_1
HP Periodic Interrupt is enabled
End of enumeration elements list.
PI_FREQ : Periodic Interrupt Frequency Defines frequency of the periodic interrupt
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : PI_FREQ_0
- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
0x1 : PI_FREQ_1
- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
0x2 : PI_FREQ_2
- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
0x3 : PI_FREQ_3
- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
0x4 : PI_FREQ_4
- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
0x5 : PI_FREQ_5
- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
0x6 : PI_FREQ_6
- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
0x7 : PI_FREQ_7
- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
0x8 : PI_FREQ_8
- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
0x9 : PI_FREQ_9
- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
0xA : PI_FREQ_10
- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
0xB : PI_FREQ_11
- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
0xC : PI_FREQ_12
- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
0xD : PI_FREQ_13
- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
0xE : PI_FREQ_14
- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
0xF : PI_FREQ_15
- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
End of enumeration elements list.
HPCALB_EN : HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : HPCALB_EN_0
HP Timer calibration disabled
0x1 : HPCALB_EN_1
HP Timer calibration enabled
End of enumeration elements list.
HPCALB_VAL : HP Calibration Value Defines signed calibration value for the HP Real Time Counter
bits : 10 - 14 (5 bit)
access : read-write
Enumeration:
0 : HPCALB_VAL_0
+0 counts per each 32768 ticks of the counter
0x1 : HPCALB_VAL_1
+1 counts per each 32768 ticks of the counter
0x2 : HPCALB_VAL_2
+2 counts per each 32768 ticks of the counter
0xF : HPCALB_VAL_15
+15 counts per each 32768 ticks of the counter
0x10 : HPCALB_VAL_16
-16 counts per each 32768 ticks of the counter
0x11 : HPCALB_VAL_17
-15 counts per each 32768 ticks of the counter
0x1E : HPCALB_VAL_30
-2 counts per each 32768 ticks of the counter
0x1F : HPCALB_VAL_31
-1 counts per each 32768 ticks of the counter
End of enumeration elements list.
HP_TS : HP Time Synchronize
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HP_TS_0
No Action
0x1 : HP_TS_1
Synchronize the HP Time Counter to the LP Time Counter
End of enumeration elements list.
BTN_CONFIG : Button Configuration
bits : 24 - 26 (3 bit)
access : read-write
BTN_MASK : Button interrupt mask
bits : 27 - 27 (1 bit)
access : read-write
SNVS_LP General Purpose Registers 0 .. 7
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP General Purpose Registers 0 .. 7
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Version ID Register 1
address_offset : 0xBF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINOR_REV : SNVS block minor version number
bits : 0 - 7 (8 bit)
access : read-only
MAJOR_REV : SNVS block major version number
bits : 8 - 15 (8 bit)
access : read-only
IP_ID : SNVS block ID
bits : 16 - 31 (16 bit)
access : read-only
SNVS_HP Version ID Register 2
address_offset : 0xBFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CONFIG_OPT : SNVS Configuration Options
bits : 0 - 7 (8 bit)
access : read-only
ECO_REV : SNVS ECO Revision
bits : 8 - 15 (8 bit)
access : read-only
INTG_OPT : SNVS Integration Options
bits : 16 - 23 (8 bit)
access : read-only
IP_ERA : IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5
bits : 24 - 31 (8 bit)
access : read-only
SNVS_HP Security Interrupt Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SV0_EN : Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SV0_EN_0
Security Violation 0 Interrupt is Disabled
0x1 : SV0_EN_1
Security Violation 0 Interrupt is Enabled
End of enumeration elements list.
SV1_EN : Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SV1_EN_0
Security Violation 1 Interrupt is Disabled
0x1 : SV1_EN_1
Security Violation 1 Interrupt is Enabled
End of enumeration elements list.
SV2_EN : Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SV2_EN_0
Security Violation 2 Interrupt is Disabled
0x1 : SV2_EN_1
Security Violation 2 Interrupt is Enabled
End of enumeration elements list.
SV3_EN : Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SV3_EN_0
Security Violation 3 Interrupt is Disabled
0x1 : SV3_EN_1
Security Violation 3 Interrupt is Enabled
End of enumeration elements list.
SV4_EN : Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SV4_EN_0
Security Violation 4 Interrupt is Disabled
0x1 : SV4_EN_1
Security Violation 4 Interrupt is Enabled
End of enumeration elements list.
SV5_EN : Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SV5_EN_0
Security Violation 5 Interrupt is Disabled
0x1 : SV5_EN_1
Security Violation 5 Interrupt is Enabled
End of enumeration elements list.
LPSVI_EN : LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LPSVI_EN_0
LP Security Violation Interrupt is Disabled
0x1 : LPSVI_EN_1
LP Security Violation Interrupt is Enabled
End of enumeration elements list.
SNVS_LP Zeroizable Master Key Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZMK : Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value
bits : 0 - 31 (32 bit)
access : read-write
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