Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Module Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRESET : Software Reset
bits : 0 - 0 (1 bit)
access : read-write
MDIS : Module Disable
bits : 1 - 1 (1 bit)
access : read-write
RXCLKSRC : Sample Clock source selection for Flash Reading
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : RXCLKSRC_0
Dummy Read strobe generated by FlexSPI Controller and loopback internally.
0x1 : RXCLKSRC_1
Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
0x3 : RXCLKSRC_3
Flash provided Read strobe and input from DQS pad
End of enumeration elements list.
ARDFEN : Enable AHB bus Read Access to IP RX FIFO.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : ARDFEN_0
IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
0x1 : ARDFEN_1
IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
End of enumeration elements list.
ATDFEN : Enable AHB bus Write Access to IP TX FIFO.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ATDFEN_0
IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
0x1 : ATDFEN_1
IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
End of enumeration elements list.
HSEN : Half Speed Serial Flash access Enable.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : HSEN_0
Disable divide by 2 of serial flash clock for half speed commands.
0x1 : HSEN_1
Enable divide by 2 of serial flash clock for half speed commands.
End of enumeration elements list.
DOZEEN : Doze mode enable bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DOZEEN_0
Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
0x1 : DOZEEN_1
Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
End of enumeration elements list.
COMBINATIONEN : This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : COMBINATIONEN_0
Disable.
0x1 : COMBINATIONEN_1
Enable.
End of enumeration elements list.
SCKFREERUNEN : This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SCKFREERUNEN_0
Disable.
0x1 : SCKFREERUNEN_1
Enable.
End of enumeration elements list.
IPGRANTWAIT : Time out wait cycle for IP command grant.
bits : 16 - 23 (8 bit)
access : read-write
AHBGRANTWAIT : Timeout wait cycle for AHB command grant.
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPCMDDONEEN : IP triggered Command Sequences Execution finished interrupt enable.
bits : 0 - 0 (1 bit)
access : read-write
IPCMDGEEN : IP triggered Command Sequences Grant Timeout interrupt enable.
bits : 1 - 1 (1 bit)
access : read-write
AHBCMDGEEN : AHB triggered Command Sequences Grant Timeout interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
IPCMDERREN : IP triggered Command Sequences Error Detected interrupt enable.
bits : 3 - 3 (1 bit)
access : read-write
AHBCMDERREN : AHB triggered Command Sequences Error Detected interrupt enable.
bits : 4 - 4 (1 bit)
access : read-write
IPRXWAEN : IP RX FIFO WaterMark available interrupt enable.
bits : 5 - 5 (1 bit)
access : read-write
IPTXWEEN : IP TX FIFO WaterMark empty interrupt enable.
bits : 6 - 6 (1 bit)
access : read-write
SCKSTOPBYRDEN : SCK is stopped during command sequence because Async RX FIFO full interrupt enable.
bits : 8 - 8 (1 bit)
access : read-write
SCKSTOPBYWREN : SCK is stopped during command sequence because Async TX FIFO empty interrupt enable.
bits : 9 - 9 (1 bit)
access : read-write
AHBBUSTIMEOUTEN : AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
bits : 10 - 10 (1 bit)
access : read-write
SEQTIMEOUTEN : Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
bits : 11 - 11 (1 bit)
access : read-write
Flash A1 Control Register 2
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARDSEQID : Sequence Index for AHB Read triggered Command in LUT.
bits : 0 - 3 (4 bit)
access : read-write
ARDSEQNUM : Sequence Number for AHB Read triggered Command in LUT.
bits : 5 - 7 (3 bit)
access : read-write
AWRSEQID : Sequence Index for AHB Write triggered Command.
bits : 8 - 11 (4 bit)
access : read-write
AWRSEQNUM : Sequence Number for AHB Write triggered Command.
bits : 13 - 15 (3 bit)
access : read-write
AWRWAIT : For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface
bits : 16 - 27 (12 bit)
access : read-write
AWRWAITUNIT : AWRWAIT unit
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0 : AWRWAITUNIT_0
The AWRWAIT unit is 2 ahb clock cycle
0x1 : AWRWAITUNIT_1
The AWRWAIT unit is 8 ahb clock cycle
0x2 : AWRWAITUNIT_2
The AWRWAIT unit is 32 ahb clock cycle
0x3 : AWRWAITUNIT_3
The AWRWAIT unit is 128 ahb clock cycle
0x4 : AWRWAITUNIT_4
The AWRWAIT unit is 512 ahb clock cycle
0x5 : AWRWAITUNIT_5
The AWRWAIT unit is 2048 ahb clock cycle
0x6 : AWRWAITUNIT_6
The AWRWAIT unit is 8192 ahb clock cycle
0x7 : AWRWAITUNIT_7
The AWRWAIT unit is 32768 ahb clock cycle
End of enumeration elements list.
CLRINSTRPTR : Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.
bits : 31 - 31 (1 bit)
access : read-write
LUT 0
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x1134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x12DC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Interrupt Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPCMDDONE : IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated.
bits : 0 - 0 (1 bit)
access : read-write
IPCMDGE : IP triggered Command Sequences Grant Timeout interrupt.
bits : 1 - 1 (1 bit)
access : read-write
AHBCMDGE : AHB triggered Command Sequences Grant Timeout interrupt.
bits : 2 - 2 (1 bit)
access : read-write
IPCMDERR : IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all.
bits : 3 - 3 (1 bit)
access : read-write
AHBCMDERR : AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all.
bits : 4 - 4 (1 bit)
access : read-write
IPRXWA : IP RX FIFO watermark available interrupt.
bits : 5 - 5 (1 bit)
access : read-write
IPTXWE : IP TX FIFO watermark empty interrupt.
bits : 6 - 6 (1 bit)
access : read-write
SCKSTOPBYRD : SCK is stopped during command sequence because Async RX FIFO full interrupt.
bits : 8 - 8 (1 bit)
access : read-write
SCKSTOPBYWR : SCK is stopped during command sequence because Async TX FIFO empty interrupt.
bits : 9 - 9 (1 bit)
access : read-write
AHBBUSTIMEOUT : AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
bits : 10 - 10 (1 bit)
access : read-write
SEQTIMEOUT : Sequence execution timeout interrupt.
bits : 11 - 11 (1 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x1420 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x1488 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Flash A1 Control Register 1
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCSS : Serial Flash CS setup time.
bits : 0 - 4 (5 bit)
access : read-write
TCSH : Serial Flash CS Hold time.
bits : 5 - 9 (5 bit)
access : read-write
WA : Word Addressable.
bits : 10 - 10 (1 bit)
access : read-write
CAS : Column Address Size.
bits : 11 - 14 (4 bit)
access : read-write
CSINTERVALUNIT : CS interval unit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CSINTERVALUNIT_0
The CS interval unit is 1 serial clock cycle
0x1 : CSINTERVALUNIT_1
The CS interval unit is 256 serial clock cycle
End of enumeration elements list.
CSINTERVAL : This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.
bits : 16 - 31 (16 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x1564 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x1638 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x16AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x17EC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x17F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT Key Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : The Key to lock or unlock LUT.
bits : 0 - 31 (32 bit)
access : read-write
DLL Control Register 0
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLLEN : DLL calibration enable.
bits : 0 - 0 (1 bit)
access : read-write
DLLRESET : Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).
bits : 1 - 1 (1 bit)
access : read-write
SLVDLYTARGET : The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock).
bits : 3 - 6 (4 bit)
access : read-write
OVRDEN : Slave clock delay line delay cell number selection override enable.
bits : 8 - 8 (1 bit)
access : read-write
OVRDVAL : Slave clock delay line delay cell number selection override value.
bits : 9 - 14 (6 bit)
access : read-write
Flash A1 Control Register 2
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARDSEQID : Sequence Index for AHB Read triggered Command in LUT.
bits : 0 - 3 (4 bit)
access : read-write
ARDSEQNUM : Sequence Number for AHB Read triggered Command in LUT.
bits : 5 - 7 (3 bit)
access : read-write
AWRSEQID : Sequence Index for AHB Write triggered Command.
bits : 8 - 11 (4 bit)
access : read-write
AWRSEQNUM : Sequence Number for AHB Write triggered Command.
bits : 13 - 15 (3 bit)
access : read-write
AWRWAIT : For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface
bits : 16 - 27 (12 bit)
access : read-write
AWRWAITUNIT : AWRWAIT unit
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0 : AWRWAITUNIT_0
The AWRWAIT unit is 2 ahb clock cycle
0x1 : AWRWAITUNIT_1
The AWRWAIT unit is 8 ahb clock cycle
0x2 : AWRWAITUNIT_2
The AWRWAIT unit is 32 ahb clock cycle
0x3 : AWRWAITUNIT_3
The AWRWAIT unit is 128 ahb clock cycle
0x4 : AWRWAITUNIT_4
The AWRWAIT unit is 512 ahb clock cycle
0x5 : AWRWAITUNIT_5
The AWRWAIT unit is 2048 ahb clock cycle
0x6 : AWRWAITUNIT_6
The AWRWAIT unit is 8192 ahb clock cycle
0x7 : AWRWAITUNIT_7
The AWRWAIT unit is 32768 ahb clock cycle
End of enumeration elements list.
CLRINSTRPTR : Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.
bits : 31 - 31 (1 bit)
access : read-write
LUT 0
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x1948 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x19A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x1A9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x1B60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x1BF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : Lock LUT
bits : 0 - 0 (1 bit)
access : read-write
UNLOCK : Unlock LUT
bits : 1 - 1 (1 bit)
access : read-write
Flash A1 Control Register 1
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCSS : Serial Flash CS setup time.
bits : 0 - 4 (5 bit)
access : read-write
TCSH : Serial Flash CS Hold time.
bits : 5 - 9 (5 bit)
access : read-write
WA : Word Addressable.
bits : 10 - 10 (1 bit)
access : read-write
CAS : Column Address Size.
bits : 11 - 14 (4 bit)
access : read-write
CSINTERVALUNIT : CS interval unit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CSINTERVALUNIT_0
The CS interval unit is 1 serial clock cycle
0x1 : CSINTERVALUNIT_1
The CS interval unit is 256 serial clock cycle
End of enumeration elements list.
CSINTERVAL : This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.
bits : 16 - 31 (16 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x1D20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x1D50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP RX FIFO Data Register 0
address_offset : 0x1EB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x1EE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
AHB RX Buffer 0 Control Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSZ : AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.
bits : 0 - 7 (8 bit)
access : read-write
MSTRID : This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.
bits : 16 - 19 (4 bit)
access : read-write
PRIORITY : This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.
bits : 24 - 25 (2 bit)
access : read-write
PREFETCHEN : AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
bits : 31 - 31 (1 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP RX FIFO Data Register 0
address_offset : 0x2014 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x20AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
Flash A1 Control Register 2
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARDSEQID : Sequence Index for AHB Read triggered Command in LUT.
bits : 0 - 3 (4 bit)
access : read-write
ARDSEQNUM : Sequence Number for AHB Read triggered Command in LUT.
bits : 5 - 7 (3 bit)
access : read-write
AWRSEQID : Sequence Index for AHB Write triggered Command.
bits : 8 - 11 (4 bit)
access : read-write
AWRSEQNUM : Sequence Number for AHB Write triggered Command.
bits : 13 - 15 (3 bit)
access : read-write
AWRWAIT : For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface
bits : 16 - 27 (12 bit)
access : read-write
AWRWAITUNIT : AWRWAIT unit
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0 : AWRWAITUNIT_0
The AWRWAIT unit is 2 ahb clock cycle
0x1 : AWRWAITUNIT_1
The AWRWAIT unit is 8 ahb clock cycle
0x2 : AWRWAITUNIT_2
The AWRWAIT unit is 32 ahb clock cycle
0x3 : AWRWAITUNIT_3
The AWRWAIT unit is 128 ahb clock cycle
0x4 : AWRWAITUNIT_4
The AWRWAIT unit is 512 ahb clock cycle
0x5 : AWRWAITUNIT_5
The AWRWAIT unit is 2048 ahb clock cycle
0x6 : AWRWAITUNIT_6
The AWRWAIT unit is 8192 ahb clock cycle
0x7 : AWRWAITUNIT_7
The AWRWAIT unit is 32768 ahb clock cycle
End of enumeration elements list.
CLRINSTRPTR : Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.
bits : 31 - 31 (1 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x217C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x2278 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x22E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
AHB RX Buffer 1 Control Register 0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSZ : AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.
bits : 0 - 7 (8 bit)
access : read-write
MSTRID : This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.
bits : 16 - 19 (4 bit)
access : read-write
PRIORITY : This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.
bits : 24 - 25 (2 bit)
access : read-write
PREFETCHEN : AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
bits : 31 - 31 (1 bit)
access : read-write
DLL Control Register 0
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLLEN : DLL calibration enable.
bits : 0 - 0 (1 bit)
access : read-write
DLLRESET : Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).
bits : 1 - 1 (1 bit)
access : read-write
SLVDLYTARGET : The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock).
bits : 3 - 6 (4 bit)
access : read-write
OVRDEN : Slave clock delay line delay cell number selection override enable.
bits : 8 - 8 (1 bit)
access : read-write
OVRDVAL : Slave clock delay line delay cell number selection override value.
bits : 9 - 14 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x2448 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x2458 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Flash A1 Control Register 1
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCSS : Serial Flash CS setup time.
bits : 0 - 4 (5 bit)
access : read-write
TCSH : Serial Flash CS Hold time.
bits : 5 - 9 (5 bit)
access : read-write
WA : Word Addressable.
bits : 10 - 10 (1 bit)
access : read-write
CAS : Column Address Size.
bits : 11 - 14 (4 bit)
access : read-write
CSINTERVALUNIT : CS interval unit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CSINTERVALUNIT_0
The CS interval unit is 1 serial clock cycle
0x1 : CSINTERVALUNIT_1
The CS interval unit is 256 serial clock cycle
End of enumeration elements list.
CSINTERVAL : This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.
bits : 16 - 31 (16 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x25CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x261C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x2744 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x27F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
AHB RX Buffer 2 Control Register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSZ : AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.
bits : 0 - 7 (8 bit)
access : read-write
MSTRID : This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.
bits : 16 - 19 (4 bit)
access : read-write
PRIORITY : This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.
bits : 24 - 25 (2 bit)
access : read-write
PREFETCHEN : AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
bits : 31 - 31 (1 bit)
access : read-write
LUT 0
address_offset : 0x2864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x28C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Flash A1 Control Register 2
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARDSEQID : Sequence Index for AHB Read triggered Command in LUT.
bits : 0 - 3 (4 bit)
access : read-write
ARDSEQNUM : Sequence Number for AHB Read triggered Command in LUT.
bits : 5 - 7 (3 bit)
access : read-write
AWRSEQID : Sequence Index for AHB Write triggered Command.
bits : 8 - 11 (4 bit)
access : read-write
AWRSEQNUM : Sequence Number for AHB Write triggered Command.
bits : 13 - 15 (3 bit)
access : read-write
AWRWAIT : For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface
bits : 16 - 27 (12 bit)
access : read-write
AWRWAITUNIT : AWRWAIT unit
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0 : AWRWAITUNIT_0
The AWRWAIT unit is 2 ahb clock cycle
0x1 : AWRWAITUNIT_1
The AWRWAIT unit is 8 ahb clock cycle
0x2 : AWRWAITUNIT_2
The AWRWAIT unit is 32 ahb clock cycle
0x3 : AWRWAITUNIT_3
The AWRWAIT unit is 128 ahb clock cycle
0x4 : AWRWAITUNIT_4
The AWRWAIT unit is 512 ahb clock cycle
0x5 : AWRWAITUNIT_5
The AWRWAIT unit is 2048 ahb clock cycle
0x6 : AWRWAITUNIT_6
The AWRWAIT unit is 8192 ahb clock cycle
0x7 : AWRWAITUNIT_7
The AWRWAIT unit is 32768 ahb clock cycle
End of enumeration elements list.
CLRINSTRPTR : Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.
bits : 31 - 31 (1 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x29D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x2BB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
AHB RX Buffer 3 Control Register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSZ : AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.
bits : 0 - 7 (8 bit)
access : read-write
MSTRID : This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.
bits : 16 - 19 (4 bit)
access : read-write
PRIORITY : This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.
bits : 24 - 25 (2 bit)
access : read-write
PREFETCHEN : AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
bits : 31 - 31 (1 bit)
access : read-write
LUT 0
address_offset : 0x2CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x2D94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x2F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x2F7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP TX FIFO Data Register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0x3168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x319C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x3358 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x33F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x354C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x3650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x3744 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x3940 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x3D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Module Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHBBUSWAIT : AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmited after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response
bits : 0 - 15 (16 bit)
access : read-write
SEQWAIT : Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles
bits : 16 - 31 (16 bit)
access : read-write
LUT 0
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x4258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x44CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x4744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x4C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x4EC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x514C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x53D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x5668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x58FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x5B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x5E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Flash A1 Control Register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSHSZ : Flash Size in KByte.
bits : 0 - 22 (23 bit)
access : read-write
LUT 0
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x60D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x6374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Flash A2 Control Register 0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSHSZ : Flash Size in KByte.
bits : 0 - 22 (23 bit)
access : read-write
LUT 0
address_offset : 0x661C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Flash B1 Control Register 0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSHSZ : Flash Size in KByte.
bits : 0 - 22 (23 bit)
access : read-write
LUT 0
address_offset : 0x68C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x6B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Flash B2 Control Register 0
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSHSZ : Flash Size in KByte.
bits : 0 - 22 (23 bit)
access : read-write
LUT 0
address_offset : 0x6E2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x70E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x73A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x7660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x7924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x7BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x7EB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Module Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAHBBUFOPT : This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : CLRAHBBUFOPT_0
AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
0x1 : CLRAHBBUFOPT_1
AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
End of enumeration elements list.
CLRLEARNPHASE : The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.
bits : 14 - 14 (1 bit)
access : read-write
SAMEDEVICEEN : All external devices are same devices (both in types and size) for A1/A2/B1/B2.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SAMEDEVICEEN_0
In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored.
0x1 : SAMEDEVICEEN_1
FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
End of enumeration elements list.
SCKBDIFFOPT : SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SCKBDIFFOPT_0
SCKB pad is used as port B SCK clock output. Port B flash access is available.
0x1 : SCKBDIFFOPT_1
SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available.
End of enumeration elements list.
RESUMEWAIT : Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
bits : 24 - 31 (8 bit)
access : read-write
LUT 0
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x8188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x845C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x8734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x8A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x8CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x8FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
LUT 0
address_offset : 0x92BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Flash Control Register 4
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WMOPT1 : Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : WMOPT1_0
DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode.
0x1 : WMOPT1_1
DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.
End of enumeration elements list.
WMENA : Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WMENA_0
Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
0x1 : WMENA_1
Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
End of enumeration elements list.
WMENB : Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : WMENB_0
Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
0x1 : WMENB_1
Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
End of enumeration elements list.
LUT 0
address_offset : 0x95A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0x9898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x9B8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0x9E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP Control Register 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFAR : Serial Flash Address for IP command.
bits : 0 - 31 (32 bit)
access : read-write
LUT 0
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
LUT 0
address_offset : 0xA180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP Control Register 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDATSZ : Flash Read/Program Data Size (in Bytes) for IP command.
bits : 0 - 15 (16 bit)
access : read-write
ISEQID : Sequence Index in LUT for IP command.
bits : 16 - 19 (4 bit)
access : read-write
ISEQNUM : Sequence Number for IP command: ISEQNUM+1.
bits : 24 - 26 (3 bit)
access : read-write
IPAREN : Parallel mode Enabled for IP command.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : IPAREN_0
Flash will be accessed in Individual mode.
0x1 : IPAREN_1
Flash will be accessed in Parallel mode.
End of enumeration elements list.
IP RX FIFO Data Register 0
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP Command Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRG : Setting this bit will trigger an IP Command.
bits : 0 - 0 (1 bit)
access : read-write
IP RX FIFO Control Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRIPRXF : Clear all valid data entries in IP RX FIFO.
bits : 0 - 0 (1 bit)
access : read-write
RXDMAEN : IP RX FIFO reading by DMA enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RXDMAEN_0
IP RX FIFO would be read by processor.
0x1 : RXDMAEN_1
IP RX FIFO would be read by DMA.
End of enumeration elements list.
RXWMRK : Watermark level is (RXWMRK+1)*64 Bits.
bits : 2 - 5 (4 bit)
access : read-write
IP RX FIFO Data Register 0
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Control Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRIPTXF : Clear all valid data entries in IP TX FIFO.
bits : 0 - 0 (1 bit)
access : read-write
TXDMAEN : IP TX FIFO filling by DMA enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TXDMAEN_0
IP TX FIFO would be filled by processor.
0x1 : TXDMAEN_1
IP TX FIFO would be filled by DMA.
End of enumeration elements list.
TXWMRK : Watermark level is (TXWMRK+1)*64 Bits.
bits : 2 - 5 (4 bit)
access : read-write
AHB Bus Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APAREN : Parallel mode enabled for AHB triggered Command (both read and write) .
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : APAREN_0
Flash will be accessed in Individual mode.
0x1 : APAREN_1
Flash will be accessed in Parallel mode.
End of enumeration elements list.
CACHABLEEN : Enable AHB bus cachable read access support.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CACHABLEEN_0
Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
0x1 : CACHABLEEN_1
Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
End of enumeration elements list.
BUFFERABLEEN : Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BUFFERABLEEN_0
Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished.
0x1 : BUFFERABLEEN_1
Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.
End of enumeration elements list.
PREFETCHEN : AHB Read Prefetch Enable.
bits : 5 - 5 (1 bit)
access : read-write
READADDROPT : AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : READADDROPT_0
There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
0x1 : READADDROPT_1
There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement.
End of enumeration elements list.
LUT 0
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
IP TX FIFO Data Register 0
address_offset : 0xC54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
IP RX FIFO Data Register 0
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
Flash A1 Control Register 1
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCSS : Serial Flash CS setup time.
bits : 0 - 4 (5 bit)
access : read-write
TCSH : Serial Flash CS Hold time.
bits : 5 - 9 (5 bit)
access : read-write
WA : Word Addressable.
bits : 10 - 10 (1 bit)
access : read-write
CAS : Column Address Size.
bits : 11 - 14 (4 bit)
access : read-write
CSINTERVALUNIT : CS interval unit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CSINTERVALUNIT_0
The CS interval unit is 1 serial clock cycle
0x1 : CSINTERVALUNIT_1
The CS interval unit is 256 serial clock cycle
End of enumeration elements list.
CSINTERVAL : This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.
bits : 16 - 31 (16 bit)
access : read-write
Status Register 0
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEQIDLE : This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.
bits : 0 - 0 (1 bit)
access : read-only
ARBIDLE : This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
bits : 1 - 1 (1 bit)
access : read-only
ARBCMDSRC : This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
bits : 2 - 3 (2 bit)
access : read-only
Enumeration:
0 : ARBCMDSRC_0
Triggered by AHB read command (triggered by AHB read).
0x1 : ARBCMDSRC_1
Triggered by AHB write command (triggered by AHB Write).
0x2 : ARBCMDSRC_2
Triggered by IP command (triggered by setting register bit IPCMD.TRG).
0x3 : ARBCMDSRC_3
Triggered by suspended command (resumed).
End of enumeration elements list.
IP RX FIFO Data Register 0
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
LUT 0
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND0 : OPERAND0
bits : 0 - 7 (8 bit)
access : read-write
NUM_PADS0 : NUM_PADS0
bits : 8 - 9 (2 bit)
access : read-write
OPCODE0 : OPCODE
bits : 10 - 15 (6 bit)
access : read-write
OPERAND1 : OPERAND1
bits : 16 - 23 (8 bit)
access : read-write
NUM_PADS1 : NUM_PADS1
bits : 24 - 25 (2 bit)
access : read-write
OPCODE1 : OPCODE1
bits : 26 - 31 (6 bit)
access : read-write
Status Register 1
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHBCMDERRID : Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
bits : 0 - 3 (4 bit)
access : read-only
AHBCMDERRCODE : Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : AHBCMDERRCODE_0
No error.
0x2 : AHBCMDERRCODE_2
AHB Write command with JMP_ON_CS instruction used in the sequence.
0x3 : AHBCMDERRCODE_3
There is unknown instruction opcode in the sequence.
0x4 : AHBCMDERRCODE_4
Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
0x5 : AHBCMDERRCODE_5
Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
0xE : AHBCMDERRCODE_14
Sequence execution timeout.
End of enumeration elements list.
IPCMDERRID : Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).
bits : 16 - 19 (4 bit)
access : read-only
IPCMDERRCODE : Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : IPCMDERRCODE_0
No error.
0x2 : IPCMDERRCODE_2
IP command with JMP_ON_CS instruction used in the sequence.
0x3 : IPCMDERRCODE_3
There is unknown instruction opcode in the sequence.
0x4 : IPCMDERRCODE_4
Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
0x5 : IPCMDERRCODE_5
Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
0x6 : IPCMDERRCODE_6
Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
0xE : IPCMDERRCODE_14
Sequence execution timeout.
0xF : IPCMDERRCODE_15
Flash boundary crossed.
End of enumeration elements list.
Status Register 2
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ASLVLOCK : Flash A sample clock slave delay line locked.
bits : 0 - 0 (1 bit)
access : read-only
AREFLOCK : Flash A sample clock reference delay line locked.
bits : 1 - 1 (1 bit)
access : read-only
ASLVSEL : Flash A sample clock slave delay line delay cell number selection .
bits : 2 - 7 (6 bit)
access : read-only
AREFSEL : Flash A sample clock reference delay line delay cell number selection.
bits : 8 - 13 (6 bit)
access : read-only
BSLVLOCK : Flash B sample clock slave delay line locked.
bits : 16 - 16 (1 bit)
access : read-only
BREFLOCK : Flash B sample clock reference delay line locked.
bits : 17 - 17 (1 bit)
access : read-only
BSLVSEL : Flash B sample clock slave delay line delay cell number selection.
bits : 18 - 23 (6 bit)
access : read-only
BREFSEL : Flash B sample clock reference delay line delay cell number selection.
bits : 24 - 29 (6 bit)
access : read-only
AHB Suspend Status Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Indicates if an AHB read prefetch command sequence has been suspended.
bits : 0 - 0 (1 bit)
access : read-only
BUFID : AHB RX BUF ID for suspended command sequence.
bits : 1 - 3 (3 bit)
access : read-only
DATLFT : Left Data size for suspended command sequence (in byte).
bits : 16 - 31 (16 bit)
access : read-only
IP RX FIFO Status Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FILL : Fill level of IP RX FIFO.
bits : 0 - 7 (8 bit)
access : read-only
RDCNTR : Total Read Data Counter: RDCNTR * 64 Bits.
bits : 16 - 31 (16 bit)
access : read-only
IP RX FIFO Data Register 0
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
IP TX FIFO Status Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FILL : Fill level of IP TX FIFO.
bits : 0 - 7 (8 bit)
access : read-only
WRCNTR : Total Write Data Counter: WRCNTR * 64 Bits.
bits : 16 - 31 (16 bit)
access : read-only
IP TX FIFO Data Register 0
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 31 (32 bit)
access : write-only
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