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XBARA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SEL0

SEL8

SEL9

SEL10

SEL11

SEL12

SEL13

SEL14

SEL15

SEL1

SEL16

SEL17

SEL18

SEL19

SEL20

SEL21

SEL22

SEL23

SEL24

SEL25

SEL26

SEL27

SEL28

SEL29

SEL30

SEL31

SEL2

SEL32

SEL33

SEL34

SEL35

SEL36

SEL37

SEL38

SEL39

SEL40

SEL41

SEL42

SEL43

SEL44

SEL45

SEL46

SEL47

SEL3

SEL48

SEL49

SEL50

SEL51

SEL52

SEL53

SEL54

SEL55

SEL56

SEL57

SEL58

SEL59

SEL60

SEL61

SEL62

SEL63

SEL4

SEL64

SEL65

CTRL0

CTRL1

SEL5

SEL6

SEL7


SEL0

Crossbar A Select Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL0 SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1

SEL0 : Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL1 : Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL8

Crossbar A Select Register 8
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL8 SEL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL16 SEL17

SEL16 : Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL17 : Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL9

Crossbar A Select Register 9
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL9 SEL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL18 SEL19

SEL18 : Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL19 : Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL10

Crossbar A Select Register 10
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL10 SEL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL20 SEL21

SEL20 : Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL21 : Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL11

Crossbar A Select Register 11
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL11 SEL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL22 SEL23

SEL22 : Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL23 : Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL12

Crossbar A Select Register 12
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL12 SEL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL24 SEL25

SEL24 : Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL25 : Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL13

Crossbar A Select Register 13
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL13 SEL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL26 SEL27

SEL26 : Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL27 : Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL14

Crossbar A Select Register 14
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL14 SEL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL28 SEL29

SEL28 : Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL29 : Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL15

Crossbar A Select Register 15
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL15 SEL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL30 SEL31

SEL30 : Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL31 : Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL1

Crossbar A Select Register 1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL1 SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL2 SEL3

SEL2 : Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL3 : Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL16

Crossbar A Select Register 16
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL16 SEL16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL32 SEL33

SEL32 : Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL33 : Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL17

Crossbar A Select Register 17
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL17 SEL17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL34 SEL35

SEL34 : Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL35 : Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL18

Crossbar A Select Register 18
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL18 SEL18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL36 SEL37

SEL36 : Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL37 : Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL19

Crossbar A Select Register 19
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL19 SEL19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL38 SEL39

SEL38 : Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL39 : Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL20

Crossbar A Select Register 20
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL20 SEL20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL40 SEL41

SEL40 : Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL41 : Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL21

Crossbar A Select Register 21
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL21 SEL21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL42 SEL43

SEL42 : Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL43 : Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL22

Crossbar A Select Register 22
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL22 SEL22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL44 SEL45

SEL44 : Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL45 : Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL23

Crossbar A Select Register 23
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL23 SEL23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL46 SEL47

SEL46 : Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL47 : Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL24

Crossbar A Select Register 24
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL24 SEL24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL48 SEL49

SEL48 : Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL49 : Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL25

Crossbar A Select Register 25
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL25 SEL25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL50 SEL51

SEL50 : Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL51 : Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL26

Crossbar A Select Register 26
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL26 SEL26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL52 SEL53

SEL52 : Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL53 : Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL27

Crossbar A Select Register 27
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL27 SEL27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL54 SEL55

SEL54 : Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL55 : Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL28

Crossbar A Select Register 28
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL28 SEL28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL56 SEL57

SEL56 : Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL57 : Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL29

Crossbar A Select Register 29
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL29 SEL29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL58 SEL59

SEL58 : Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL59 : Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL30

Crossbar A Select Register 30
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL30 SEL30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL60 SEL61

SEL60 : Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL61 : Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL31

Crossbar A Select Register 31
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL31 SEL31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL62 SEL63

SEL62 : Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL63 : Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL2

Crossbar A Select Register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL2 SEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL4 SEL5

SEL4 : Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL5 : Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL32

Crossbar A Select Register 32
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL32 SEL32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL64 SEL65

SEL64 : Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL65 : Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL33

Crossbar A Select Register 33
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL33 SEL33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL66 SEL67

SEL66 : Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL67 : Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL34

Crossbar A Select Register 34
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL34 SEL34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL68 SEL69

SEL68 : Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL69 : Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL35

Crossbar A Select Register 35
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL35 SEL35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL70 SEL71

SEL70 : Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL71 : Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL36

Crossbar A Select Register 36
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL36 SEL36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL72 SEL73

SEL72 : Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL73 : Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL37

Crossbar A Select Register 37
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL37 SEL37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL74 SEL75

SEL74 : Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL75 : Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL38

Crossbar A Select Register 38
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL38 SEL38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL76 SEL77

SEL76 : Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL77 : Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL39

Crossbar A Select Register 39
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL39 SEL39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL78 SEL79

SEL78 : Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL79 : Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL40

Crossbar A Select Register 40
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL40 SEL40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL80 SEL81

SEL80 : Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL81 : Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL41

Crossbar A Select Register 41
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL41 SEL41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL82 SEL83

SEL82 : Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL83 : Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL42

Crossbar A Select Register 42
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL42 SEL42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL84 SEL85

SEL84 : Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL85 : Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL43

Crossbar A Select Register 43
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL43 SEL43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL86 SEL87

SEL86 : Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL87 : Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL44

Crossbar A Select Register 44
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL44 SEL44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL88 SEL89

SEL88 : Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL89 : Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL45

Crossbar A Select Register 45
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL45 SEL45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL90 SEL91

SEL90 : Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL91 : Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL46

Crossbar A Select Register 46
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL46 SEL46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL92 SEL93

SEL92 : Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL93 : Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL47

Crossbar A Select Register 47
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL47 SEL47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL94 SEL95

SEL94 : Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL95 : Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL3

Crossbar A Select Register 3
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL3 SEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL6 SEL7

SEL6 : Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL7 : Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL48

Crossbar A Select Register 48
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL48 SEL48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL96 SEL97

SEL96 : Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL97 : Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL49

Crossbar A Select Register 49
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL49 SEL49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL98 SEL99

SEL98 : Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL99 : Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL50

Crossbar A Select Register 50
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL50 SEL50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL100 SEL101

SEL100 : Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL101 : Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL51

Crossbar A Select Register 51
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL51 SEL51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL102 SEL103

SEL102 : Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL103 : Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL52

Crossbar A Select Register 52
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL52 SEL52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL104 SEL105

SEL104 : Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL105 : Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL53

Crossbar A Select Register 53
address_offset : 0x6A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL53 SEL53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL106 SEL107

SEL106 : Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL107 : Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL54

Crossbar A Select Register 54
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL54 SEL54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL108 SEL109

SEL108 : Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL109 : Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL55

Crossbar A Select Register 55
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL55 SEL55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL110 SEL111

SEL110 : Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL111 : Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL56

Crossbar A Select Register 56
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL56 SEL56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL112 SEL113

SEL112 : Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL113 : Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL57

Crossbar A Select Register 57
address_offset : 0x72 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL57 SEL57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL114 SEL115

SEL114 : Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL115 : Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL58

Crossbar A Select Register 58
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL58 SEL58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL116 SEL117

SEL116 : Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL117 : Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL59

Crossbar A Select Register 59
address_offset : 0x76 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL59 SEL59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL118 SEL119

SEL118 : Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL119 : Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL60

Crossbar A Select Register 60
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL60 SEL60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL120 SEL121

SEL120 : Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL121 : Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL61

Crossbar A Select Register 61
address_offset : 0x7A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL61 SEL61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL122 SEL123

SEL122 : Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL123 : Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL62

Crossbar A Select Register 62
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL62 SEL62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL124 SEL125

SEL124 : Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL125 : Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL63

Crossbar A Select Register 63
address_offset : 0x7E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL63 SEL63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL126 SEL127

SEL126 : Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL127 : Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL4

Crossbar A Select Register 4
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL4 SEL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL8 SEL9

SEL8 : Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL9 : Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL64

Crossbar A Select Register 64
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL64 SEL64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL128 SEL129

SEL128 : Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL129 : Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL65

Crossbar A Select Register 65
address_offset : 0x82 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL65 SEL65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL130 SEL131

SEL130 : Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL131 : Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


CTRL0

Crossbar A Control Register 0
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN0 IEN0 EDGE0 STS0 DEN1 IEN1 EDGE1 STS1

DEN0 : DMA Enable for XBAR_OUT0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DEN0_0

DMA disabled

0x1 : DEN0_1

DMA enabled

End of enumeration elements list.

IEN0 : Interrupt Enable for XBAR_OUT0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : IEN0_0

Interrupt disabled

0x1 : IEN0_1

Interrupt enabled

End of enumeration elements list.

EDGE0 : Active edge for edge detection on XBAR_OUT0
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : EDGE0_0

STS0 never asserts

0x1 : EDGE0_1

STS0 asserts on rising edges of XBAR_OUT0

0x2 : EDGE0_2

STS0 asserts on falling edges of XBAR_OUT0

0x3 : EDGE0_3

STS0 asserts on rising and falling edges of XBAR_OUT0

End of enumeration elements list.

STS0 : Edge detection status for XBAR_OUT0
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : STS0_0

Active edge not yet detected on XBAR_OUT0

0x1 : STS0_1

Active edge detected on XBAR_OUT0

End of enumeration elements list.

DEN1 : DMA Enable for XBAR_OUT1
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DEN1_0

DMA disabled

0x1 : DEN1_1

DMA enabled

End of enumeration elements list.

IEN1 : Interrupt Enable for XBAR_OUT1
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : IEN1_0

Interrupt disabled

0x1 : IEN1_1

Interrupt enabled

End of enumeration elements list.

EDGE1 : Active edge for edge detection on XBAR_OUT1
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0 : EDGE1_0

STS1 never asserts

0x1 : EDGE1_1

STS1 asserts on rising edges of XBAR_OUT1

0x2 : EDGE1_2

STS1 asserts on falling edges of XBAR_OUT1

0x3 : EDGE1_3

STS1 asserts on rising and falling edges of XBAR_OUT1

End of enumeration elements list.

STS1 : Edge detection status for XBAR_OUT1
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : STS1_0

Active edge not yet detected on XBAR_OUT1

0x1 : STS1_1

Active edge detected on XBAR_OUT1

End of enumeration elements list.


CTRL1

Crossbar A Control Register 1
address_offset : 0x86 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN2 IEN2 EDGE2 STS2 DEN3 IEN3 EDGE3 STS3

DEN2 : DMA Enable for XBAR_OUT2
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DEN2_0

DMA disabled

0x1 : DEN2_1

DMA enabled

End of enumeration elements list.

IEN2 : Interrupt Enable for XBAR_OUT2
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : IEN2_0

Interrupt disabled

0x1 : IEN2_1

Interrupt enabled

End of enumeration elements list.

EDGE2 : Active edge for edge detection on XBAR_OUT2
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : EDGE2_0

STS2 never asserts

0x1 : EDGE2_1

STS2 asserts on rising edges of XBAR_OUT2

0x2 : EDGE2_2

STS2 asserts on falling edges of XBAR_OUT2

0x3 : EDGE2_3

STS2 asserts on rising and falling edges of XBAR_OUT2

End of enumeration elements list.

STS2 : Edge detection status for XBAR_OUT2
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : STS2_0

Active edge not yet detected on XBAR_OUT2

0x1 : STS2_1

Active edge detected on XBAR_OUT2

End of enumeration elements list.

DEN3 : DMA Enable for XBAR_OUT3
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DEN3_0

DMA disabled

0x1 : DEN3_1

DMA enabled

End of enumeration elements list.

IEN3 : Interrupt Enable for XBAR_OUT3
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : IEN3_0

Interrupt disabled

0x1 : IEN3_1

Interrupt enabled

End of enumeration elements list.

EDGE3 : Active edge for edge detection on XBAR_OUT3
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0 : EDGE3_0

STS3 never asserts

0x1 : EDGE3_1

STS3 asserts on rising edges of XBAR_OUT3

0x2 : EDGE3_2

STS3 asserts on falling edges of XBAR_OUT3

0x3 : EDGE3_3

STS3 asserts on rising and falling edges of XBAR_OUT3

End of enumeration elements list.

STS3 : Edge detection status for XBAR_OUT3
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : STS3_0

Active edge not yet detected on XBAR_OUT3

0x1 : STS3_1

Active edge detected on XBAR_OUT3

End of enumeration elements list.


SEL5

Crossbar A Select Register 5
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL5 SEL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL10 SEL11

SEL10 : Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL11 : Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL6

Crossbar A Select Register 6
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL6 SEL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL12 SEL13

SEL12 : Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL13 : Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write


SEL7

Crossbar A Select Register 7
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL7 SEL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL14 SEL15

SEL14 : Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment)
bits : 0 - 6 (7 bit)
access : read-write

SEL15 : Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment)
bits : 8 - 14 (7 bit)
access : read-write



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