\n
address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
GPC Interface control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEGA_PDN_REQ : MEGA domain power down request
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MEGA_PDN_REQ_0
No Request
0x1 : MEGA_PDN_REQ_1
Request power down sequence
End of enumeration elements list.
MEGA_PUP_REQ : MEGA domain power up request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MEGA_PUP_REQ_0
No Request
0x1 : MEGA_PUP_REQ_1
Request power up sequence
End of enumeration elements list.
PDRAM0_PGE : FlexRAM PDRAM0 Power Gate Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : PDRAM0_PGE_0
FlexRAM PDRAM0 domain will keep power on even if CPU core is power down.
0x1 : PDRAM0_PGE_1
FlexRAM PDRAM0 domain will be power down once when CPU core is power down.
End of enumeration elements list.
IRQ masking register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR3 : IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write
IRQ masking register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR4 : IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write
IRQ status resister 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR1 : IRQ[31:0] status, read only
bits : 0 - 31 (32 bit)
access : read-only
IRQ status resister 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR2 : IRQ[63:32] status, read only
bits : 0 - 31 (32 bit)
access : read-only
IRQ status resister 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR3 : IRQ[95:64] status, read only
bits : 0 - 31 (32 bit)
access : read-only
IRQ status resister 4
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR4 : IRQ[127:96] status, read only
bits : 0 - 31 (32 bit)
access : read-only
IRQ masking register 5
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR5 : IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write
IRQ status resister 5
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR4 : IRQ[159:128] status, read only
bits : 0 - 31 (32 bit)
access : read-only
IRQ masking register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR1 : IRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write
IRQ masking register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR2 : IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write
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