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CCM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CCR

CACRR

CBCDR

CBCMR

CSCMR1

CSCMR2

CSCDR1

CS1CDR

CS2CDR

CDCDR

CSCDR2

CSCDR3

CDHIPR

CLPCR

CISR

CIMR

CCOSR

CGPR

CCGR0

CCGR1

CCGR2

CCGR3

CCGR4

CCGR5

CSR

CCGR6

CCGR7

CMEOR

CCSR


CCR

CCM Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCNT COSC_EN REG_BYPASS_COUNT RBC_EN

OSCNT : Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened.
bits : 0 - 7 (8 bit)
access : read-write

COSC_EN : On chip oscillator enable bit - this bit value is reflected on the output cosc_en
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : COSC_EN_0

disable on chip oscillator

0x1 : COSC_EN_1

enable on chip oscillator

End of enumeration elements list.

REG_BYPASS_COUNT : Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ
bits : 21 - 26 (6 bit)
access : read-write

Enumeration:

0 : REG_BYPASS_COUNT_0

no delay

0x1 : REG_BYPASS_COUNT_1

1 CKIL clock period delay

0x3F : REG_BYPASS_COUNT_63

63 CKIL clock periods delay

End of enumeration elements list.

RBC_EN : Enable for REG_BYPASS_COUNTER
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : RBC_EN_0

REG_BYPASS_COUNTER disabled

0x1 : RBC_EN_1

REG_BYPASS_COUNTER enabled.

End of enumeration elements list.


CACRR

CCM Arm Clock Root Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CACRR CACRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARM_PODF

ARM_PODF : Divider for ARM clock root
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : ARM_PODF_0

divide by 1

0x1 : ARM_PODF_1

divide by 2

0x2 : ARM_PODF_2

divide by 3

0x3 : ARM_PODF_3

divide by 4

0x4 : ARM_PODF_4

divide by 5

0x5 : ARM_PODF_5

divide by 6

0x6 : ARM_PODF_6

divide by 7

0x7 : ARM_PODF_7

divide by 8

End of enumeration elements list.


CBCDR

CCM Bus Clock Divider Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBCDR CBCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEMC_CLK_SEL SEMC_ALT_CLK_SEL IPG_PODF AHB_PODF SEMC_PODF PERIPH_CLK_SEL PERIPH_CLK2_PODF

SEMC_CLK_SEL : SEMC clock source select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SEMC_CLK_SEL_0

Periph_clk output will be used as SEMC clock root

0x1 : SEMC_CLK_SEL_1

SEMC alternative clock will be used as SEMC clock root

End of enumeration elements list.

SEMC_ALT_CLK_SEL : SEMC alternative clock select
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SEMC_ALT_CLK_SEL_0

PLL2 PFD2 will be selected as alternative clock for SEMC root clock

0x1 : SEMC_ALT_CLK_SEL_1

PLL3 PFD1 will be selected as alternative clock for SEMC root clock

End of enumeration elements list.

IPG_PODF : Divider for ipg podf.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : IPG_PODF_0

divide by 1

0x1 : IPG_PODF_1

divide by 2

0x2 : IPG_PODF_2

divide by 3

0x3 : IPG_PODF_3

divide by 4

End of enumeration elements list.

AHB_PODF : Divider for AHB PODF
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0 : AHB_PODF_0

divide by 1

0x1 : AHB_PODF_1

divide by 2

0x2 : AHB_PODF_2

divide by 3

0x3 : AHB_PODF_3

divide by 4

0x4 : AHB_PODF_4

divide by 5

0x5 : AHB_PODF_5

divide by 6

0x6 : AHB_PODF_6

divide by 7

0x7 : AHB_PODF_7

divide by 8

End of enumeration elements list.

SEMC_PODF : Post divider for SEMC clock
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : SEMC_PODF_0

divide by 1

0x1 : SEMC_PODF_1

divide by 2

0x2 : SEMC_PODF_2

divide by 3

0x3 : SEMC_PODF_3

divide by 4

0x4 : SEMC_PODF_4

divide by 5

0x5 : SEMC_PODF_5

divide by 6

0x6 : SEMC_PODF_6

divide by 7

0x7 : SEMC_PODF_7

divide by 8

End of enumeration elements list.

PERIPH_CLK_SEL : Selector for peripheral main clock
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : PERIPH_CLK_SEL_0

derive clock from pre_periph_clk_sel

0x1 : PERIPH_CLK_SEL_1

derive clock from periph_clk2_clk_divided

End of enumeration elements list.

PERIPH_CLK2_PODF : Divider for periph_clk2_podf.
bits : 27 - 29 (3 bit)
access : read-write

Enumeration:

0 : PERIPH_CLK2_PODF_0

divide by 1

0x1 : PERIPH_CLK2_PODF_1

divide by 2

0x2 : PERIPH_CLK2_PODF_2

divide by 3

0x3 : PERIPH_CLK2_PODF_3

divide by 4

0x4 : PERIPH_CLK2_PODF_4

divide by 5

0x5 : PERIPH_CLK2_PODF_5

divide by 6

0x6 : PERIPH_CLK2_PODF_6

divide by 7

0x7 : PERIPH_CLK2_PODF_7

divide by 8

End of enumeration elements list.


CBCMR

CCM Bus Clock Multiplexer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBCMR CBCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPI_CLK_SEL FLEXSPI2_CLK_SEL PERIPH_CLK2_SEL TRACE_CLK_SEL PRE_PERIPH_CLK_SEL LCDIF_PODF LPSPI_PODF FLEXSPI2_PODF

LPSPI_CLK_SEL : Selector for lpspi clock multiplexer
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : LPSPI_CLK_SEL_0

derive clock from PLL3 PFD1 clk

0x1 : LPSPI_CLK_SEL_1

derive clock from PLL3 PFD0

0x2 : LPSPI_CLK_SEL_2

derive clock from PLL2

0x3 : LPSPI_CLK_SEL_3

derive clock from PLL2 PFD2

End of enumeration elements list.

FLEXSPI2_CLK_SEL : Selector for flexspi2 clock multiplexer
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : FLEXSPI2_CLK_SEL_0

derive clock from PLL2 PFD2

0x1 : FLEXSPI2_CLK_SEL_1

derive clock from PLL3 PFD0

0x2 : FLEXSPI2_CLK_SEL_2

derive clock from PLL3 PFD1

0x3 : FLEXSPI2_CLK_SEL_3

derive clock from PLL2 (pll2_main_clk)

End of enumeration elements list.

PERIPH_CLK2_SEL : Selector for peripheral clk2 clock multiplexer
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : PERIPH_CLK2_SEL_0

derive clock from pll3_sw_clk

0x1 : PERIPH_CLK2_SEL_1

derive clock from osc_clk (pll1_ref_clk)

0x2 : PERIPH_CLK2_SEL_2

derive clock from pll2_bypass_clk

End of enumeration elements list.

TRACE_CLK_SEL : Selector for Trace clock multiplexer
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : TRACE_CLK_SEL_0

derive clock from PLL2

0x1 : TRACE_CLK_SEL_1

derive clock from PLL2 PFD2

0x2 : TRACE_CLK_SEL_2

derive clock from PLL2 PFD0

0x3 : TRACE_CLK_SEL_3

derive clock from PLL2 PFD1

End of enumeration elements list.

PRE_PERIPH_CLK_SEL : Selector for pre_periph clock multiplexer
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0 : PRE_PERIPH_CLK_SEL_0

derive clock from PLL2

0x1 : PRE_PERIPH_CLK_SEL_1

derive clock from PLL2 PFD2

0x2 : PRE_PERIPH_CLK_SEL_2

derive clock from PLL2 PFD0

0x3 : PRE_PERIPH_CLK_SEL_3

derive clock from divided PLL1

End of enumeration elements list.

LCDIF_PODF : Post-divider for LCDIF clock.
bits : 23 - 25 (3 bit)
access : read-write

Enumeration:

0 : LCDIF_PODF_0

divide by 1

0x1 : LCDIF_PODF_1

divide by 2

0x2 : LCDIF_PODF_2

divide by 3

0x3 : LCDIF_PODF_3

divide by 4

0x4 : LCDIF_PODF_4

divide by 5

0x5 : LCDIF_PODF_5

divide by 6

0x6 : LCDIF_PODF_6

divide by 7

0x7 : LCDIF_PODF_7

divide by 8

End of enumeration elements list.

LPSPI_PODF : Divider for LPSPI. Divider should be updated when output clock is gated.
bits : 26 - 28 (3 bit)
access : read-write

Enumeration:

0 : LPSPI_PODF_0

divide by 1

0x1 : LPSPI_PODF_1

divide by 2

0x2 : LPSPI_PODF_2

divide by 3

0x3 : LPSPI_PODF_3

divide by 4

0x4 : LPSPI_PODF_4

divide by 5

0x5 : LPSPI_PODF_5

divide by 6

0x6 : LPSPI_PODF_6

divide by 7

0x7 : LPSPI_PODF_7

divide by 8

End of enumeration elements list.

FLEXSPI2_PODF : Divider for flexspi2 clock root.
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0 : FLEXSPI2_PODF_0

divide by 1

0x1 : FLEXSPI2_PODF_1

divide by 2

0x2 : FLEXSPI2_PODF_2

divide by 3

0x3 : FLEXSPI2_PODF_3

divide by 4

0x4 : FLEXSPI2_PODF_4

divide by 5

0x5 : FLEXSPI2_PODF_5

divide by 6

0x6 : FLEXSPI2_PODF_6

divide by 7

0x7 : FLEXSPI2_PODF_7

divide by 8

End of enumeration elements list.


CSCMR1

CCM Serial Clock Multiplexer Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCMR1 CSCMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERCLK_PODF PERCLK_CLK_SEL SAI1_CLK_SEL SAI2_CLK_SEL SAI3_CLK_SEL USDHC1_CLK_SEL USDHC2_CLK_SEL FLEXSPI_PODF FLEXSPI_CLK_SEL

PERCLK_PODF : Divider for perclk podf.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

0x8 : DIVIDE_9

Divide by 9

0x9 : DIVIDE_10

Divide by 10

0xA : DIVIDE_11

Divide by 11

0xB : DIVIDE_12

Divide by 12

0xC : DIVIDE_13

Divide by 13

0xD : DIVIDE_14

Divide by 14

0xE : DIVIDE_15

Divide by 15

0xF : DIVIDE_16

Divide by 16

0x10 : DIVIDE_17

Divide by 17

0x11 : DIVIDE_18

Divide by 18

0x12 : DIVIDE_19

Divide by 19

0x13 : DIVIDE_20

Divide by 20

0x14 : DIVIDE_21

Divide by 21

0x15 : DIVIDE_22

Divide by 22

0x16 : DIVIDE_23

Divide by 23

0x17 : DIVIDE_24

Divide by 24

0x18 : DIVIDE_25

Divide by 25

0x19 : DIVIDE_26

Divide by 26

0x1A : DIVIDE_27

Divide by 27

0x1B : DIVIDE_28

Divide by 28

0x1C : DIVIDE_29

Divide by 29

0x1D : DIVIDE_30

Divide by 30

0x1E : DIVIDE_31

Divide by 31

0x1F : DIVIDE_32

Divide by 32

0x20 : DIVIDE_33

Divide by 33

0x21 : DIVIDE_34

Divide by 34

0x22 : DIVIDE_35

Divide by 35

0x23 : DIVIDE_36

Divide by 36

0x24 : DIVIDE_37

Divide by 37

0x25 : DIVIDE_38

Divide by 38

0x26 : DIVIDE_39

Divide by 39

0x27 : DIVIDE_40

Divide by 40

0x28 : DIVIDE_41

Divide by 41

0x29 : DIVIDE_42

Divide by 42

0x2A : DIVIDE_43

Divide by 43

0x2B : DIVIDE_44

Divide by 44

0x2C : DIVIDE_45

Divide by 45

0x2D : DIVIDE_46

Divide by 46

0x2E : DIVIDE_47

Divide by 47

0x2F : DIVIDE_48

Divide by 48

0x30 : DIVIDE_49

Divide by 49

0x31 : DIVIDE_50

Divide by 50

0x32 : DIVIDE_51

Divide by 51

0x33 : DIVIDE_52

Divide by 52

0x34 : DIVIDE_53

Divide by 53

0x35 : DIVIDE_54

Divide by 54

0x36 : DIVIDE_55

Divide by 55

0x37 : DIVIDE_56

Divide by 56

0x38 : DIVIDE_57

Divide by 57

0x39 : DIVIDE_58

Divide by 58

0x3A : DIVIDE_59

Divide by 59

0x3B : DIVIDE_60

Divide by 60

0x3C : DIVIDE_61

Divide by 61

0x3D : DIVIDE_62

Divide by 62

0x3E : DIVIDE_63

Divide by 63

0x3F : DIVIDE_64

Divide by 64

End of enumeration elements list.

PERCLK_CLK_SEL : Selector for the perclk clock multiplexor
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : PERCLK_CLK_SEL_0

derive clock from ipg clk root

0x1 : PERCLK_CLK_SEL_1

derive clock from osc_clk

End of enumeration elements list.

SAI1_CLK_SEL : Selector for sai1 clock multiplexer
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0 : SAI1_CLK_SEL_0

derive clock from PLL3 PFD2

0x1 : SAI1_CLK_SEL_1

derive clock from PLL5

0x2 : SAI1_CLK_SEL_2

derive clock from PLL4

End of enumeration elements list.

SAI2_CLK_SEL : Selector for sai2 clock multiplexer
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SAI2_CLK_SEL_0

derive clock from PLL3 PFD2

0x1 : SAI2_CLK_SEL_1

derive clock from PLL5

0x2 : SAI2_CLK_SEL_2

derive clock from PLL4

End of enumeration elements list.

SAI3_CLK_SEL : Selector for sai3/adc1/adc2 clock multiplexer
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : SAI3_CLK_SEL_0

derive clock from PLL3 PFD2

0x1 : SAI3_CLK_SEL_1

derive clock from PLL5

0x2 : SAI3_CLK_SEL_2

derive clock from PLL4

End of enumeration elements list.

USDHC1_CLK_SEL : Selector for usdhc1 clock multiplexer
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : USDHC1_CLK_SEL_0

derive clock from PLL2 PFD2

0x1 : USDHC1_CLK_SEL_1

derive clock from PLL2 PFD0

End of enumeration elements list.

USDHC2_CLK_SEL : Selector for usdhc2 clock multiplexer
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : USDHC2_CLK_SEL_0

derive clock from PLL2 PFD2

0x1 : USDHC2_CLK_SEL_1

derive clock from PLL2 PFD0

End of enumeration elements list.

FLEXSPI_PODF : Divider for flexspi clock root.
bits : 23 - 25 (3 bit)
access : read-write

Enumeration:

0 : FLEXSPI_PODF_0

divide by 1

0x1 : FLEXSPI_PODF_1

divide by 2

0x2 : FLEXSPI_PODF_2

divide by 3

0x3 : FLEXSPI_PODF_3

divide by 4

0x4 : FLEXSPI_PODF_4

divide by 5

0x5 : FLEXSPI_PODF_5

divide by 6

0x6 : FLEXSPI_PODF_6

divide by 7

0x7 : FLEXSPI_PODF_7

divide by 8

End of enumeration elements list.

FLEXSPI_CLK_SEL : Selector for flexspi clock multiplexer
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : FLEXSPI_CLK_SEL_0

derive clock from semc_clk_root_pre

0x1 : FLEXSPI_CLK_SEL_1

derive clock from pll3_sw_clk

0x2 : FLEXSPI_CLK_SEL_2

derive clock from PLL2 PFD2

0x3 : FLEXSPI_CLK_SEL_3

derive clock from PLL3 PFD0

End of enumeration elements list.


CSCMR2

CCM Serial Clock Multiplexer Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCMR2 CSCMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_CLK_PODF CAN_CLK_SEL FLEXIO2_CLK_SEL

CAN_CLK_PODF : Divider for CAN/CANFD clock podf.
bits : 2 - 7 (6 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

0x8 : DIVIDE_9

Divide by 9

0x9 : DIVIDE_10

Divide by 10

0xA : DIVIDE_11

Divide by 11

0xB : DIVIDE_12

Divide by 12

0xC : DIVIDE_13

Divide by 13

0xD : DIVIDE_14

Divide by 14

0xE : DIVIDE_15

Divide by 15

0xF : DIVIDE_16

Divide by 16

0x10 : DIVIDE_17

Divide by 17

0x11 : DIVIDE_18

Divide by 18

0x12 : DIVIDE_19

Divide by 19

0x13 : DIVIDE_20

Divide by 20

0x14 : DIVIDE_21

Divide by 21

0x15 : DIVIDE_22

Divide by 22

0x16 : DIVIDE_23

Divide by 23

0x17 : DIVIDE_24

Divide by 24

0x18 : DIVIDE_25

Divide by 25

0x19 : DIVIDE_26

Divide by 26

0x1A : DIVIDE_27

Divide by 27

0x1B : DIVIDE_28

Divide by 28

0x1C : DIVIDE_29

Divide by 29

0x1D : DIVIDE_30

Divide by 30

0x1E : DIVIDE_31

Divide by 31

0x1F : DIVIDE_32

Divide by 32

0x20 : DIVIDE_33

Divide by 33

0x21 : DIVIDE_34

Divide by 34

0x22 : DIVIDE_35

Divide by 35

0x23 : DIVIDE_36

Divide by 36

0x24 : DIVIDE_37

Divide by 37

0x25 : DIVIDE_38

Divide by 38

0x26 : DIVIDE_39

Divide by 39

0x27 : DIVIDE_40

Divide by 40

0x28 : DIVIDE_41

Divide by 41

0x29 : DIVIDE_42

Divide by 42

0x2A : DIVIDE_43

Divide by 43

0x2B : DIVIDE_44

Divide by 44

0x2C : DIVIDE_45

Divide by 45

0x2D : DIVIDE_46

Divide by 46

0x2E : DIVIDE_47

Divide by 47

0x2F : DIVIDE_48

Divide by 48

0x30 : DIVIDE_49

Divide by 49

0x31 : DIVIDE_50

Divide by 50

0x32 : DIVIDE_51

Divide by 51

0x33 : DIVIDE_52

Divide by 52

0x34 : DIVIDE_53

Divide by 53

0x35 : DIVIDE_54

Divide by 54

0x36 : DIVIDE_55

Divide by 55

0x37 : DIVIDE_56

Divide by 56

0x38 : DIVIDE_57

Divide by 57

0x39 : DIVIDE_58

Divide by 58

0x3A : DIVIDE_59

Divide by 59

0x3B : DIVIDE_60

Divide by 60

0x3C : DIVIDE_61

Divide by 61

0x3D : DIVIDE_62

Divide by 62

0x3E : DIVIDE_63

Divide by 63

0x3F : DIVIDE_64

Divide by 64

End of enumeration elements list.

CAN_CLK_SEL : Selector for CAN/CANFD clock multiplexer
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : CAN_CLK_SEL_0

derive clock from pll3_sw_clk divided clock (60M)

0x1 : CAN_CLK_SEL_1

derive clock from osc_clk (24M)

0x2 : CAN_CLK_SEL_2

derive clock from pll3_sw_clk divided clock (80M)

0x3 : CAN_CLK_SEL_3

Disable FlexCAN clock

End of enumeration elements list.

FLEXIO2_CLK_SEL : Selector for flexio2/flexio3 clock multiplexer
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

0 : FLEXIO2_CLK_SEL_0

derive clock from PLL4 divided clock

0x1 : FLEXIO2_CLK_SEL_1

derive clock from PLL3 PFD2 clock

0x2 : FLEXIO2_CLK_SEL_2

derive clock from PLL5 clock

0x3 : FLEXIO2_CLK_SEL_3

derive clock from pll3_sw_clk

End of enumeration elements list.


CSCDR1

CCM Serial Clock Divider Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCDR1 CSCDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_CLK_PODF UART_CLK_SEL USDHC1_PODF USDHC2_PODF TRACE_PODF

UART_CLK_PODF : Divider for uart clock podf.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

0x8 : DIVIDE_9

Divide by 9

0x9 : DIVIDE_10

Divide by 10

0xA : DIVIDE_11

Divide by 11

0xB : DIVIDE_12

Divide by 12

0xC : DIVIDE_13

Divide by 13

0xD : DIVIDE_14

Divide by 14

0xE : DIVIDE_15

Divide by 15

0xF : DIVIDE_16

Divide by 16

0x10 : DIVIDE_17

Divide by 17

0x11 : DIVIDE_18

Divide by 18

0x12 : DIVIDE_19

Divide by 19

0x13 : DIVIDE_20

Divide by 20

0x14 : DIVIDE_21

Divide by 21

0x15 : DIVIDE_22

Divide by 22

0x16 : DIVIDE_23

Divide by 23

0x17 : DIVIDE_24

Divide by 24

0x18 : DIVIDE_25

Divide by 25

0x19 : DIVIDE_26

Divide by 26

0x1A : DIVIDE_27

Divide by 27

0x1B : DIVIDE_28

Divide by 28

0x1C : DIVIDE_29

Divide by 29

0x1D : DIVIDE_30

Divide by 30

0x1E : DIVIDE_31

Divide by 31

0x1F : DIVIDE_32

Divide by 32

0x20 : DIVIDE_33

Divide by 33

0x21 : DIVIDE_34

Divide by 34

0x22 : DIVIDE_35

Divide by 35

0x23 : DIVIDE_36

Divide by 36

0x24 : DIVIDE_37

Divide by 37

0x25 : DIVIDE_38

Divide by 38

0x26 : DIVIDE_39

Divide by 39

0x27 : DIVIDE_40

Divide by 40

0x28 : DIVIDE_41

Divide by 41

0x29 : DIVIDE_42

Divide by 42

0x2A : DIVIDE_43

Divide by 43

0x2B : DIVIDE_44

Divide by 44

0x2C : DIVIDE_45

Divide by 45

0x2D : DIVIDE_46

Divide by 46

0x2E : DIVIDE_47

Divide by 47

0x2F : DIVIDE_48

Divide by 48

0x30 : DIVIDE_49

Divide by 49

0x31 : DIVIDE_50

Divide by 50

0x32 : DIVIDE_51

Divide by 51

0x33 : DIVIDE_52

Divide by 52

0x34 : DIVIDE_53

Divide by 53

0x35 : DIVIDE_54

Divide by 54

0x36 : DIVIDE_55

Divide by 55

0x37 : DIVIDE_56

Divide by 56

0x38 : DIVIDE_57

Divide by 57

0x39 : DIVIDE_58

Divide by 58

0x3A : DIVIDE_59

Divide by 59

0x3B : DIVIDE_60

Divide by 60

0x3C : DIVIDE_61

Divide by 61

0x3D : DIVIDE_62

Divide by 62

0x3E : DIVIDE_63

Divide by 63

0x3F : DIVIDE_64

Divide by 64

End of enumeration elements list.

UART_CLK_SEL : Selector for the UART clock multiplexor
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : UART_CLK_SEL_0

derive clock from pll3_80m

0x1 : UART_CLK_SEL_1

derive clock from osc_clk

End of enumeration elements list.

USDHC1_PODF : Divider for usdhc1 clock podf. Divider should be updated when output clock is gated.
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0 : USDHC1_PODF_0

divide by 1

0x1 : USDHC1_PODF_1

divide by 2

0x2 : USDHC1_PODF_2

divide by 3

0x3 : USDHC1_PODF_3

divide by 4

0x4 : USDHC1_PODF_4

divide by 5

0x5 : USDHC1_PODF_5

divide by 6

0x6 : USDHC1_PODF_6

divide by 7

0x7 : USDHC1_PODF_7

divide by 8

End of enumeration elements list.

USDHC2_PODF : Divider for usdhc2 clock. Divider should be updated when output clock is gated.
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : USDHC2_PODF_0

divide by 1

0x1 : USDHC2_PODF_1

divide by 2

0x2 : USDHC2_PODF_2

divide by 3

0x3 : USDHC2_PODF_3

divide by 4

0x4 : USDHC2_PODF_4

divide by 5

0x5 : USDHC2_PODF_5

divide by 6

0x6 : USDHC2_PODF_6

divide by 7

0x7 : USDHC2_PODF_7

divide by 8

End of enumeration elements list.

TRACE_PODF : Divider for trace clock. Divider should be updated when output clock is gated.
bits : 25 - 26 (2 bit)
access : read-write

Enumeration:

0 : TRACE_PODF_0

divide by 1

0x1 : TRACE_PODF_1

divide by 2

0x2 : TRACE_PODF_2

divide by 3

0x3 : TRACE_PODF_3

divide by 4

End of enumeration elements list.


CS1CDR

CCM Clock Divider Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS1CDR CS1CDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAI1_CLK_PODF SAI1_CLK_PRED FLEXIO2_CLK_PRED SAI3_CLK_PODF SAI3_CLK_PRED FLEXIO2_CLK_PODF

SAI1_CLK_PODF : Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

0x8 : DIVIDE_9

Divide by 9

0x9 : DIVIDE_10

Divide by 10

0xA : DIVIDE_11

Divide by 11

0xB : DIVIDE_12

Divide by 12

0xC : DIVIDE_13

Divide by 13

0xD : DIVIDE_14

Divide by 14

0xE : DIVIDE_15

Divide by 15

0xF : DIVIDE_16

Divide by 16

0x10 : DIVIDE_17

Divide by 17

0x11 : DIVIDE_18

Divide by 18

0x12 : DIVIDE_19

Divide by 19

0x13 : DIVIDE_20

Divide by 20

0x14 : DIVIDE_21

Divide by 21

0x15 : DIVIDE_22

Divide by 22

0x16 : DIVIDE_23

Divide by 23

0x17 : DIVIDE_24

Divide by 24

0x18 : DIVIDE_25

Divide by 25

0x19 : DIVIDE_26

Divide by 26

0x1A : DIVIDE_27

Divide by 27

0x1B : DIVIDE_28

Divide by 28

0x1C : DIVIDE_29

Divide by 29

0x1D : DIVIDE_30

Divide by 30

0x1E : DIVIDE_31

Divide by 31

0x1F : DIVIDE_32

Divide by 32

0x20 : DIVIDE_33

Divide by 33

0x21 : DIVIDE_34

Divide by 34

0x22 : DIVIDE_35

Divide by 35

0x23 : DIVIDE_36

Divide by 36

0x24 : DIVIDE_37

Divide by 37

0x25 : DIVIDE_38

Divide by 38

0x26 : DIVIDE_39

Divide by 39

0x27 : DIVIDE_40

Divide by 40

0x28 : DIVIDE_41

Divide by 41

0x29 : DIVIDE_42

Divide by 42

0x2A : DIVIDE_43

Divide by 43

0x2B : DIVIDE_44

Divide by 44

0x2C : DIVIDE_45

Divide by 45

0x2D : DIVIDE_46

Divide by 46

0x2E : DIVIDE_47

Divide by 47

0x2F : DIVIDE_48

Divide by 48

0x30 : DIVIDE_49

Divide by 49

0x31 : DIVIDE_50

Divide by 50

0x32 : DIVIDE_51

Divide by 51

0x33 : DIVIDE_52

Divide by 52

0x34 : DIVIDE_53

Divide by 53

0x35 : DIVIDE_54

Divide by 54

0x36 : DIVIDE_55

Divide by 55

0x37 : DIVIDE_56

Divide by 56

0x38 : DIVIDE_57

Divide by 57

0x39 : DIVIDE_58

Divide by 58

0x3A : DIVIDE_59

Divide by 59

0x3B : DIVIDE_60

Divide by 60

0x3C : DIVIDE_61

Divide by 61

0x3D : DIVIDE_62

Divide by 62

0x3E : DIVIDE_63

Divide by 63

0x3F : DIVIDE_64

Divide by 64

End of enumeration elements list.

SAI1_CLK_PRED : Divider for sai1 clock pred.
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0 : SAI1_CLK_PRED_0

divide by 1

0x1 : SAI1_CLK_PRED_1

divide by 2

0x2 : SAI1_CLK_PRED_2

divide by 3

0x3 : SAI1_CLK_PRED_3

divide by 4

0x4 : SAI1_CLK_PRED_4

divide by 5

0x5 : SAI1_CLK_PRED_5

divide by 6

0x6 : SAI1_CLK_PRED_6

divide by 7

0x7 : SAI1_CLK_PRED_7

divide by 8

End of enumeration elements list.

FLEXIO2_CLK_PRED : Divider for flexio2/flexio3 clock.
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0 : FLEXIO2_CLK_PRED_0

divide by 1

0x1 : FLEXIO2_CLK_PRED_1

divide by 2

0x2 : FLEXIO2_CLK_PRED_2

divide by 3

0x3 : FLEXIO2_CLK_PRED_3

divide by 4

0x4 : FLEXIO2_CLK_PRED_4

divide by 5

0x5 : FLEXIO2_CLK_PRED_5

divide by 6

0x6 : FLEXIO2_CLK_PRED_6

divide by 7

0x7 : FLEXIO2_CLK_PRED_7

divide by 8

End of enumeration elements list.

SAI3_CLK_PODF : Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

0x8 : DIVIDE_9

Divide by 9

0x9 : DIVIDE_10

Divide by 10

0xA : DIVIDE_11

Divide by 11

0xB : DIVIDE_12

Divide by 12

0xC : DIVIDE_13

Divide by 13

0xD : DIVIDE_14

Divide by 14

0xE : DIVIDE_15

Divide by 15

0xF : DIVIDE_16

Divide by 16

0x10 : DIVIDE_17

Divide by 17

0x11 : DIVIDE_18

Divide by 18

0x12 : DIVIDE_19

Divide by 19

0x13 : DIVIDE_20

Divide by 20

0x14 : DIVIDE_21

Divide by 21

0x15 : DIVIDE_22

Divide by 22

0x16 : DIVIDE_23

Divide by 23

0x17 : DIVIDE_24

Divide by 24

0x18 : DIVIDE_25

Divide by 25

0x19 : DIVIDE_26

Divide by 26

0x1A : DIVIDE_27

Divide by 27

0x1B : DIVIDE_28

Divide by 28

0x1C : DIVIDE_29

Divide by 29

0x1D : DIVIDE_30

Divide by 30

0x1E : DIVIDE_31

Divide by 31

0x1F : DIVIDE_32

Divide by 32

0x20 : DIVIDE_33

Divide by 33

0x21 : DIVIDE_34

Divide by 34

0x22 : DIVIDE_35

Divide by 35

0x23 : DIVIDE_36

Divide by 36

0x24 : DIVIDE_37

Divide by 37

0x25 : DIVIDE_38

Divide by 38

0x26 : DIVIDE_39

Divide by 39

0x27 : DIVIDE_40

Divide by 40

0x28 : DIVIDE_41

Divide by 41

0x29 : DIVIDE_42

Divide by 42

0x2A : DIVIDE_43

Divide by 43

0x2B : DIVIDE_44

Divide by 44

0x2C : DIVIDE_45

Divide by 45

0x2D : DIVIDE_46

Divide by 46

0x2E : DIVIDE_47

Divide by 47

0x2F : DIVIDE_48

Divide by 48

0x30 : DIVIDE_49

Divide by 49

0x31 : DIVIDE_50

Divide by 50

0x32 : DIVIDE_51

Divide by 51

0x33 : DIVIDE_52

Divide by 52

0x34 : DIVIDE_53

Divide by 53

0x35 : DIVIDE_54

Divide by 54

0x36 : DIVIDE_55

Divide by 55

0x37 : DIVIDE_56

Divide by 56

0x38 : DIVIDE_57

Divide by 57

0x39 : DIVIDE_58

Divide by 58

0x3A : DIVIDE_59

Divide by 59

0x3B : DIVIDE_60

Divide by 60

0x3C : DIVIDE_61

Divide by 61

0x3D : DIVIDE_62

Divide by 62

0x3E : DIVIDE_63

Divide by 63

0x3F : DIVIDE_64

Divide by 64

End of enumeration elements list.

SAI3_CLK_PRED : Divider for sai3/adc1/adc2 clock pred.
bits : 22 - 24 (3 bit)
access : read-write

Enumeration:

0 : SAI3_CLK_PRED_0

divide by 1

0x1 : SAI3_CLK_PRED_1

divide by 2

0x2 : SAI3_CLK_PRED_2

divide by 3

0x3 : SAI3_CLK_PRED_3

divide by 4

0x4 : SAI3_CLK_PRED_4

divide by 5

0x5 : SAI3_CLK_PRED_5

divide by 6

0x6 : SAI3_CLK_PRED_6

divide by 7

0x7 : SAI3_CLK_PRED_7

divide by 8

End of enumeration elements list.

FLEXIO2_CLK_PODF : Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated.
bits : 25 - 27 (3 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

End of enumeration elements list.


CS2CDR

CCM Clock Divider Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS2CDR CS2CDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAI2_CLK_PODF SAI2_CLK_PRED

SAI2_CLK_PODF : Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

0x8 : DIVIDE_9

Divide by 9

0x9 : DIVIDE_10

Divide by 10

0xA : DIVIDE_11

Divide by 11

0xB : DIVIDE_12

Divide by 12

0xC : DIVIDE_13

Divide by 13

0xD : DIVIDE_14

Divide by 14

0xE : DIVIDE_15

Divide by 15

0xF : DIVIDE_16

Divide by 16

0x10 : DIVIDE_17

Divide by 17

0x11 : DIVIDE_18

Divide by 18

0x12 : DIVIDE_19

Divide by 19

0x13 : DIVIDE_20

Divide by 20

0x14 : DIVIDE_21

Divide by 21

0x15 : DIVIDE_22

Divide by 22

0x16 : DIVIDE_23

Divide by 23

0x17 : DIVIDE_24

Divide by 24

0x18 : DIVIDE_25

Divide by 25

0x19 : DIVIDE_26

Divide by 26

0x1A : DIVIDE_27

Divide by 27

0x1B : DIVIDE_28

Divide by 28

0x1C : DIVIDE_29

Divide by 29

0x1D : DIVIDE_30

Divide by 30

0x1E : DIVIDE_31

Divide by 31

0x1F : DIVIDE_32

Divide by 32

0x20 : DIVIDE_33

Divide by 33

0x21 : DIVIDE_34

Divide by 34

0x22 : DIVIDE_35

Divide by 35

0x23 : DIVIDE_36

Divide by 36

0x24 : DIVIDE_37

Divide by 37

0x25 : DIVIDE_38

Divide by 38

0x26 : DIVIDE_39

Divide by 39

0x27 : DIVIDE_40

Divide by 40

0x28 : DIVIDE_41

Divide by 41

0x29 : DIVIDE_42

Divide by 42

0x2A : DIVIDE_43

Divide by 43

0x2B : DIVIDE_44

Divide by 44

0x2C : DIVIDE_45

Divide by 45

0x2D : DIVIDE_46

Divide by 46

0x2E : DIVIDE_47

Divide by 47

0x2F : DIVIDE_48

Divide by 48

0x30 : DIVIDE_49

Divide by 49

0x31 : DIVIDE_50

Divide by 50

0x32 : DIVIDE_51

Divide by 51

0x33 : DIVIDE_52

Divide by 52

0x34 : DIVIDE_53

Divide by 53

0x35 : DIVIDE_54

Divide by 54

0x36 : DIVIDE_55

Divide by 55

0x37 : DIVIDE_56

Divide by 56

0x38 : DIVIDE_57

Divide by 57

0x39 : DIVIDE_58

Divide by 58

0x3A : DIVIDE_59

Divide by 59

0x3B : DIVIDE_60

Divide by 60

0x3C : DIVIDE_61

Divide by 61

0x3D : DIVIDE_62

Divide by 62

0x3E : DIVIDE_63

Divide by 63

0x3F : DIVIDE_64

Divide by 64

End of enumeration elements list.

SAI2_CLK_PRED : Divider for sai2 clock pred.Divider should be updated when output clock is gated.
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0 : SAI2_CLK_PRED_0

divide by 1

0x1 : SAI2_CLK_PRED_1

divide by 2

0x2 : SAI2_CLK_PRED_2

divide by 3

0x3 : SAI2_CLK_PRED_3

divide by 4

0x4 : SAI2_CLK_PRED_4

divide by 5

0x5 : SAI2_CLK_PRED_5

divide by 6

0x6 : SAI2_CLK_PRED_6

divide by 7

0x7 : SAI2_CLK_PRED_7

divide by 8

End of enumeration elements list.


CDCDR

CCM D1 Clock Divider Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDCDR CDCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLEXIO1_CLK_SEL FLEXIO1_CLK_PODF FLEXIO1_CLK_PRED SPDIF0_CLK_SEL SPDIF0_CLK_PODF SPDIF0_CLK_PRED

FLEXIO1_CLK_SEL : Selector for flexio1 clock multiplexer
bits : 7 - 8 (2 bit)
access : read-write

Enumeration:

0 : FLEXIO1_CLK_SEL_0

derive clock from PLL4

0x1 : FLEXIO1_CLK_SEL_1

derive clock from PLL3 PFD2

0x2 : FLEXIO1_CLK_SEL_2

derive clock from PLL5

0x3 : FLEXIO1_CLK_SEL_3

derive clock from pll3_sw_clk

End of enumeration elements list.

FLEXIO1_CLK_PODF : Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

End of enumeration elements list.

FLEXIO1_CLK_PRED : Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

End of enumeration elements list.

SPDIF0_CLK_SEL : Selector for spdif0 clock multiplexer
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0 : SPDIF0_CLK_SEL_0

derive clock from PLL4

0x1 : SPDIF0_CLK_SEL_1

derive clock from PLL3 PFD2

0x2 : SPDIF0_CLK_SEL_2

derive clock from PLL5

0x3 : SPDIF0_CLK_SEL_3

derive clock from pll3_sw_clk

End of enumeration elements list.

SPDIF0_CLK_PODF : Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
bits : 22 - 24 (3 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

End of enumeration elements list.

SPDIF0_CLK_PRED : Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
bits : 25 - 27 (3 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

End of enumeration elements list.


CSCDR2

CCM Serial Clock Divider Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCDR2 CSCDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCDIF_PRED LCDIF_PRE_CLK_SEL LPI2C_CLK_SEL LPI2C_CLK_PODF

LCDIF_PRED : Pre-divider for lcdif clock. Divider should be updated when output clock is gated.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0 : LCDIF_PRED_0

divide by 1

0x1 : LCDIF_PRED_1

divide by 2

0x2 : LCDIF_PRED_2

divide by 3

0x3 : LCDIF_PRED_3

divide by 4

0x4 : LCDIF_PRED_4

divide by 5

0x5 : LCDIF_PRED_5

divide by 6

0x6 : LCDIF_PRED_6

divide by 7

0x7 : LCDIF_PRED_7

divide by 8

End of enumeration elements list.

LCDIF_PRE_CLK_SEL : Selector for lcdif root clock pre-multiplexer
bits : 15 - 17 (3 bit)
access : read-write

Enumeration:

0 : LCDIF_PRE_CLK_SEL_0

derive clock from PLL2

0x1 : LCDIF_PRE_CLK_SEL_1

derive clock from PLL3 PFD3

0x2 : LCDIF_PRE_CLK_SEL_2

derive clock from PLL5

0x3 : LCDIF_PRE_CLK_SEL_3

derive clock from PLL2 PFD0

0x4 : LCDIF_PRE_CLK_SEL_4

derive clock from PLL2 PFD1

0x5 : LCDIF_PRE_CLK_SEL_5

derive clock from PLL3 PFD1

End of enumeration elements list.

LPI2C_CLK_SEL : Selector for the LPI2C clock multiplexor
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : LPI2C_CLK_SEL_0

derive clock from pll3_60m

0x1 : LPI2C_CLK_SEL_1

derive clock from osc_clk

End of enumeration elements list.

LPI2C_CLK_PODF : Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
bits : 19 - 24 (6 bit)
access : read-write

Enumeration:

0 : DIVIDE_1

Divide by 1

0x1 : DIVIDE_2

Divide by 2

0x2 : DIVIDE_3

Divide by 3

0x3 : DIVIDE_4

Divide by 4

0x4 : DIVIDE_5

Divide by 5

0x5 : DIVIDE_6

Divide by 6

0x6 : DIVIDE_7

Divide by 7

0x7 : DIVIDE_8

Divide by 8

0x8 : DIVIDE_9

Divide by 9

0x9 : DIVIDE_10

Divide by 10

0xA : DIVIDE_11

Divide by 11

0xB : DIVIDE_12

Divide by 12

0xC : DIVIDE_13

Divide by 13

0xD : DIVIDE_14

Divide by 14

0xE : DIVIDE_15

Divide by 15

0xF : DIVIDE_16

Divide by 16

0x10 : DIVIDE_17

Divide by 17

0x11 : DIVIDE_18

Divide by 18

0x12 : DIVIDE_19

Divide by 19

0x13 : DIVIDE_20

Divide by 20

0x14 : DIVIDE_21

Divide by 21

0x15 : DIVIDE_22

Divide by 22

0x16 : DIVIDE_23

Divide by 23

0x17 : DIVIDE_24

Divide by 24

0x18 : DIVIDE_25

Divide by 25

0x19 : DIVIDE_26

Divide by 26

0x1A : DIVIDE_27

Divide by 27

0x1B : DIVIDE_28

Divide by 28

0x1C : DIVIDE_29

Divide by 29

0x1D : DIVIDE_30

Divide by 30

0x1E : DIVIDE_31

Divide by 31

0x1F : DIVIDE_32

Divide by 32

0x20 : DIVIDE_33

Divide by 33

0x21 : DIVIDE_34

Divide by 34

0x22 : DIVIDE_35

Divide by 35

0x23 : DIVIDE_36

Divide by 36

0x24 : DIVIDE_37

Divide by 37

0x25 : DIVIDE_38

Divide by 38

0x26 : DIVIDE_39

Divide by 39

0x27 : DIVIDE_40

Divide by 40

0x28 : DIVIDE_41

Divide by 41

0x29 : DIVIDE_42

Divide by 42

0x2A : DIVIDE_43

Divide by 43

0x2B : DIVIDE_44

Divide by 44

0x2C : DIVIDE_45

Divide by 45

0x2D : DIVIDE_46

Divide by 46

0x2E : DIVIDE_47

Divide by 47

0x2F : DIVIDE_48

Divide by 48

0x30 : DIVIDE_49

Divide by 49

0x31 : DIVIDE_50

Divide by 50

0x32 : DIVIDE_51

Divide by 51

0x33 : DIVIDE_52

Divide by 52

0x34 : DIVIDE_53

Divide by 53

0x35 : DIVIDE_54

Divide by 54

0x36 : DIVIDE_55

Divide by 55

0x37 : DIVIDE_56

Divide by 56

0x38 : DIVIDE_57

Divide by 57

0x39 : DIVIDE_58

Divide by 58

0x3A : DIVIDE_59

Divide by 59

0x3B : DIVIDE_60

Divide by 60

0x3C : DIVIDE_61

Divide by 61

0x3D : DIVIDE_62

Divide by 62

0x3E : DIVIDE_63

Divide by 63

0x3F : DIVIDE_64

Divide by 64

End of enumeration elements list.


CSCDR3

CCM Serial Clock Divider Register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCDR3 CSCDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSI_CLK_SEL CSI_PODF

CSI_CLK_SEL : Selector for csi_mclk multiplexer
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : CSI_CLK_SEL_0

derive clock from osc_clk (24M)

0x1 : CSI_CLK_SEL_1

derive clock from PLL2 PFD2

0x2 : CSI_CLK_SEL_2

derive clock from pll3_120M

0x3 : CSI_CLK_SEL_3

derive clock from PLL3 PFD1

End of enumeration elements list.

CSI_PODF : Post divider for csi_mclk. Divider should be updated when output clock is gated.
bits : 11 - 13 (3 bit)
access : read-write

Enumeration:

0 : CSI_PODF_0

divide by 1

0x1 : CSI_PODF_1

divide by 2

0x2 : CSI_PODF_2

divide by 3

0x3 : CSI_PODF_3

divide by 4

0x4 : CSI_PODF_4

divide by 5

0x5 : CSI_PODF_5

divide by 6

0x6 : CSI_PODF_6

divide by 7

0x7 : CSI_PODF_7

divide by 8

End of enumeration elements list.


CDHIPR

CCM Divider Handshake In-Process Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDHIPR CDHIPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEMC_PODF_BUSY AHB_PODF_BUSY PERIPH2_CLK_SEL_BUSY PERIPH_CLK_SEL_BUSY ARM_PODF_BUSY

SEMC_PODF_BUSY : Busy indicator for semc_podf.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : SEMC_PODF_BUSY_0

divider is not busy and its value represents the actual division.

0x1 : SEMC_PODF_BUSY_1

divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied.

End of enumeration elements list.

AHB_PODF_BUSY : Busy indicator for ahb_podf.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : AHB_PODF_BUSY_0

divider is not busy and its value represents the actual division.

0x1 : AHB_PODF_BUSY_1

divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied.

End of enumeration elements list.

PERIPH2_CLK_SEL_BUSY : Busy indicator for periph2_clk_sel mux control.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : PERIPH2_CLK_SEL_BUSY_0

mux is not busy and its value represents the actual division.

0x1 : PERIPH2_CLK_SEL_BUSY_1

mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied.

End of enumeration elements list.

PERIPH_CLK_SEL_BUSY : Busy indicator for periph_clk_sel mux control.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

0 : PERIPH_CLK_SEL_BUSY_0

mux is not busy and its value represents the actual division.

0x1 : PERIPH_CLK_SEL_BUSY_1

mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied.

End of enumeration elements list.

ARM_PODF_BUSY : Busy indicator for arm_podf.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

0 : ARM_PODF_BUSY_0

divider is not busy and its value represents the actual division.

0x1 : ARM_PODF_BUSY_1

divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied.

End of enumeration elements list.


CLPCR

CCM Low Power Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLPCR CLPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM ARM_CLK_DIS_ON_LPM SBYOS DIS_REF_OSC VSTBY STBY_COUNT COSC_PWRDOWN BYPASS_LPM_HS1 BYPASS_LPM_HS0 MASK_CORE0_WFI MASK_SCU_IDLE MASK_L2CC_IDLE

LPM : Setting the low power mode that system will enter on next assertion of dsm_request signal.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : LPM_0

Remain in run mode

0x1 : LPM_1

Transfer to wait mode

0x2 : LPM_2

Transfer to stop mode

End of enumeration elements list.

ARM_CLK_DIS_ON_LPM : Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ARM_CLK_DIS_ON_LPM_0

ARM clock enabled on wait mode.

0x1 : ARM_CLK_DIS_ON_LPM_1

ARM clock disabled on wait mode. .

End of enumeration elements list.

SBYOS : Standby clock oscillator bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SBYOS_0

On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0')

0x1 : SBYOS_1

On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process.

End of enumeration elements list.

DIS_REF_OSC : dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DIS_REF_OSC_0

external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.

0x1 : DIS_REF_OSC_1

external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'

End of enumeration elements list.

VSTBY : Voltage standby request bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : VSTBY_0

Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')

0x1 : VSTBY_1

Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').

End of enumeration elements list.

STBY_COUNT : Standby counter definition
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : STBY_COUNT_0

CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles

0x1 : STBY_COUNT_1

CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles

0x2 : STBY_COUNT_2

CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles

0x3 : STBY_COUNT_3

CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles

End of enumeration elements list.

COSC_PWRDOWN : In run mode, software can manually control powering down of on chip oscillator, i
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : COSC_PWRDOWN_0

On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.

0x1 : COSC_PWRDOWN_1

On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.

End of enumeration elements list.

BYPASS_LPM_HS1 : Bypass low power mode handshake. This bit should always be set to 1'b1 by software.
bits : 19 - 19 (1 bit)
access : read-write

BYPASS_LPM_HS0 : Bypass low power mode handshake. This bit should always be set to 1'b1 by software.
bits : 21 - 21 (1 bit)
access : read-write

MASK_CORE0_WFI : Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : MASK_CORE0_WFI_0

WFI of core0 is not masked

0x1 : MASK_CORE0_WFI_1

WFI of core0 is masked

End of enumeration elements list.

MASK_SCU_IDLE : Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : MASK_SCU_IDLE_0

SCU IDLE is not masked

0x1 : MASK_SCU_IDLE_1

SCU IDLE is masked

End of enumeration elements list.

MASK_L2CC_IDLE : Mask L2CC IDLE for entering low power mode
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : MASK_L2CC_IDLE_0

L2CC IDLE is not masked

0x1 : MASK_L2CC_IDLE_1

L2CC IDLE is masked

End of enumeration elements list.


CISR

CCM Interrupt Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CISR CISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LRF_PLL COSC_READY SEMC_PODF_LOADED PERIPH2_CLK_SEL_LOADED AHB_PODF_LOADED PERIPH_CLK_SEL_LOADED ARM_PODF_LOADED

LRF_PLL : CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : LRF_PLL_0

interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs

0x1 : LRF_PLL_1

interrupt generated due to lock ready of all enabled and not bypaseed PLLs

End of enumeration elements list.

COSC_READY : CCM interrupt request 2 generated due to on board oscillator ready, i
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : COSC_READY_0

interrupt is not generated due to on board oscillator ready

0x1 : COSC_READY_1

interrupt generated due to on board oscillator ready

End of enumeration elements list.

SEMC_PODF_LOADED : CCM interrupt request 1 generated due to frequency change of semc_podf
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SEMC_PODF_LOADED_0

interrupt is not generated due to frequency change of semc_podf

0x1 : SEMC_PODF_LOADED_1

interrupt generated due to frequency change of semc_podf

End of enumeration elements list.

PERIPH2_CLK_SEL_LOADED : CCM interrupt request 1 generated due to frequency change of periph2_clk_sel
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : PERIPH2_CLK_SEL_LOADED_0

interrupt is not generated due to frequency change of periph2_clk_sel

0x1 : PERIPH2_CLK_SEL_LOADED_1

interrupt generated due to frequency change of periph2_clk_sel

End of enumeration elements list.

AHB_PODF_LOADED : CCM interrupt request 1 generated due to frequency change of ahb_podf
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : AHB_PODF_LOADED_0

interrupt is not generated due to frequency change of ahb_podf

0x1 : AHB_PODF_LOADED_1

interrupt generated due to frequency change of ahb_podf

End of enumeration elements list.

PERIPH_CLK_SEL_LOADED : CCM interrupt request 1 generated due to update of periph_clk_sel.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : PERIPH_CLK_SEL_LOADED_0

interrupt is not generated due to update of periph_clk_sel.

0x1 : PERIPH_CLK_SEL_LOADED_1

interrupt generated due to update of periph_clk_sel.

End of enumeration elements list.

ARM_PODF_LOADED : CCM interrupt request 1 generated due to frequency change of arm_podf
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : ARM_PODF_LOADED_0

interrupt is not generated due to frequency change of arm_podf

0x1 : ARM_PODF_LOADED_1

interrupt generated due to frequency change of arm_podf

End of enumeration elements list.


CIMR

CCM Interrupt Mask Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIMR CIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK_LRF_PLL MASK_COSC_READY MASK_SEMC_PODF_LOADED MASK_PERIPH2_CLK_SEL_LOADED MASK_AHB_PODF_LOADED MASK_PERIPH_CLK_SEL_LOADED ARM_PODF_LOADED

MASK_LRF_PLL : mask interrupt generation due to lrf of PLLs
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MASK_LRF_PLL_0

don't mask interrupt due to lrf of PLLs - interrupt will be created

0x1 : MASK_LRF_PLL_1

mask interrupt due to lrf of PLLs

End of enumeration elements list.

MASK_COSC_READY : mask interrupt generation due to on board oscillator ready
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : MASK_COSC_READY_0

don't mask interrupt due to on board oscillator ready - interrupt will be created

0x1 : MASK_COSC_READY_1

mask interrupt due to on board oscillator ready

End of enumeration elements list.

MASK_SEMC_PODF_LOADED : mask interrupt generation due to frequency change of semc_podf
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : MASK_SEMC_PODF_LOADED_0

don't mask interrupt due to frequency change of semc_podf - interrupt will be created

0x1 : MASK_SEMC_PODF_LOADED_1

mask interrupt due to frequency change of semc_podf

End of enumeration elements list.

MASK_PERIPH2_CLK_SEL_LOADED : mask interrupt generation due to update of periph2_clk_sel.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : MASK_PERIPH2_CLK_SEL_LOADED_0

don't mask interrupt due to update of periph2_clk_sel - interrupt will be created

0x1 : MASK_PERIPH2_CLK_SEL_LOADED_1

mask interrupt due to update of periph2_clk_sel

End of enumeration elements list.

MASK_AHB_PODF_LOADED : mask interrupt generation due to frequency change of ahb_podf
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MASK_AHB_PODF_LOADED_0

don't mask interrupt due to frequency change of ahb_podf - interrupt will be created

0x1 : MASK_AHB_PODF_LOADED_1

mask interrupt due to frequency change of ahb_podf

End of enumeration elements list.

MASK_PERIPH_CLK_SEL_LOADED : mask interrupt generation due to update of periph_clk_sel.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : MASK_PERIPH_CLK_SEL_LOADED_0

don't mask interrupt due to update of periph_clk_sel - interrupt will be created

0x1 : MASK_PERIPH_CLK_SEL_LOADED_1

mask interrupt due to update of periph_clk_sel

End of enumeration elements list.

ARM_PODF_LOADED : mask interrupt generation due to frequency change of arm_podf
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : ARM_PODF_LOADED_0

don't mask interrupt due to frequency change of arm_podf - interrupt will be created

0x1 : ARM_PODF_LOADED_1

mask interrupt due to frequency change of arm_podf

End of enumeration elements list.


CCOSR

CCM Clock Output Source Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCOSR CCOSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKO1_SEL CLKO1_DIV CLKO1_EN CLK_OUT_SEL CLKO2_SEL CLKO2_DIV CLKO2_EN

CLKO1_SEL : Selection of the clock to be generated on CCM_CLKO1
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : CLKO1_SEL_0

USB1 PLL clock (divided by 2)

0x1 : CLKO1_SEL_1

SYS PLL clock (divided by 2)

0x3 : CLKO1_SEL_3

VIDEO PLL clock (divided by 2)

0x5 : CLKO1_SEL_5

semc_clk_root

0xA : CLKO1_SEL_10

lcdif_pix_clk_root

0xB : CLKO1_SEL_11

ahb_clk_root

0xC : CLKO1_SEL_12

ipg_clk_root

0xD : CLKO1_SEL_13

perclk_root

0xE : CLKO1_SEL_14

ckil_sync_clk_root

0xF : CLKO1_SEL_15

pll4_main_clk

End of enumeration elements list.

CLKO1_DIV : Setting the divider of CCM_CLKO1
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0 : CLKO1_DIV_0

divide by 1

0x1 : CLKO1_DIV_1

divide by 2

0x2 : CLKO1_DIV_2

divide by 3

0x3 : CLKO1_DIV_3

divide by 4

0x4 : CLKO1_DIV_4

divide by 5

0x5 : CLKO1_DIV_5

divide by 6

0x6 : CLKO1_DIV_6

divide by 7

0x7 : CLKO1_DIV_7

divide by 8

End of enumeration elements list.

CLKO1_EN : Enable of CCM_CLKO1 clock
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : CLKO1_EN_0

CCM_CLKO1 disabled.

0x1 : CLKO1_EN_1

CCM_CLKO1 enabled.

End of enumeration elements list.

CLK_OUT_SEL : CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CLK_OUT_SEL_0

CCM_CLKO1 output drives CCM_CLKO1 clock

0x1 : CLK_OUT_SEL_1

CCM_CLKO1 output drives CCM_CLKO2 clock

End of enumeration elements list.

CLKO2_SEL : Selection of the clock to be generated on CCM_CLKO2
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0x3 : CLKO2_SEL_3

usdhc1_clk_root

0x6 : CLKO2_SEL_6

lpi2c_clk_root

0xB : CLKO2_SEL_11

csi_clk_root

0xE : CLKO2_SEL_14

osc_clk

0x11 : CLKO2_SEL_17

usdhc2_clk_root

0x12 : CLKO2_SEL_18

sai1_clk_root

0x13 : CLKO2_SEL_19

sai2_clk_root

0x14 : CLKO2_SEL_20

sai3_clk_root (shared with ADC1 and ADC2 alt_clk root)

0x17 : CLKO2_SEL_23

can_clk_root (FlexCAN, shared with CANFD)

0x1B : CLKO2_SEL_27

flexspi_clk_root

0x1C : CLKO2_SEL_28

uart_clk_root

0x1D : CLKO2_SEL_29

spdif0_clk_root

End of enumeration elements list.

CLKO2_DIV : Setting the divider of CCM_CLKO2
bits : 21 - 23 (3 bit)
access : read-write

Enumeration:

0 : CLKO2_DIV_0

divide by 1

0x1 : CLKO2_DIV_1

divide by 2

0x2 : CLKO2_DIV_2

divide by 3

0x3 : CLKO2_DIV_3

divide by 4

0x4 : CLKO2_DIV_4

divide by 5

0x5 : CLKO2_DIV_5

divide by 6

0x6 : CLKO2_DIV_6

divide by 7

0x7 : CLKO2_DIV_7

divide by 8

End of enumeration elements list.

CLKO2_EN : Enable of CCM_CLKO2 clock
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : CLKO2_EN_0

CCM_CLKO2 disabled.

0x1 : CLKO2_EN_1

CCM_CLKO2 enabled.

End of enumeration elements list.


CGPR

CCM General Purpose Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGPR CGPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMIC_DELAY_SCALER EFUSE_PROG_SUPPLY_GATE SYS_MEM_DS_CTRL FPL INT_MEM_CLK_LPM

PMIC_DELAY_SCALER : Defines clock dividion of clock for stby_count (pmic delay counter)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PMIC_DELAY_SCALER_0

clock is not divided

0x1 : PMIC_DELAY_SCALER_1

clock is divided /8

End of enumeration elements list.

EFUSE_PROG_SUPPLY_GATE : Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : EFUSE_PROG_SUPPLY_GATE_0

fuse programing supply voltage is gated off to the efuse module

0x1 : EFUSE_PROG_SUPPLY_GATE_1

allow fuse programing.

End of enumeration elements list.

SYS_MEM_DS_CTRL : System memory DS control
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : SYS_MEM_DS_CTRL_0

Disable memory DS mode always

0x1 : SYS_MEM_DS_CTRL_1

Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled

#1x : SYS_MEM_DS_CTRL_2

enable memory (outside ARM platform) DS mode when system is in STOP mode

End of enumeration elements list.

FPL : Fast PLL enable.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : FPL_0

Engage PLL enable default way.

0x1 : FPL_1

Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.

End of enumeration elements list.

INT_MEM_CLK_LPM : Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : INT_MEM_CLK_LPM_0

Disable the clock to the ARM platform memories when entering Low Power Mode

0x1 : INT_MEM_CLK_LPM_1

Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)

End of enumeration elements list.


CCGR0

CCM Clock Gating Register 0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCGR0 CCGR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CG0 CG1 CG2 CG3 CG4 CG5 CG6 CG7 CG8 CG9 CG10 CG11 CG12 CG13 CG14 CG15

CG0 : aips_tz1 clocks (aips_tz1_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write

CG1 : aips_tz2 clocks (aips_tz2_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write

CG2 : mqs clock ( mqs_hmclk_clock_enable)
bits : 4 - 5 (2 bit)
access : read-write

CG3 : flexspi_exsc clock (flexspi_exsc_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write

CG4 : sim_m or sim_main register access clock (sim_m_mainclk_r_enable)
bits : 8 - 9 (2 bit)
access : read-write

CG5 : dcp clock (dcp_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write

CG6 : lpuart3 clock (lpuart3_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write

CG7 : can1 clock (can1_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write

CG8 : can1_serial clock (can1_serial_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write

CG9 : can2 clock (can2_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write

CG10 : can2_serial clock (can2_serial_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write

CG11 : trace clock (trace_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write

CG12 : gpt2 bus clocks (gpt2_bus_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write

CG13 : gpt2 serial clocks (gpt2_serial_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write

CG14 : lpuart2 clock (lpuart2_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write

CG15 : gpio2_clocks (gpio2_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write


CCGR1

CCM Clock Gating Register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCGR1 CCGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CG0 CG1 CG2 CG3 CG4 CG5 CG6 CG7 CG8 CG9 CG10 CG11 CG12 CG13 CG14 CG15

CG0 : lpspi1 clocks (lpspi1_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write

CG1 : lpspi2 clocks (lpspi2_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write

CG2 : lpspi3 clocks (lpspi3_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write

CG3 : lpspi4 clocks (lpspi4_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write

CG4 : adc2 clock (adc2_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write

CG5 : enet clock (enet_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write

CG6 : pit clocks (pit_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write

CG7 : aoi2 clocks (aoi2_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write

CG8 : adc1 clock (adc1_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write

CG9 : semc_exsc clock (semc_exsc_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write

CG10 : gpt1 bus clock (gpt_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write

CG11 : gpt1 serial clock (gpt_serial_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write

CG12 : lpuart4 clock (lpuart4_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write

CG13 : gpio1 clock (gpio1_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write

CG14 : csu clock (csu_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write

CG15 : Reserved
bits : 30 - 31 (2 bit)
access : read-write


CCGR2

CCM Clock Gating Register 2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCGR2 CCGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CG0 CG1 CG2 CG3 CG4 CG5 CG6 CG7 CG8 CG9 CG10 CG11 CG12 CG13 CG14 CG15

CG0 : ocram_exsc clock (ocram_exsc_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write

CG1 : csi clock (csi_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write

CG2 : iomuxc_snvs clock (iomuxc_snvs_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write

CG3 : lpi2c1 clock (lpi2c1_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write

CG4 : lpi2c2 clock (lpi2c2_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write

CG5 : lpi2c3 clock (lpi2c3_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write

CG6 : OCOTP_CTRL clock (iim_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write

CG7 : xbar3 clock (xbar3_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write

CG8 : ipmux1 clock (ipmux1_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write

CG9 : ipmux2 clock (ipmux2_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write

CG10 : ipmux3 clock (ipmux3_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write

CG11 : xbar1 clock (xbar1_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write

CG12 : xbar2 clock (xbar2_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write

CG13 : gpio3 clock (gpio3_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write

CG14 : lcd clocks (lcd_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write

CG15 : pxp clocks (pxp_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write


CCGR3

CCM Clock Gating Register 3
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCGR3 CCGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CG0 CG1 CG2 CG3 CG4 CG5 CG6 CG7 CG8 CG9 CG10 CG11 CG12 CG13 CG14 CG15

CG0 : flexio2 clocks (flexio2_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write

CG1 : lpuart5 clock (lpuart5_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write

CG2 : semc clocks (semc_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write

CG3 : lpuart6 clock (lpuart6_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write

CG4 : aoi1 clock (aoi1_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write

CG5 : lcdif pix clock (lcdif_pix_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write

CG6 : gpio4 clock (gpio4_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write

CG7 : ewm clocks (ewm_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write

CG8 : wdog1 clock (wdog1_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write

CG9 : flexram clock (flexram_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write

CG10 : acmp1 clocks (acmp1_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write

CG11 : acmp2 clocks (acmp2_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write

CG12 : acmp3 clocks (acmp3_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write

CG13 : acmp4 clocks (acmp4_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write

CG14 : The OCRAM clock cannot be turned off when the CM cache is running on this device.
bits : 28 - 29 (2 bit)
access : read-write

CG15 : iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write


CCGR4

CCM Clock Gating Register 4
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCGR4 CCGR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CG0 CG1 CG2 CG3 CG4 CG5 CG6 CG7 CG8 CG9 CG10 CG11 CG12 CG13 CG14 CG15

CG0 : sim_m7 register access clock (sim_m7_mainclk_r_enable)
bits : 0 - 1 (2 bit)
access : read-write

CG1 : iomuxc clock (iomuxc_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write

CG2 : iomuxc gpr clock (iomuxc_gpr_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write

CG3 : bee clock(bee_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write

CG4 : sim_m7 clock (sim_m7_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write

CG5 : tsc_dig clock (tsc_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write

CG6 : sim_m clocks (sim_m_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write

CG7 : sim_ems clocks (sim_ems_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write

CG8 : pwm1 clocks (pwm1_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write

CG9 : pwm2 clocks (pwm2_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write

CG10 : pwm3 clocks (pwm3_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write

CG11 : pwm4 clocks (pwm4_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write

CG12 : enc1 clocks (enc1_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write

CG13 : enc2 clocks (enc2_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write

CG14 : enc3 clocks (enc3_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write

CG15 : enc4 clocks (enc4_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write


CCGR5

CCM Clock Gating Register 5
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCGR5 CCGR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CG0 CG1 CG2 CG3 CG4 CG5 CG6 CG7 CG8 CG9 CG10 CG11 CG12 CG13 CG14 CG15

CG0 : rom clock (rom_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write

CG1 : flexio1 clock (flexio1_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write

CG2 : wdog3 clock (wdog3_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write

CG3 : dma clock (dma_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write

CG4 : kpp clock (kpp_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write

CG5 : wdog2 clock (wdog2_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write

CG6 : aipstz4 clocks (aips_tz4_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write

CG7 : spdif clock (spdif_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write

CG8 : sim_main clock (sim_main_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write

CG9 : sai1 clock (sai1_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write

CG10 : sai2 clock (sai2_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write

CG11 : sai3 clock (sai3_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write

CG12 : lpuart1 clock (lpuart1_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write

CG13 : lpuart7 clock (lpuart7_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write

CG14 : snvs_hp clock (snvs_hp_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write

CG15 : snvs_lp clock (snvs_lp_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write


CSR

CCM Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REF_EN_B CAMP2_READY COSC_READY

REF_EN_B : Status of the value of CCM_REF_EN_B output of ccm
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : REF_EN_B_0

value of CCM_REF_EN_B is '0'

0x1 : REF_EN_B_1

value of CCM_REF_EN_B is '1'

End of enumeration elements list.

CAMP2_READY : Status indication of CAMP2.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : CAMP2_READY_0

CAMP2 is not ready.

0x1 : CAMP2_READY_1

CAMP2 is ready.

End of enumeration elements list.

COSC_READY : Status indication of on board oscillator
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

0 : COSC_READY_0

on board oscillator is not ready.

0x1 : COSC_READY_1

on board oscillator is ready.

End of enumeration elements list.


CCGR6

CCM Clock Gating Register 6
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCGR6 CCGR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CG0 CG1 CG2 CG3 CG4 CG5 CG6 CG7 CG8 CG9 CG10 CG11 CG12 CG13 CG14 CG15

CG0 : usboh3 clock (usboh3_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write

CG1 : usdhc1 clocks (usdhc1_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write

CG2 : usdhc2 clocks (usdhc2_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write

CG3 : dcdc clocks (dcdc_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write

CG4 : ipmux4 clock (ipmux4_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write

CG5 : flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared
bits : 10 - 11 (2 bit)
access : read-write

CG6 : trng clock (trng_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write

CG7 : lpuart8 clocks (lpuart8_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write

CG8 : timer4 clocks (timer4_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write

CG9 : aips_tz3 clock (aips_tz3_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write

CG10 : sim_axbs_p_clk_enable
bits : 20 - 21 (2 bit)
access : read-write

CG11 : anadig clocks (anadig_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write

CG12 : lpi2c4 serial clock (lpi2c4_serial_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write

CG13 : timer1 clocks (timer1_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write

CG14 : timer2 clocks (timer2_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write

CG15 : timer3 clocks (timer3_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write


CCGR7

CCM Clock Gating Register 7
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCGR7 CCGR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CG0 CG1 CG2 CG3 CG4 CG5 CG6

CG0 : enet2_clk_enable
bits : 0 - 1 (2 bit)
access : read-write

CG1 : flexspi2_clk_enable
bits : 2 - 3 (2 bit)
access : read-write

CG2 : axbs_l_clk_enable
bits : 4 - 5 (2 bit)
access : read-write

CG3 : can3_clk_enable
bits : 6 - 7 (2 bit)
access : read-write

CG4 : can3_serial_clk_enable
bits : 8 - 9 (2 bit)
access : read-write

CG5 : aips_lite_clk_enable
bits : 10 - 11 (2 bit)
access : read-write

CG6 : flexio3_clk_enable
bits : 12 - 13 (2 bit)
access : read-write


CMEOR

CCM Module Enable Overide Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMEOR CMEOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD_EN_OV_GPT MOD_EN_OV_PIT MOD_EN_USDHC MOD_EN_OV_TRNG MOD_EN_OV_CANFD_CPI MOD_EN_OV_CAN2_CPI MOD_EN_OV_CAN1_CPI

MOD_EN_OV_GPT : Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk'
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : MOD_EN_OV_GPT_0

don't override module enable signal

0x1 : MOD_EN_OV_GPT_1

override module enable signal

End of enumeration elements list.

MOD_EN_OV_PIT : Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk'
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : MOD_EN_OV_PIT_0

don't override module enable signal

0x1 : MOD_EN_OV_PIT_1

override module enable signal

End of enumeration elements list.

MOD_EN_USDHC : overide clock enable signal from USDHC.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : MOD_EN_USDHC_0

don't override module enable signal

0x1 : MOD_EN_USDHC_1

override module enable signal

End of enumeration elements list.

MOD_EN_OV_TRNG : Overide clock enable signal from TRNG
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : MOD_EN_OV_TRNG_0

don't override module enable signal

0x1 : MOD_EN_OV_TRNG_1

override module enable signal

End of enumeration elements list.

MOD_EN_OV_CANFD_CPI : Overide clock enable signal from FlexCAN3(CANFD) - clock will not be gated based on CAN's signal 'enable_clk_cpi'
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : MOD_EN_OV_CANFD_CPI_0

don't override module enable signal

0x1 : MOD_EN_OV_CANFD_CPI_1

override module enable signal

End of enumeration elements list.

MOD_EN_OV_CAN2_CPI : Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi'
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : MOD_EN_OV_CAN2_CPI_0

don't override module enable signal

0x1 : MOD_EN_OV_CAN2_CPI_1

override module enable signal

End of enumeration elements list.

MOD_EN_OV_CAN1_CPI : Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi'
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : MOD_EN_OV_CAN1_CPI_0

don't overide module enable signal

0x1 : MOD_EN_OV_CAN1_CPI_1

overide module enable signal

End of enumeration elements list.


CCSR

CCM Clock Switcher Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCSR CCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL3_SW_CLK_SEL

PLL3_SW_CLK_SEL : Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PLL3_SW_CLK_SEL_0

pll3_main_clk

0x1 : PLL3_SW_CLK_SEL_1

pll3 bypass clock

End of enumeration elements list.



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