\n
address_offset : 0x0 Bytes (0x0)
size : 0x168 byte (0x0)
mem_usage : registers
protection : not protected
ADC_ETC Global Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIG_ENABLE : TRIG enable register
bits : 0 - 7 (8 bit)
access : read-write
EXT0_TRIG_ENABLE : TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger.
bits : 8 - 8 (1 bit)
access : read-write
EXT0_TRIG_PRIORITY : External TSC0 trigger priority, 7 is Highest, 0 is lowest .
bits : 9 - 11 (3 bit)
access : read-write
EXT1_TRIG_ENABLE : TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger.
bits : 12 - 12 (1 bit)
access : read-write
EXT1_TRIG_PRIORITY : External TSC1 trigger priority, 7 is Highest, 0 is lowest .
bits : 13 - 15 (3 bit)
access : read-write
PRE_DIVIDER : Pre-divider for trig delay and interval .
bits : 16 - 23 (8 bit)
access : read-write
DMA_MODE_SEL : 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared
bits : 29 - 29 (1 bit)
access : read-write
TSC_BYPASS : 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared.
bits : 30 - 30 (1 bit)
access : read-write
SOFTRST : Software reset, high active. When write 1 ,all logical will be reset.
bits : 31 - 31 (1 bit)
access : read-write
ETC_TRIG0 Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRIG : Software write 1 as the TRIGGER. This register is self-clearing.
bits : 0 - 0 (1 bit)
access : read-write
TRIG_MODE : TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
bits : 4 - 4 (1 bit)
access : read-write
TRIG_CHAIN : TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
bits : 8 - 10 (3 bit)
access : read-write
TRIG_PRIORITY : External trigger priority, 7 is highest, 0 is lowest .
bits : 12 - 14 (3 bit)
access : read-write
SYNC_MODE : TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
bits : 16 - 16 (1 bit)
access : read-write
ETC_TRIG6 Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRIG : Software write 1 as the TRIGGER. This register is self-clearing.
bits : 0 - 0 (1 bit)
access : read-write
TRIG_MODE : TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
bits : 4 - 4 (1 bit)
access : read-write
TRIG_CHAIN : TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
bits : 8 - 10 (3 bit)
access : read-write
TRIG_PRIORITY : External trigger priority, 7 is highest, 0 is lowest .
bits : 12 - 14 (3 bit)
access : read-write
SYNC_MODE : TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
bits : 16 - 16 (1 bit)
access : read-write
ETC_TRIG6 Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_DELAY : TRIGGER initial delay counter
bits : 0 - 15 (16 bit)
access : read-write
SAMPLE_INTERVAL : TRIGGER sampling interval counter
bits : 16 - 31 (16 bit)
access : read-write
ETC_TRIG Chain 0/1 Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : CHAIN0 CSEL ADC channel selection
bits : 0 - 3 (4 bit)
access : read-write
HWTS0 : CHAIN0 HWTS ADC hardware trigger selection
bits : 4 - 11 (8 bit)
access : read-write
B2B0 : CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 12 - 12 (1 bit)
access : read-write
IE0 : CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 13 - 14 (2 bit)
access : read-write
CSEL1 : CHAIN1 CSEL ADC channel selection
bits : 16 - 19 (4 bit)
access : read-write
HWTS1 : CHAIN1 HWTS ADC hardware trigger selection
bits : 20 - 27 (8 bit)
access : read-write
B2B1 : CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 28 - 28 (1 bit)
access : read-write
IE1 : CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 2/3 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL2 : CHAIN2 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS2 : CHAIN2 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B2 : CHAIN2 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE2 : CHAIN2 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL3 : CHAIN3 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS3 : CHAIN3 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B3 : CHAIN3 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE3 : CHAIN3 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 4/5 Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL4 : CHAIN4 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS4 : CHAIN4 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B4 : CHAIN4 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE4 : CHAIN4 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL5 : CHAIN5 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS5 : CHAIN5 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B5 : CHAIN5 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE5 : CHAIN5 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 6/7 Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL6 : CHAIN6 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS6 : CHAIN6 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B6 : CHAIN6 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE6 : CHAIN6 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL7 : CHAIN7 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS7 : CHAIN7 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B7 : CHAIN7 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE7 : CHAIN7 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Result Data 1/0 Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Result DATA0
bits : 0 - 11 (12 bit)
access : read-only
DATA1 : Result DATA1
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 3/2 Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Result DATA2
bits : 0 - 11 (12 bit)
access : read-only
DATA3 : Result DATA3
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 5/4 Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Result DATA4
bits : 0 - 11 (12 bit)
access : read-only
DATA5 : Result DATA5
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 7/6 Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Result DATA6
bits : 0 - 11 (12 bit)
access : read-only
DATA7 : Result DATA7
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG7 Control Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRIG : Software write 1 as the TRIGGER. This register is self-clearing.
bits : 0 - 0 (1 bit)
access : read-write
TRIG_MODE : TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
bits : 4 - 4 (1 bit)
access : read-write
TRIG_CHAIN : TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
bits : 8 - 10 (3 bit)
access : read-write
TRIG_PRIORITY : External trigger priority, 7 is highest, 0 is lowest .
bits : 12 - 14 (3 bit)
access : read-write
SYNC_MODE : TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
bits : 16 - 16 (1 bit)
access : read-write
ETC_TRIG7 Counter Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_DELAY : TRIGGER initial delay counter
bits : 0 - 15 (16 bit)
access : read-write
SAMPLE_INTERVAL : TRIGGER sampling interval counter
bits : 16 - 31 (16 bit)
access : read-write
ETC_TRIG Chain 0/1 Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : CHAIN0 CSEL ADC channel selection
bits : 0 - 3 (4 bit)
access : read-write
HWTS0 : CHAIN0 HWTS ADC hardware trigger selection
bits : 4 - 11 (8 bit)
access : read-write
B2B0 : CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 12 - 12 (1 bit)
access : read-write
IE0 : CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 13 - 14 (2 bit)
access : read-write
CSEL1 : CHAIN1 CSEL ADC channel selection
bits : 16 - 19 (4 bit)
access : read-write
HWTS1 : CHAIN1 HWTS ADC hardware trigger selection
bits : 20 - 27 (8 bit)
access : read-write
B2B1 : CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 28 - 28 (1 bit)
access : read-write
IE1 : CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 2/3 Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL2 : CHAIN2 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS2 : CHAIN2 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B2 : CHAIN2 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE2 : CHAIN2 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL3 : CHAIN3 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS3 : CHAIN3 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B3 : CHAIN3 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE3 : CHAIN3 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 4/5 Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL4 : CHAIN4 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS4 : CHAIN4 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B4 : CHAIN4 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE4 : CHAIN4 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL5 : CHAIN5 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS5 : CHAIN5 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B5 : CHAIN5 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE5 : CHAIN5 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 6/7 Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL6 : CHAIN6 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS6 : CHAIN6 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B6 : CHAIN6 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE6 : CHAIN6 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL7 : CHAIN7 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS7 : CHAIN7 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B7 : CHAIN7 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE7 : CHAIN7 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG0 Counter Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_DELAY : TRIGGER initial delay counter
bits : 0 - 15 (16 bit)
access : read-write
SAMPLE_INTERVAL : TRIGGER sampling interval counter
bits : 16 - 31 (16 bit)
access : read-write
ETC_TRIG Result Data 1/0 Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Result DATA0
bits : 0 - 11 (12 bit)
access : read-only
DATA1 : Result DATA1
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 3/2 Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Result DATA2
bits : 0 - 11 (12 bit)
access : read-only
DATA3 : Result DATA3
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 5/4 Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Result DATA4
bits : 0 - 11 (12 bit)
access : read-only
DATA5 : Result DATA5
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 7/6 Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Result DATA6
bits : 0 - 11 (12 bit)
access : read-only
DATA7 : Result DATA7
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Chain 0/1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : CHAIN0 CSEL ADC channel selection
bits : 0 - 3 (4 bit)
access : read-write
HWTS0 : CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.
bits : 4 - 11 (8 bit)
access : read-write
B2B0 : CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 12 - 12 (1 bit)
access : read-write
IE0 : CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 13 - 14 (2 bit)
access : read-write
CSEL1 : CHAIN1 CSEL ADC channel selection
bits : 16 - 19 (4 bit)
access : read-write
HWTS1 : CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.
bits : 20 - 27 (8 bit)
access : read-write
B2B1 : CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 28 - 28 (1 bit)
access : read-write
IE1 : CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 2/3 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL2 : CHAIN2 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS2 : CHAIN2 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B2 : CHAIN2 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE2 : CHAIN2 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL3 : CHAIN3 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS3 : CHAIN3 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B3 : CHAIN3 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE3 : CHAIN3 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 4/5 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL4 : CHAIN4 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS4 : CHAIN4 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B4 : CHAIN4 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE4 : CHAIN4 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL5 : CHAIN5 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS5 : CHAIN5 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B5 : CHAIN5 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE5 : CHAIN5 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 6/7 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL6 : CHAIN6 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS6 : CHAIN6 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B6 : CHAIN6 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE6 : CHAIN6 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL7 : CHAIN7 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS7 : CHAIN7 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B7 : CHAIN7 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE7 : CHAIN7 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Result Data 1/0 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Result DATA0
bits : 0 - 11 (12 bit)
access : read-only
DATA1 : Result DATA1
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 3/2 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Result DATA2
bits : 0 - 11 (12 bit)
access : read-only
DATA3 : Result DATA3
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 5/4 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Result DATA4
bits : 0 - 11 (12 bit)
access : read-only
DATA5 : Result DATA5
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 7/6 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Result DATA6
bits : 0 - 11 (12 bit)
access : read-only
DATA7 : Result DATA7
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG1 Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRIG : Software write 1 as the TRIGGER. This register is self-clearing.
bits : 0 - 0 (1 bit)
access : read-write
TRIG_MODE : TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
bits : 4 - 4 (1 bit)
access : read-write
TRIG_CHAIN : TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
bits : 8 - 10 (3 bit)
access : read-write
TRIG_PRIORITY : External trigger priority, 7 is highest, 0 is lowest .
bits : 12 - 14 (3 bit)
access : read-write
SYNC_MODE : TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
bits : 16 - 16 (1 bit)
access : read-write
ETC_TRIG1 Counter Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_DELAY : TRIGGER initial delay counter
bits : 0 - 15 (16 bit)
access : read-write
SAMPLE_INTERVAL : TRIGGER sampling interval counter
bits : 16 - 31 (16 bit)
access : read-write
ETC DONE0 and DONE1 IRQ State Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIG0_DONE0 : TRIG0 done0 interrupt detection
bits : 0 - 0 (1 bit)
access : read-write
TRIG1_DONE0 : TRIG1 done0 interrupt detection
bits : 1 - 1 (1 bit)
access : read-write
TRIG2_DONE0 : TRIG2 done0 interrupt detection
bits : 2 - 2 (1 bit)
access : read-write
TRIG3_DONE0 : TRIG3 done0 interrupt detection
bits : 3 - 3 (1 bit)
access : read-write
TRIG4_DONE0 : TRIG4 done0 interrupt detection
bits : 4 - 4 (1 bit)
access : read-write
TRIG5_DONE0 : TRIG5 done0 interrupt detection
bits : 5 - 5 (1 bit)
access : read-write
TRIG6_DONE0 : TRIG6 done0 interrupt detection
bits : 6 - 6 (1 bit)
access : read-write
TRIG7_DONE0 : TRIG7 done0 interrupt detection
bits : 7 - 7 (1 bit)
access : read-write
TRIG0_DONE1 : TRIG0 done1 interrupt detection
bits : 16 - 16 (1 bit)
access : read-write
TRIG1_DONE1 : TRIG1 done1 interrupt detection
bits : 17 - 17 (1 bit)
access : read-write
TRIG2_DONE1 : TRIG2 done1 interrupt detection
bits : 18 - 18 (1 bit)
access : read-write
TRIG3_DONE1 : TRIG3 done1 interrupt detection
bits : 19 - 19 (1 bit)
access : read-write
TRIG4_DONE1 : TRIG4 done1 interrupt detection
bits : 20 - 20 (1 bit)
access : read-write
TRIG5_DONE1 : TRIG5 done1 interrupt detection
bits : 21 - 21 (1 bit)
access : read-write
TRIG6_DONE1 : TRIG6 done1 interrupt detection
bits : 22 - 22 (1 bit)
access : read-write
TRIG7_DONE1 : TRIG7 done1 interrupt detection
bits : 23 - 23 (1 bit)
access : read-write
ETC_TRIG Chain 0/1 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : CHAIN0 CSEL ADC channel selection
bits : 0 - 3 (4 bit)
access : read-write
HWTS0 : CHAIN0 HWTS ADC hardware trigger selection
bits : 4 - 11 (8 bit)
access : read-write
B2B0 : CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 12 - 12 (1 bit)
access : read-write
IE0 : CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 13 - 14 (2 bit)
access : read-write
CSEL1 : CHAIN1 CSEL ADC channel selection
bits : 16 - 19 (4 bit)
access : read-write
HWTS1 : CHAIN1 HWTS ADC hardware trigger selection
bits : 20 - 27 (8 bit)
access : read-write
B2B1 : CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 28 - 28 (1 bit)
access : read-write
IE1 : CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 2/3 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL2 : CHAIN2 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS2 : CHAIN2 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B2 : CHAIN2 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE2 : CHAIN2 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL3 : CHAIN3 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS3 : CHAIN3 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B3 : CHAIN3 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE3 : CHAIN3 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 4/5 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL4 : CHAIN4 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS4 : CHAIN4 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B4 : CHAIN4 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE4 : CHAIN4 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL5 : CHAIN5 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS5 : CHAIN5 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B5 : CHAIN5 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE5 : CHAIN5 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 6/7 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL6 : CHAIN6 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS6 : CHAIN6 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B6 : CHAIN6 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE6 : CHAIN6 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL7 : CHAIN7 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS7 : CHAIN7 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B7 : CHAIN7 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE7 : CHAIN7 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Result Data 1/0 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Result DATA0
bits : 0 - 11 (12 bit)
access : read-only
DATA1 : Result DATA1
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 3/2 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Result DATA2
bits : 0 - 11 (12 bit)
access : read-only
DATA3 : Result DATA3
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 5/4 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Result DATA4
bits : 0 - 11 (12 bit)
access : read-only
DATA5 : Result DATA5
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 7/6 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Result DATA6
bits : 0 - 11 (12 bit)
access : read-only
DATA7 : Result DATA7
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG2 Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRIG : Software write 1 as the TRIGGER. This register is self-clearing.
bits : 0 - 0 (1 bit)
access : read-write
TRIG_MODE : TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
bits : 4 - 4 (1 bit)
access : read-write
TRIG_CHAIN : TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
bits : 8 - 10 (3 bit)
access : read-write
TRIG_PRIORITY : External trigger priority, 7 is highest, 0 is lowest .
bits : 12 - 14 (3 bit)
access : read-write
SYNC_MODE : TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
bits : 16 - 16 (1 bit)
access : read-write
ETC_TRIG2 Counter Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_DELAY : TRIGGER initial delay counter
bits : 0 - 15 (16 bit)
access : read-write
SAMPLE_INTERVAL : TRIGGER sampling interval counter
bits : 16 - 31 (16 bit)
access : read-write
ETC_TRIG Chain 0/1 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : CHAIN0 CSEL ADC channel selection
bits : 0 - 3 (4 bit)
access : read-write
HWTS0 : CHAIN0 HWTS ADC hardware trigger selection
bits : 4 - 11 (8 bit)
access : read-write
B2B0 : CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 12 - 12 (1 bit)
access : read-write
IE0 : CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 13 - 14 (2 bit)
access : read-write
CSEL1 : CHAIN1 CSEL ADC channel selection
bits : 16 - 19 (4 bit)
access : read-write
HWTS1 : CHAIN1 HWTS ADC hardware trigger selection
bits : 20 - 27 (8 bit)
access : read-write
B2B1 : CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 28 - 28 (1 bit)
access : read-write
IE1 : CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 2/3 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL2 : CHAIN2 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS2 : CHAIN2 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B2 : CHAIN2 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE2 : CHAIN2 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL3 : CHAIN3 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS3 : CHAIN3 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B3 : CHAIN3 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE3 : CHAIN3 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 4/5 Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL4 : CHAIN4 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS4 : CHAIN4 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B4 : CHAIN4 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE4 : CHAIN4 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL5 : CHAIN5 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS5 : CHAIN5 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B5 : CHAIN5 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE5 : CHAIN5 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 6/7 Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL6 : CHAIN6 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS6 : CHAIN6 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B6 : CHAIN6 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE6 : CHAIN6 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL7 : CHAIN7 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS7 : CHAIN7 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B7 : CHAIN7 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE7 : CHAIN7 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Result Data 1/0 Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Result DATA0
bits : 0 - 11 (12 bit)
access : read-only
DATA1 : Result DATA1
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 3/2 Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Result DATA2
bits : 0 - 11 (12 bit)
access : read-only
DATA3 : Result DATA3
bits : 16 - 27 (12 bit)
access : read-only
ETC DONE_2 and DONE_ERR IRQ State Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIG0_DONE2 : TRIG0 done2 interrupt detection
bits : 0 - 0 (1 bit)
access : read-write
TRIG1_DONE2 : TRIG1 done2 interrupt detection
bits : 1 - 1 (1 bit)
access : read-write
TRIG2_DONE2 : TRIG2 done2 interrupt detection
bits : 2 - 2 (1 bit)
access : read-write
TRIG3_DONE2 : TRIG3 done2 interrupt detection
bits : 3 - 3 (1 bit)
access : read-write
TRIG4_DONE2 : TRIG4 done2 interrupt detection
bits : 4 - 4 (1 bit)
access : read-write
TRIG5_DONE2 : TRIG5 done2 interrupt detection
bits : 5 - 5 (1 bit)
access : read-write
TRIG6_DONE2 : TRIG6 done2 interrupt detection
bits : 6 - 6 (1 bit)
access : read-write
TRIG7_DONE2 : TRIG7 done2 interrupt detection
bits : 7 - 7 (1 bit)
access : read-write
TRIG0_ERR : TRIG0 error interrupt detection
bits : 16 - 16 (1 bit)
access : read-write
TRIG1_ERR : TRIG1 error interrupt detection
bits : 17 - 17 (1 bit)
access : read-write
TRIG2_ERR : TRIG2 error interrupt detection
bits : 18 - 18 (1 bit)
access : read-write
TRIG3_ERR : TRIG3 error interrupt detection
bits : 19 - 19 (1 bit)
access : read-write
TRIG4_ERR : TRIG4 error interrupt detection
bits : 20 - 20 (1 bit)
access : read-write
TRIG5_ERR : TRIG5 error interrupt detection
bits : 21 - 21 (1 bit)
access : read-write
TRIG6_ERR : TRIG6 error interrupt detection
bits : 22 - 22 (1 bit)
access : read-write
TRIG7_ERR : TRIG7 error interrupt detection
bits : 23 - 23 (1 bit)
access : read-write
ETC_TRIG Result Data 5/4 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Result DATA4
bits : 0 - 11 (12 bit)
access : read-only
DATA5 : Result DATA5
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 7/6 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Result DATA6
bits : 0 - 11 (12 bit)
access : read-only
DATA7 : Result DATA7
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG3 Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRIG : Software write 1 as the TRIGGER. This register is self-clearing.
bits : 0 - 0 (1 bit)
access : read-write
TRIG_MODE : TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
bits : 4 - 4 (1 bit)
access : read-write
TRIG_CHAIN : TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
bits : 8 - 10 (3 bit)
access : read-write
TRIG_PRIORITY : External trigger priority, 7 is highest, 0 is lowest .
bits : 12 - 14 (3 bit)
access : read-write
SYNC_MODE : TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
bits : 16 - 16 (1 bit)
access : read-write
ETC_TRIG3 Counter Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_DELAY : TRIGGER initial delay counter
bits : 0 - 15 (16 bit)
access : read-write
SAMPLE_INTERVAL : TRIGGER sampling interval counter
bits : 16 - 31 (16 bit)
access : read-write
ETC_TRIG Chain 0/1 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : CHAIN0 CSEL ADC channel selection
bits : 0 - 3 (4 bit)
access : read-write
HWTS0 : CHAIN0 HWTS ADC hardware trigger selection
bits : 4 - 11 (8 bit)
access : read-write
B2B0 : CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 12 - 12 (1 bit)
access : read-write
IE0 : CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 13 - 14 (2 bit)
access : read-write
CSEL1 : CHAIN1 CSEL ADC channel selection
bits : 16 - 19 (4 bit)
access : read-write
HWTS1 : CHAIN1 HWTS ADC hardware trigger selection
bits : 20 - 27 (8 bit)
access : read-write
B2B1 : CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 28 - 28 (1 bit)
access : read-write
IE1 : CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 2/3 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL2 : CHAIN2 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS2 : CHAIN2 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B2 : CHAIN2 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE2 : CHAIN2 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL3 : CHAIN3 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS3 : CHAIN3 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B3 : CHAIN3 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE3 : CHAIN3 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 4/5 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL4 : CHAIN4 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS4 : CHAIN4 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B4 : CHAIN4 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE4 : CHAIN4 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL5 : CHAIN5 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS5 : CHAIN5 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B5 : CHAIN5 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE5 : CHAIN5 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 6/7 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL6 : CHAIN6 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS6 : CHAIN6 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B6 : CHAIN6 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE6 : CHAIN6 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL7 : CHAIN7 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS7 : CHAIN7 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B7 : CHAIN7 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE7 : CHAIN7 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Result Data 1/0 Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Result DATA0
bits : 0 - 11 (12 bit)
access : read-only
DATA1 : Result DATA1
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 3/2 Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Result DATA2
bits : 0 - 11 (12 bit)
access : read-only
DATA3 : Result DATA3
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 5/4 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Result DATA4
bits : 0 - 11 (12 bit)
access : read-only
DATA5 : Result DATA5
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 7/6 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Result DATA6
bits : 0 - 11 (12 bit)
access : read-only
DATA7 : Result DATA7
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG4 Control Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRIG : Software write 1 as the TRIGGER. This register is self-clearing.
bits : 0 - 0 (1 bit)
access : read-write
TRIG_MODE : TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
bits : 4 - 4 (1 bit)
access : read-write
TRIG_CHAIN : TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
bits : 8 - 10 (3 bit)
access : read-write
TRIG_PRIORITY : External trigger priority, 7 is highest, 0 is lowest .
bits : 12 - 14 (3 bit)
access : read-write
SYNC_MODE : TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
bits : 16 - 16 (1 bit)
access : read-write
ETC_TRIG4 Counter Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_DELAY : TRIGGER initial delay counter
bits : 0 - 15 (16 bit)
access : read-write
SAMPLE_INTERVAL : TRIGGER sampling interval counter
bits : 16 - 31 (16 bit)
access : read-write
ETC_TRIG Chain 0/1 Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : CHAIN0 CSEL ADC channel selection
bits : 0 - 3 (4 bit)
access : read-write
HWTS0 : CHAIN0 HWTS ADC hardware trigger selection
bits : 4 - 11 (8 bit)
access : read-write
B2B0 : CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 12 - 12 (1 bit)
access : read-write
IE0 : CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 13 - 14 (2 bit)
access : read-write
CSEL1 : CHAIN1 CSEL ADC channel selection
bits : 16 - 19 (4 bit)
access : read-write
HWTS1 : CHAIN1 HWTS ADC hardware trigger selection
bits : 20 - 27 (8 bit)
access : read-write
B2B1 : CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 28 - 28 (1 bit)
access : read-write
IE1 : CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 2/3 Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL2 : CHAIN2 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS2 : CHAIN2 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B2 : CHAIN2 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE2 : CHAIN2 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL3 : CHAIN3 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS3 : CHAIN3 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B3 : CHAIN3 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE3 : CHAIN3 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC DMA control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIG0_ENABLE : When TRIG0 done enable DMA request
bits : 0 - 0 (1 bit)
access : read-write
TRIG1_ENABLE : When TRIG1 done enable DMA request
bits : 1 - 1 (1 bit)
access : read-write
TRIG2_ENABLE : When TRIG2 done enable DMA request
bits : 2 - 2 (1 bit)
access : read-write
TRIG3_ENABLE : When TRIG3 done enable DMA request
bits : 3 - 3 (1 bit)
access : read-write
TRIG4_ENABLE : When TRIG4 done enable DMA request
bits : 4 - 4 (1 bit)
access : read-write
TRIG5_ENABLE : When TRIG5 done enable DMA request
bits : 5 - 5 (1 bit)
access : read-write
TRIG6_ENABLE : When TRIG6 done enable DMA request
bits : 6 - 6 (1 bit)
access : read-write
TRIG7_ENABLE : When TRIG7 done enable DMA request
bits : 7 - 7 (1 bit)
access : read-write
TRIG0_REQ : When TRIG0 done DMA request detection
bits : 16 - 16 (1 bit)
access : read-write
TRIG1_REQ : When TRIG1 done DMA request detection
bits : 17 - 17 (1 bit)
access : read-write
TRIG2_REQ : When TRIG2 done DMA request detection
bits : 18 - 18 (1 bit)
access : read-write
TRIG3_REQ : When TRIG3 done DMA request detection
bits : 19 - 19 (1 bit)
access : read-write
TRIG4_REQ : When TRIG4 done DMA request detection
bits : 20 - 20 (1 bit)
access : read-write
TRIG5_REQ : When TRIG5 done DMA request detection
bits : 21 - 21 (1 bit)
access : read-write
TRIG6_REQ : When TRIG6 done DMA request detection
bits : 22 - 22 (1 bit)
access : read-write
TRIG7_REQ : When TRIG7 done DMA request detection
bits : 23 - 23 (1 bit)
access : read-write
ETC_TRIG Chain 4/5 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL4 : CHAIN4 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS4 : CHAIN4 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B4 : CHAIN4 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE4 : CHAIN4 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL5 : CHAIN5 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS5 : CHAIN5 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B5 : CHAIN5 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE5 : CHAIN5 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 6/7 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL6 : CHAIN6 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS6 : CHAIN6 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B6 : CHAIN6 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE6 : CHAIN6 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL7 : CHAIN7 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS7 : CHAIN7 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B7 : CHAIN7 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE7 : CHAIN7 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Result Data 1/0 Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Result DATA0
bits : 0 - 11 (12 bit)
access : read-only
DATA1 : Result DATA1
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 3/2 Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Result DATA2
bits : 0 - 11 (12 bit)
access : read-only
DATA3 : Result DATA3
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 5/4 Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Result DATA4
bits : 0 - 11 (12 bit)
access : read-only
DATA5 : Result DATA5
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 7/6 Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Result DATA6
bits : 0 - 11 (12 bit)
access : read-only
DATA7 : Result DATA7
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG5 Control Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRIG : Software write 1 as the TRIGGER
bits : 0 - 0 (1 bit)
access : read-write
TRIG_MODE : TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
bits : 4 - 4 (1 bit)
access : read-write
TRIG_CHAIN : TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
bits : 8 - 10 (3 bit)
access : read-write
TRIG_PRIORITY : External trigger priority, 7 is highest, 0 is lowest .
bits : 12 - 14 (3 bit)
access : read-write
SYNC_MODE : TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
bits : 16 - 16 (1 bit)
access : read-write
ETC_TRIG5 Counter Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_DELAY : TRIGGER initial delay counter
bits : 0 - 15 (16 bit)
access : read-write
SAMPLE_INTERVAL : TRIGGER sampling interval counter
bits : 16 - 31 (16 bit)
access : read-write
ETC_TRIG Chain 0/1 Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : CHAIN0 CSEL ADC channel selection
bits : 0 - 3 (4 bit)
access : read-write
HWTS0 : CHAIN0 HWTS ADC hardware trigger selection
bits : 4 - 11 (8 bit)
access : read-write
B2B0 : CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 12 - 12 (1 bit)
access : read-write
IE0 : CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 13 - 14 (2 bit)
access : read-write
CSEL1 : CHAIN1 CSEL ADC channel selection
bits : 16 - 19 (4 bit)
access : read-write
HWTS1 : CHAIN1 HWTS ADC hardware trigger selection
bits : 20 - 27 (8 bit)
access : read-write
B2B1 : CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
bits : 28 - 28 (1 bit)
access : read-write
IE1 : CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 2/3 Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL2 : CHAIN2 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS2 : CHAIN2 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B2 : CHAIN2 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE2 : CHAIN2 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL3 : CHAIN3 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS3 : CHAIN3 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B3 : CHAIN3 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE3 : CHAIN3 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 4/5 Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL4 : CHAIN4 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS4 : CHAIN4 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B4 : CHAIN4 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE4 : CHAIN4 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL5 : CHAIN5 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS5 : CHAIN5 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B5 : CHAIN5 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE5 : CHAIN5 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Chain 6/7 Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL6 : CHAIN6 CSEL
bits : 0 - 3 (4 bit)
access : read-write
HWTS6 : CHAIN6 HWTS
bits : 4 - 11 (8 bit)
access : read-write
B2B6 : CHAIN6 B2B
bits : 12 - 12 (1 bit)
access : read-write
IE6 : CHAIN6 IE
bits : 13 - 14 (2 bit)
access : read-write
CSEL7 : CHAIN7 CSEL
bits : 16 - 19 (4 bit)
access : read-write
HWTS7 : CHAIN7 HWTS
bits : 20 - 27 (8 bit)
access : read-write
B2B7 : CHAIN7 B2B
bits : 28 - 28 (1 bit)
access : read-write
IE7 : CHAIN7 IE
bits : 29 - 30 (2 bit)
access : read-write
ETC_TRIG Result Data 1/0 Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Result DATA0
bits : 0 - 11 (12 bit)
access : read-only
DATA1 : Result DATA1
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 3/2 Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Result DATA2
bits : 0 - 11 (12 bit)
access : read-only
DATA3 : Result DATA3
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 5/4 Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Result DATA4
bits : 0 - 11 (12 bit)
access : read-only
DATA5 : Result DATA5
bits : 16 - 27 (12 bit)
access : read-only
ETC_TRIG Result Data 7/6 Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Result DATA6
bits : 0 - 11 (12 bit)
access : read-only
DATA7 : Result DATA7
bits : 16 - 27 (12 bit)
access : read-only
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