Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFAC byte (0x0)
mem_usage : registers
protection : not protected
Auxiliary Control Register,
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISFOLD : Disables folding of IT instructions.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISFOLD_0
Normal operation.
End of enumeration elements list.
FPEXCODIS : Disables FPU exception outputs.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : FPEXCODIS_0
Normal operation.
0x1 : FPEXCODIS_1
FPU exception outputs are disabled.
End of enumeration elements list.
DISRAMODE : Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISRAMODE_0
Normal operation.
0x1 : DISRAMODE_1
Dynamic disabled.
End of enumeration elements list.
DISITMATBFLUSH : Disables ITM and DWT ATB flush.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x1 : DISITMATBFLUSH_1
ITM and DWT ATB flush disabled, this bit is always 1.
End of enumeration elements list.
DISBTACREAD : Disables BTAC read.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISBTACREAD_0
Normal operation.
0x1 : DISBTACREAD_1
BTAC is not used and only static branch prediction can occur.
End of enumeration elements list.
DISBTACALLOC : Disables BTAC allocate.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISBTACALLOC_0
Normal operation.
0x1 : DISBTACALLOC_1
No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated.
End of enumeration elements list.
DISCRITAXIRUR : Disables critical AXI Read-Under-Read.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISCRITAXIRUR_0
Normal operation.
0x1 : DISCRITAXIRUR_1
An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set.
End of enumeration elements list.
DISDI : Disables dual-issued.
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
0 : DISDI_0
Normal operation.
0x1 : DISDI_1
Nothing can be dual-issued when this instruction type is in channel 0.
End of enumeration elements list.
DISISSCH1 : Disables dual-issued.
bits : 21 - 25 (5 bit)
access : read-write
Enumeration:
0 : DISISSCH1_0
Normal operation.
0x1 : DISISSCH1_1
Nothing can be dual-issued when this instruction type is in channel 1.
End of enumeration elements list.
DISDYNADD : Disables dynamic allocation of ADD and SUB instructions
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISDYNADD_0
Normal operation. Some ADD and SUB instrctions are resolved in EX1.
0x1 : DISDYNADD_1
All ADD and SUB instructions are resolved in EX2.
End of enumeration elements list.
DISCRITAXIRUW : Disables critical AXI read-under-write
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISCRITAXIRUW_0
Normal operation. This is backwards compatible with r0.
0x1 : DISCRITAXIRUW_1
AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete.
End of enumeration elements list.
DISFPUISSOPT : Disables critical AXI read-under-write
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISFPUISSOPT_0
Normal operation.
End of enumeration elements list.
CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Indicates patch release: 0x0 = Patch 0
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Indicates part number
bits : 4 - 15 (12 bit)
access : read-only
ARCHITECTURE : ARCHITECTURE
bits : 16 - 19 (4 bit)
access : read-only
VARIANT : Indicates processor revision: 0x2 = Revision 2
bits : 20 - 23 (4 bit)
access : read-only
IMPLEMENTER : Implementer code
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Active exception number
bits : 0 - 8 (9 bit)
access : read-only
RETTOBASE : Indicates whether there are preempted active exceptions
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : RETTOBASE_0
there are preempted active exceptions to execute
0x1 : RETTOBASE_1
there are no active exceptions, or the currently-executing exception is the only active exception
End of enumeration elements list.
VECTPENDING : Exception number of the highest priority pending enabled exception
bits : 12 - 20 (9 bit)
access : read-only
ISRPENDING : Interrupt pending flag, excluding NMI and Faults
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : ISRPENDING_0
No external interrupt pending.
0x1 : ISRPENDING_1
External interrupt pending.
End of enumeration elements list.
PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
0 : PENDSTCLR_0
no effect
0x1 : PENDSTCLR_1
removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick exception set-pending bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : PENDSTSET_0
write: no effect; read: SysTick exception is not pending
0x1 : PENDSTSET_1
write: changes SysTick exception state to pending; read: SysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV clear-pending bit
bits : 27 - 27 (1 bit)
access : write-only
Enumeration:
0 : PENDSVCLR_0
no effect
0x1 : PENDSVCLR_1
removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV set-pending bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : PENDSVSET_0
write: no effect; read: PendSV exception is not pending
0x1 : PENDSVSET_1
write: changes PendSV exception state to pending; read: PendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI set-pending bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NMIPENDSET_0
write: no effect; read: NMI exception is not pending
0x1 : NMIPENDSET_1
write: changes NMI exception state to pending; read: NMI exception is pending
End of enumeration elements list.
Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector table base offset
bits : 7 - 31 (25 bit)
access : read-write
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTRESET : Writing 1 to this bit causes a local system reset
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : VECTRESET_0
No change
0x1 : VECTRESET_1
Causes a local system reset
End of enumeration elements list.
VECTCLRACTIVE : Writing 1 to this bit clears all active state information for fixed and configurable exceptions.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
0 : VECTCLRACTIVE_0
No change
0x1 : VECTCLRACTIVE_1
Clears all active state information for fixed and configurable exceptions
End of enumeration elements list.
SYSRESETREQ : System reset request
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
0 : SYSRESETREQ_0
no system reset request
0x1 : SYSRESETREQ_1
asserts a signal to the outer system that requests a reset
End of enumeration elements list.
PRIGROUP : Interrupt priority grouping field. This field determines the split of group priority from subpriority.
bits : 8 - 10 (3 bit)
access : read-write
ENDIANNESS : Data endianness
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : ENDIANNESS_0
Little-endian
0x1 : ENDIANNESS_1
Big-endian
End of enumeration elements list.
VECTKEY : Register key
bits : 16 - 31 (16 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Indicates sleep-on-exit when returning from Handler mode to Thread mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SLEEPONEXIT_0
o not sleep when returning to Thread mode
0x1 : SLEEPONEXIT_1
enter sleep, or deep sleep, on return from an ISR
End of enumeration elements list.
SLEEPDEEP : Controls whether the processor uses sleep or deep sleep as its low power mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SLEEPDEEP_0
sleep
0x1 : SLEEPDEEP_1
deep sleep
End of enumeration elements list.
SEVONPEND : Send Event on Pending bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SEVONPEND_0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
0x1 : SEVONPEND_1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
End of enumeration elements list.
Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONBASETHRDENA : Indicates how the processor enters Thread mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NONBASETHRDENA_0
processor can enter Thread mode only when no exception is active
0x1 : NONBASETHRDENA_1
processor can enter Thread mode from any level under the control of an EXC_RETURN value
End of enumeration elements list.
USERSETMPEND : Enables unprivileged software access to the STIR
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : USERSETMPEND_0
disable
0x1 : USERSETMPEND_1
enable
End of enumeration elements list.
UNALIGN_TRP : Enables unaligned access traps
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : UNALIGN_TRP_0
do not trap unaligned halfword and word accesses
0x1 : UNALIGN_TRP_1
trap unaligned halfword and word accesses
End of enumeration elements list.
DIV_0_TRP : Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DIV_0_TRP_0
do not trap divide by 0
0x1 : DIV_0_TRP_1
trap divide by 0
End of enumeration elements list.
BFHFNMIGN : Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : BFHFNMIGN_0
data bus faults caused by load and store instructions cause a lock-up
0x1 : BFHFNMIGN_1
handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
End of enumeration elements list.
STKALIGN : Indicates stack alignment on exception entry
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : STKALIGN_0
4-byte aligned
0x1 : STKALIGN_1
8-byte aligned
End of enumeration elements list.
DC : Enables L1 data cache.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DC_0
L1 data cache disabled
0x1 : DC_1
L1 data cache enabled
End of enumeration elements list.
IC : Enables L1 instruction cache.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : IC_0
L1 instruction cache disabled
0x1 : IC_1
L1 instruction cache enabled
End of enumeration elements list.
BP : Always reads-as-one. It indicates branch prediction is enabled.
bits : 18 - 18 (1 bit)
access : read-only
System Handler Priority Register 1
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of system handler 4, MemManage
bits : 0 - 7 (8 bit)
access : read-write
PRI_5 : Priority of system handler 5, BusFault
bits : 8 - 15 (8 bit)
access : read-write
PRI_6 : Priority of system handler 6, UsageFault
bits : 16 - 23 (8 bit)
access : read-write
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of system handler 11, SVCall
bits : 24 - 31 (8 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of system handler 14, PendSV
bits : 16 - 23 (8 bit)
access : read-write
PRI_15 : Priority of system handler 15, SysTick exception
bits : 24 - 31 (8 bit)
access : read-write
System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : MemManage exception active bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEMFAULTACT_0
exception is not active
0x1 : MEMFAULTACT_1
exception is active
End of enumeration elements list.
BUSFAULTACT : BusFault exception active bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : BUSFAULTACT_0
exception is not active
0x1 : BUSFAULTACT_1
exception is active
End of enumeration elements list.
USGFAULTACT : UsageFault exception active bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : USGFAULTACT_0
exception is not active
0x1 : USGFAULTACT_1
exception is active
End of enumeration elements list.
SVCALLACT : SVCall active bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SVCALLACT_0
exception is not active
0x1 : SVCALLACT_1
exception is active
End of enumeration elements list.
MONITORACT : Debug monitor active bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : MONITORACT_0
exception is not active
0x1 : MONITORACT_1
exception is active
End of enumeration elements list.
PENDSVACT : PendSV exception active bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : PENDSVACT_0
exception is not active
0x1 : PENDSVACT_1
exception is active
End of enumeration elements list.
SYSTICKACT : SysTick exception active bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SYSTICKACT_0
exception is not active
0x1 : SYSTICKACT_1
exception is active
End of enumeration elements list.
USGFAULTPENDED : UsageFault exception pending bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : USGFAULTPENDED_0
exception is not pending
0x1 : USGFAULTPENDED_1
exception is pending
End of enumeration elements list.
MEMFAULTPENDED : MemManage exception pending bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : MEMFAULTPENDED_0
exception is not pending
0x1 : MEMFAULTPENDED_1
exception is pending
End of enumeration elements list.
BUSFAULTPENDED : BusFault exception pending bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : BUSFAULTPENDED_0
exception is not pending
0x1 : BUSFAULTPENDED_1
exception is pending
End of enumeration elements list.
SVCALLPENDED : SVCall pending bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SVCALLPENDED_0
exception is not pending
0x1 : SVCALLPENDED_1
exception is pending
End of enumeration elements list.
MEMFAULTENA : MemManage enable bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : MEMFAULTENA_0
disable the exception
0x1 : MEMFAULTENA_1
enable the exception
End of enumeration elements list.
BUSFAULTENA : BusFault enable bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : BUSFAULTENA_0
disable the exception
0x1 : BUSFAULTENA_1
enable the exception
End of enumeration elements list.
USGFAULTENA : UsageFault enable bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : USGFAULTENA_0
disable the exception
0x1 : USGFAULTENA_1
enable the exception
End of enumeration elements list.
Configurable Fault Status Register
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IACCVIOL : Instruction access violation flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : IACCVIOL_0
no instruction access violation fault
0x1 : IACCVIOL_1
the processor attempted an instruction fetch from a location that does not permit execution
End of enumeration elements list.
DACCVIOL : Data access violation flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DACCVIOL_0
no data access violation fault
0x1 : DACCVIOL_1
the processor attempted a load or store at a location that does not permit the operation
End of enumeration elements list.
MUNSTKERR : MemManage fault on unstacking for a return from exception
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MUNSTKERR_0
no unstacking fault
0x1 : MUNSTKERR_1
unstack for an exception return has caused one or more access violations
End of enumeration elements list.
MSTKERR : MemManage fault on stacking for exception entry
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MSTKERR_0
no stacking fault
0x1 : MSTKERR_1
stacking for an exception entry has caused one or more access violations
End of enumeration elements list.
MLSPERR : MemManage fault occurred during floating-point lazy state preservation
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MLSPERR_0
No MemManage fault occurred during floating-point lazy state preservation
0x1 : MLSPERR_1
A MemManage fault occurred during floating-point lazy state preservation
End of enumeration elements list.
MMARVALID : MemManage Fault Address Register (MMFAR) valid flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MMARVALID_0
value in MMAR is not a valid fault address
0x1 : MMARVALID_1
MMAR holds a valid fault address
End of enumeration elements list.
IBUSERR : Instruction bus error
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : IBUSERR_0
no instruction bus error
0x1 : IBUSERR_1
instruction bus error
End of enumeration elements list.
PRECISERR : Precise data bus error
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : PRECISERR_0
no precise data bus error
0x1 : PRECISERR_1
a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
End of enumeration elements list.
IMPRECISERR : Imprecise data bus error
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : IMPRECISERR_0
no imprecise data bus error
0x1 : IMPRECISERR_1
a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
End of enumeration elements list.
UNSTKERR : BusFault on unstacking for a return from exception
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : UNSTKERR_0
no unstacking fault
0x1 : UNSTKERR_1
unstack for an exception return has caused one or more BusFaults
End of enumeration elements list.
STKERR : BusFault on stacking for exception entry
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : STKERR_0
no stacking fault
0x1 : STKERR_1
stacking for an exception entry has caused one or more BusFaults
End of enumeration elements list.
LSPERR : Bus fault occurred during floating-point lazy state preservation
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : LSPERR_0
No bus fault occurred during floating-point lazy state preservation
0x1 : LSPERR_1
A bus fault occurred during floating-point lazy state preservation
End of enumeration elements list.
BFARVALID : BusFault Address Register (BFAR) valid flag
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : BFARVALID_0
value in BFAR is not a valid fault address
0x1 : BFARVALID_1
BFAR holds a valid fault address
End of enumeration elements list.
UNDEFINSTR : Undefined instruction UsageFault
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : UNDEFINSTR_0
no undefined instruction UsageFault
0x1 : UNDEFINSTR_1
the processor has attempted to execute an undefined instruction
End of enumeration elements list.
INVSTATE : Invalid state UsageFault
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : INVSTATE_0
no invalid state UsageFault
0x1 : INVSTATE_1
the processor has attempted to execute an instruction that makes illegal use of the EPSR
End of enumeration elements list.
INVPC : Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : INVPC_0
no invalid PC load UsageFault
0x1 : INVPC_1
the processor has attempted an illegal load of EXC_RETURN to the PC
End of enumeration elements list.
NOCP : No coprocessor UsageFault
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOCP_0
no UsageFault caused by attempting to access a coprocessor
0x1 : NOCP_1
the processor has attempted to access a coprocessor
End of enumeration elements list.
UNALIGNED : Unaligned access UsageFault
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : UNALIGNED_0
no unaligned access fault, or unaligned access trapping not enabled
0x1 : UNALIGNED_1
the processor has made an unaligned memory access
End of enumeration elements list.
DIVBYZERO : Divide by zero UsageFault
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DIVBYZERO_0
no divide by zero fault, or divide by zero trapping not enabled
0x1 : DIVBYZERO_1
the processor has executed an SDIV or UDIV instruction with a divisor of 0
End of enumeration elements list.
HardFault Status register
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTTBL : Indicates a BusFault on a vector table read during exception processing.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : VECTTBL_0
no BusFault on vector table read
0x1 : VECTTBL_1
BusFault on vector table read
End of enumeration elements list.
FORCED : Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : FORCED_0
no forced HardFault
0x1 : FORCED_1
forced HardFault
End of enumeration elements list.
DEBUGEVT : Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DEBUGEVT_0
No Debug event has occurred.
0x1 : DEBUGEVT_1
Debug event has occurred. The Debug Fault Status Register has been updated.
End of enumeration elements list.
Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED : Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HALTED_0
No active halt request debug event
0x1 : HALTED_1
Halt request debug event active
End of enumeration elements list.
BKPT : Debug event generated by BKPT instruction execution or a breakpoint match in FPB
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : BKPT_0
No current breakpoint debug event
0x1 : BKPT_1
At least one current breakpoint debug event
End of enumeration elements list.
DWTTRAP : Debug event generated by the DWT
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DWTTRAP_0
No current debug events generated by the DWT
0x1 : DWTTRAP_1
At least one current debug event generated by the DWT
End of enumeration elements list.
VCATCH : Indicates triggering of a Vector catch
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : VCATCH_0
No Vector catch triggered
0x1 : VCATCH_1
Vector catch triggered
End of enumeration elements list.
EXTERNAL : Debug event generated because of the assertion of an external debug request
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EXTERNAL_0
No external debug request debug event
0x1 : EXTERNAL_1
External debug request debug event
End of enumeration elements list.
MemManage Fault Address Register
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of MemManage fault location
bits : 0 - 31 (32 bit)
access : read-write
BusFault Address Register
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of the BusFault location
bits : 0 - 31 (32 bit)
access : read-write
Processor Feature Register 0
address_offset : 0xD40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATE0 : ARM instruction set support
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : STATE0_0
ARMv7-M unused
0x1 : STATE0_1
ARMv7-M unused
0x2 : STATE0_2
ARMv7-M unused
0x3 : STATE0_3
Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions.
End of enumeration elements list.
STATE1 : Thumb instruction set support
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : STATE1_0
The processor does not support the ARM instruction set.
0x1 : STATE1_1
ARMv7-M unused
End of enumeration elements list.
STATE2 : ARMv7-M unused
bits : 8 - 11 (4 bit)
access : read-only
STATE3 : ARMv7-M unused
bits : 12 - 15 (4 bit)
access : read-only
Processor Feature Register 1
address_offset : 0xD44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROGMODEL : M profile programmers' model
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : PROGMODEL_0
ARMv7-M unused
0x2 : PROGMODEL_2
Two-stack programmers' model supported
End of enumeration elements list.
Debug Feature Register
address_offset : 0xD48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEBUGMODEL : Support for memory-mapped debug model for M profile processors
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : DEBUGMODEL_0
Not supported
0x1 : DEBUGMODEL_1
Support for M profile Debug architecture, with memory-mapped access.
End of enumeration elements list.
Auxiliary Feature Register
address_offset : 0xD4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMPLEMENTATION_DEFINED0 : Gives information about the IMPLEMENTATION DEFINED features of a processor implementation.
bits : 0 - 3 (4 bit)
access : read-only
IMPLEMENTATION_DEFINED1 : Gives information about the IMPLEMENTATION DEFINED features of a processor implementation.
bits : 4 - 7 (4 bit)
access : read-only
IMPLEMENTATION_DEFINED2 : Gives information about the IMPLEMENTATION DEFINED features of a processor implementation.
bits : 8 - 11 (4 bit)
access : read-only
IMPLEMENTATION_DEFINED3 : Gives information about the IMPLEMENTATION DEFINED features of a processor implementation.
bits : 12 - 15 (4 bit)
access : read-only
Memory Model Feature Register 0
address_offset : 0xD50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PMSASUPPORT : Indicates support for a PMSA
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : PMSASUPPORT_0
Not supported
0x1 : PMSASUPPORT_1
ARMv7-M unused
0x2 : PMSASUPPORT_2
ARMv7-M unused
0x3 : PMSASUPPORT_3
PMSAv7, providing support for a base region and subregions.
End of enumeration elements list.
OUTERMOST_SHAREABILITY : Indicates the outermost shareability domain implemented
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : OUTERMOST_SHAREABILITY_0
Implemented as Non-cacheable
0x1 : OUTERMOST_SHAREABILITY_1
ARMv7-M unused
0x2 : OUTERMOST_SHAREABILITY_2
ARMv7-M unused
0x3 : OUTERMOST_SHAREABILITY_3
ARMv7-M unused
0x4 : OUTERMOST_SHAREABILITY_4
ARMv7-M unused
0x5 : OUTERMOST_SHAREABILITY_5
ARMv7-M unused
0x6 : OUTERMOST_SHAREABILITY_6
ARMv7-M unused
0x7 : OUTERMOST_SHAREABILITY_7
ARMv7-M unused
0x8 : OUTERMOST_SHAREABILITY_8
ARMv7-M unused
0x9 : OUTERMOST_SHAREABILITY_9
ARMv7-M unused
0xA : OUTERMOST_SHAREABILITY_10
ARMv7-M unused
0xB : OUTERMOST_SHAREABILITY_11
ARMv7-M unused
0xC : OUTERMOST_SHAREABILITY_12
ARMv7-M unused
0xD : OUTERMOST_SHAREABILITY_13
ARMv7-M unused
0xE : OUTERMOST_SHAREABILITY_14
ARMv7-M unused
0xF : OUTERMOST_SHAREABILITY_15
Shareability ignored.
End of enumeration elements list.
SHAREABILITY_LEVELS : Indicates the number of shareability levels implemented
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : SHAREABILITY_LEVELS_0
One level of shareability implemented
0x1 : SHAREABILITY_LEVELS_1
ARMv7-M unused
End of enumeration elements list.
TCM_SUPPORT : Indicates the support for Tightly Coupled Memory
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : TCM_SUPPORT_0
No tightly coupled memories implemented.
0x1 : TCM_SUPPORT_1
Tightly coupled memories implemented with IMPLEMENTATION DEFINED control.
0x2 : TCM_SUPPORT_2
ARMv7-M unused
End of enumeration elements list.
AUXILIARY_REGISTERS : Indicates the support for Auxiliary registers
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : AUXILIARY_REGISTERS_0
Not supported
0x1 : AUXILIARY_REGISTERS_1
Support for Auxiliary Control Register only.
0x2 : AUXILIARY_REGISTERS_2
ARMv7-M unused
End of enumeration elements list.
Memory Model Feature Register 1
address_offset : 0xD54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID_MMFR1 : Gives information about the implemented memory model and memory management support.
bits : 0 - 31 (32 bit)
access : read-only
Memory Model Feature Register 2
address_offset : 0xD58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WFI_STALL : Indicates the support for Wait For Interrupt (WFI) stalling
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : WFI_STALL_0
Not supported
0x1 : WFI_STALL_1
Support for WFI stalling
End of enumeration elements list.
Memory Model Feature Register 3
address_offset : 0xD5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID_MMFR3 : Gives information about the implemented memory model and memory management support.
bits : 0 - 31 (32 bit)
access : read-only
Instruction Set Attributes Register 0
address_offset : 0xD60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITCOUNT_INSTRS : Indicates the supported Bit Counting instructions
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : BITCOUNT_INSTRS_0
None supported, ARMv7-M unused
0x1 : BITCOUNT_INSTRS_1
Adds support for the CLZ instruction
End of enumeration elements list.
BITFIELD_INSTRS : Indicates the supported BitField instructions
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : BITFIELD_INSTRS_0
None supported, ARMv7-M unused
0x1 : BITFIELD_INSTRS_1
Adds support for the BFC, BFI, SBFX, and UBFX instructions
End of enumeration elements list.
CMPBRANCH_INSTRS : Indicates the supported combined Compare and Branch instructions
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : CMPBRANCH_INSTRS_0
None supported, ARMv7-M unused
0x1 : CMPBRANCH_INSTRS_1
Adds support for the CBNZ and CBZ instructions
End of enumeration elements list.
COPROC_INSTRS : Indicates the supported Coprocessor instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : COPROC_INSTRS_0
None supported, except for separately attributed architectures, for example the Floating-point extension
0x1 : COPROC_INSTRS_1
Adds support for generic CDP, LDC, MCR, MRC, and STC instructions
0x2 : COPROC_INSTRS_2
As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions
0x3 : COPROC_INSTRS_3
As for 2, and adds support for generic MCRR and MRRC instructions
0x4 : COPROC_INSTRS_4
As for 3, and adds support for generic MCRR2 and MRRC2 instructions
End of enumeration elements list.
DEBUG_INSTRS : Indicates the supported Debug instructions
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : DEBUG_INSTRS_0
None supported, ARMv7-M unused
0x1 : DEBUG_INSTRS_1
Adds support for the BKPT instruction
End of enumeration elements list.
DIVIDE_INSTRS : Indicates the supported Divide instructions
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : DIVIDE_INSTRS_0
None supported, ARMv7-M unused
0x1 : DIVIDE_INSTRS_1
Adds support for the SDIV and UDIV instructions
End of enumeration elements list.
Instruction Set Attributes Register 1
address_offset : 0xD64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTEND_INSTRS : Indicates the supported Extend instructions
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : EXTEND_INSTRS_0
None supported, ARMv7-M unused
0x1 : EXTEND_INSTRS_1
Adds support for the SXTB, SXTH, UXTB, and UXTH instructions
0x2 : EXTEND_INSTRS_2
As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions
End of enumeration elements list.
IFTHEN_INSTRS : Indicates the supported IfThen instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : IFTHEN_INSTRS_0
None supported, ARMv7-M unused
0x1 : IFTHEN_INSTRS_1
Adds support for the IT instructions, and for the IT bits in the PSRs
End of enumeration elements list.
IMMEDIATE_INSTRS : Indicates the support for data-processing instructions with long immediate
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : IMMEDIATE_INSTRS_0
None supported, ARMv7-M unused
0x1 : IMMEDIATE_INSTRS_1
Adds support for the ADDW, MOVW, MOVT, and SUBW instructions
End of enumeration elements list.
INTERWORK_INSTRS : Indicates the supported Interworking instructions
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : INTERWORK_INSTRS_0
None supported, ARMv7-M unused
0x1 : INTERWORK_INSTRS_1
Adds support for the BX instruction, and the T bit in the PSR
0x2 : INTERWORK_INSTRS_2
As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior
0x3 : INTERWORK_INSTRS_3
ARMv7-M unused
End of enumeration elements list.
Instruction Set Attributes Register 2
address_offset : 0xD68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOADSTORE_INSTRS : Indicates the supported additional load and store instructions
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : LOADSTORE_INSTRS_0
None supported, ARMv7-M unused
0x1 : LOADSTORE_INSTRS_1
Adds support for the LDRD and STRD instructions
End of enumeration elements list.
MEMHINT_INSTRS : Indicates the supported Memory Hint instructions
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : MEMHINT_INSTRS_0
None supported, ARMv7-M unused.
0x1 : MEMHINT_INSTRS_1
Adds support for the PLD instruction, ARMv7-M unused.
0x2 : MEMHINT_INSTRS_2
As for 1, ARMv7-M unused.
0x3 : MEMHINT_INSTRS_3
As for 1 or 2, and adds support for the PLI instruction.
End of enumeration elements list.
MULTIACCESSINT_INSTRS : Indicates the support for multi-access interruptible instructions
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : MULTIACCESSINT_INSTRS_0
None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused.
0x1 : MULTIACCESSINT_INSTRS_1
LDM and STM instructions are restartable.
0x2 : MULTIACCESSINT_INSTRS_2
LDM and STM instructions are continuable.
End of enumeration elements list.
MULT_INSTRS : Indicates the supported additional Multiply instructions
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : MULT_INSTRS_0
None supported. This means only MUL is supported. ARMv7-M unused.
0x1 : MULT_INSTRS_1
Adds support for the MLA instruction, ARMv7-M unused.
0x2 : MULT_INSTRS_2
As for 1, and adds support for the MLS instruction.
End of enumeration elements list.
MULTS_INSTRS : Indicates the supported advanced signed Multiply instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : MULTS_INSTRS_0
None supported, ARMv7-M unused
0x1 : MULTS_INSTRS_1
Adds support for the SMULL and SMLAL instructions
0x2 : MULTS_INSTRS_2
As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions.
0x3 : MULTS_INSTRS_3
As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions.
End of enumeration elements list.
MULTU_INSTRS : Indicates the supported advanced unsigned Multiply instructions
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : MULTU_INSTRS_0
None supported, ARMv7-M unused
0x1 : MULTU_INSTRS_1
Adds support for the UMULL and UMLAL instructions.
0x2 : MULTU_INSTRS_2
As for 1, and adds support for the UMAAL instruction.
End of enumeration elements list.
REVERSAL_INSTRS : Indicates the supported Reversal instructions
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
0 : REVERSAL_INSTRS_0
None supported, ARMv7-M unused
0x1 : REVERSAL_INSTRS_1
Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused.
0x2 : REVERSAL_INSTRS_2
As for 1, and adds support for the RBIT instruction.
End of enumeration elements list.
Instruction Set Attributes Register 3
address_offset : 0xD6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SATURATE_INSTRS : Indicates the supported Saturate instructions
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : SATURATE_INSTRS_0
None supported
0x1 : SATURATE_INSTRS_1
Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs.
End of enumeration elements list.
SIMD_INSTRS : Indicates the supported SIMD instructions
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : SIMD_INSTRS_0
None supported, ARMv7-M unused.
0x1 : SIMD_INSTRS_1
Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs.
0x3 : SIMD_INSTRS_3
As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs.
End of enumeration elements list.
SVC_INSTRS : Indicates the supported SVC instructions
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : SVC_INSTRS_0
None supported, ARMv7-M unused.
0x1 : SVC_INSTRS_1
Adds support for the SVC instruction.
End of enumeration elements list.
SYNCHPRIM_INSTRS : Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives
bits : 12 - 15 (4 bit)
access : read-only
TABBRANCH_INSTRS : Indicates the supported Table Branch instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : TABBRANCH_INSTRS_0
None supported, ARMv7-M unused.
0x1 : TABBRANCH_INSTRS_1
Adds support for the TBB and TBH instructions.
End of enumeration elements list.
THUMBCOPY_INSTRS : Indicates the supported non flag-setting MOV instructions
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : THUMBCOPY_INSTRS_0
None supported, ARMv7-M unused.
0x1 : THUMBCOPY_INSTRS_1
Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register.
End of enumeration elements list.
TRUENOP_INSTRS : Indicates the supported non flag-setting MOV instructions
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : TRUENOP_INSTRS_0
None supported, ARMv7-M unused.
0x1 : TRUENOP_INSTRS_1
Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register.
End of enumeration elements list.
Instruction Set Attributes Register 4
address_offset : 0xD70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UNPRIV_INSTRS : Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix.
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : UNPRIV_INSTRS_0
None supported, ARMv7-M unused.
0x1 : UNPRIV_INSTRS_1
Adds support for the LDRBT, LDRT, STRBT, and STRT instructions.
0x2 : UNPRIV_INSTRS_2
As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions.
End of enumeration elements list.
WITHSHIFTS_INSTRS : Indicates the support for instructions with shifts
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : WITHSHIFTS_INSTRS_0
Nonzero shifts supported only in MOV and shift instructions.
0x1 : WITHSHIFTS_INSTRS_1
Adds support for shifts of loads and stores over the range LSL 0-3.
0x3 : WITHSHIFTS_INSTRS_3
As for 1, and adds support for other constant shift options, on loads, stores, and other instructions.
0x4 : WITHSHIFTS_INSTRS_4
ARMv7-M unused.
End of enumeration elements list.
WRITEBACK_INSTRS : Indicates the support for Writeback addressing modes
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : WRITEBACK_INSTRS_0
Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused.
0x1 : WRITEBACK_INSTRS_1
Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture.
End of enumeration elements list.
BARRIER_INSTRS : Indicates the supported Barrier instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : BARRIER_INSTRS_0
None supported, ARMv7-M unused.
0x1 : BARRIER_INSTRS_1
Adds support for the DMB, DSB, and ISB barrier instructions.
End of enumeration elements list.
SYNCHPRIM_INSTRS_FRAC : Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives
bits : 20 - 23 (4 bit)
access : read-only
PSR_M_INSTRS : Indicates the supported M profile instructions to modify the PSRs
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : PSR_M_INSTRS_0
None supported, ARMv7-M unused.
0x1 : PSR_M_INSTRS_1
Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs.
End of enumeration elements list.
Cache Level ID register
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CL1 : Indicate the type of cache implemented at level 1.
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : CL1_0
No cache
0x1 : CL1_1
Instruction cache only
0x2 : CL1_2
Data cache only
0x3 : CL1_3
Separate instruction and data caches
0x4 : CL1_4
Unified cache
End of enumeration elements list.
CL2 : Indicate the type of cache implemented at level 2.
bits : 3 - 5 (3 bit)
access : read-only
Enumeration:
0 : CL2_0
No cache
0x1 : CL2_1
Instruction cache only
0x2 : CL2_2
Data cache only
0x3 : CL2_3
Separate instruction and data caches
0x4 : CL2_4
Unified cache
End of enumeration elements list.
CL3 : Indicate the type of cache implemented at level 3.
bits : 6 - 8 (3 bit)
access : read-only
Enumeration:
0 : CL3_0
No cache
0x1 : CL3_1
Instruction cache only
0x2 : CL3_2
Data cache only
0x3 : CL3_3
Separate instruction and data caches
0x4 : CL3_4
Unified cache
End of enumeration elements list.
CL4 : Indicate the type of cache implemented at level 4.
bits : 9 - 11 (3 bit)
access : read-only
Enumeration:
0 : CL4_0
No cache
0x1 : CL4_1
Instruction cache only
0x2 : CL4_2
Data cache only
0x3 : CL4_3
Separate instruction and data caches
0x4 : CL4_4
Unified cache
End of enumeration elements list.
CL5 : Indicate the type of cache implemented at level 5.
bits : 12 - 14 (3 bit)
access : read-only
Enumeration:
0 : CL5_0
No cache
0x1 : CL5_1
Instruction cache only
0x2 : CL5_2
Data cache only
0x3 : CL5_3
Separate instruction and data caches
0x4 : CL5_4
Unified cache
End of enumeration elements list.
CL6 : Indicate the type of cache implemented at level 6.
bits : 15 - 17 (3 bit)
access : read-only
Enumeration:
0 : CL6_0
No cache
0x1 : CL6_1
Instruction cache only
0x2 : CL6_2
Data cache only
0x3 : CL6_3
Separate instruction and data caches
0x4 : CL6_4
Unified cache
End of enumeration elements list.
CL7 : Indicate the type of cache implemented at level 7.
bits : 18 - 20 (3 bit)
access : read-only
Enumeration:
0 : CL7_0
No cache
0x1 : CL7_1
Instruction cache only
0x2 : CL7_2
Data cache only
0x3 : CL7_3
Separate instruction and data caches
0x4 : CL7_4
Unified cache
End of enumeration elements list.
LOUIS : Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ.
bits : 21 - 23 (3 bit)
access : read-only
Enumeration:
0 : LOUIS_0
0
0x1 : LOUIS_1
1
0x2 : LOUIS_2
2
0x3 : LOUIS_3
3
0x4 : LOUIS_4
4
0x5 : LOUIS_5
5
0x6 : LOUIS_6
6
0x7 : LOUIS_7
7
End of enumeration elements list.
LOC : Level of Coherency for the cache hierarchy
bits : 24 - 26 (3 bit)
access : read-only
Enumeration:
0 : LOC_0
0
0x1 : LOC_1
1
0x2 : LOC_2
2
0x3 : LOC_3
3
0x4 : LOC_4
4
0x5 : LOC_5
5
0x6 : LOC_6
6
0x7 : LOC_7
7
End of enumeration elements list.
LOU : Level of Unification for the cache hierarchy
bits : 27 - 29 (3 bit)
access : read-only
Enumeration:
0 : LOU_0
0
0x1 : LOU_1
1
0x2 : LOU_2
2
0x3 : LOU_3
3
0x4 : LOU_4
4
0x5 : LOU_5
5
0x6 : LOU_6
6
0x7 : LOU_7
7
End of enumeration elements list.
Cache Type register
address_offset : 0xD7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMINLINE : Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor.
bits : 0 - 3 (4 bit)
access : read-only
DMINLINE : Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor.
bits : 16 - 19 (4 bit)
access : read-only
ERG : Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words.
bits : 20 - 23 (4 bit)
access : read-only
CWG : Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words.
bits : 24 - 27 (4 bit)
access : read-only
FORMAT : Indicates the implemented CTR format.
bits : 29 - 31 (3 bit)
access : read-only
Enumeration:
0x4 : FORMAT_4
ARMv7 format.
End of enumeration elements list.
Cache Size ID Register
address_offset : 0xD80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LINESIZE : (Log2(Number of words in cache line)) - 2.
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : LINESIZE_0
The line length of 4 words.
0x1 : LINESIZE_1
The line length of 8 words.
0x2 : LINESIZE_2
The line length of 16 words.
0x3 : LINESIZE_3
The line length of 32 words.
0x4 : LINESIZE_4
The line length of 64 words.
0x5 : LINESIZE_5
The line length of 128 words.
0x6 : LINESIZE_6
The line length of 256 words.
0x7 : LINESIZE_7
The line length of 512 words.
End of enumeration elements list.
ASSOCIATIVITY : (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.
bits : 3 - 12 (10 bit)
access : read-only
NUMSETS : (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.
bits : 13 - 27 (15 bit)
access : read-only
WA : Indicates whether the cache level supports write-allocation
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : WA_0
Feature not supported
0x1 : WA_1
Feature supported
End of enumeration elements list.
RA : Indicates whether the cache level supports read-allocation
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RA_0
Feature not supported
0x1 : RA_1
Feature supported
End of enumeration elements list.
WB : Indicates whether the cache level supports write-back
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : WB_0
Feature not supported
0x1 : WB_1
Feature supported
End of enumeration elements list.
WT : Indicates whether the cache level supports write-through
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WT_0
Feature not supported
0x1 : WT_1
Feature supported
End of enumeration elements list.
Cache Size Selection Register
address_offset : 0xD84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IND : Instruction not data bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : IND_0
Data or unified cache.
0x1 : IND_1
Instruction cache.
End of enumeration elements list.
LEVEL : Cache level of required cache
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0 : LEVEL_0
Level 1 cache.
0x1 : LEVEL_1
Level 2 cache.
0x2 : LEVEL_2
Level 3 cache.
0x3 : LEVEL_3
Level 4 cache.
0x4 : LEVEL_4
Level 5 cache.
0x5 : LEVEL_5
Level 6 cache.
0x6 : LEVEL_6
Level 7 cache.
End of enumeration elements list.
Coprocessor Access Control Register
address_offset : 0xD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP0 : Access privileges for coprocessor 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : CP0_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP0_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP0_3
Full access.
End of enumeration elements list.
CP1 : Access privileges for coprocessor 1.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : CP1_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP1_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP1_3
Full access.
End of enumeration elements list.
CP2 : Access privileges for coprocessor 2.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : CP2_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP2_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP2_3
Full access.
End of enumeration elements list.
CP3 : Access privileges for coprocessor 3.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : CP3_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP3_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP3_3
Full access.
End of enumeration elements list.
CP4 : Access privileges for coprocessor 4.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : CP4_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP4_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP4_3
Full access.
End of enumeration elements list.
CP5 : Access privileges for coprocessor 5.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : CP5_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP5_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP5_3
Full access.
End of enumeration elements list.
CP6 : Access privileges for coprocessor 6.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : CP6_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP6_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP6_3
Full access.
End of enumeration elements list.
CP7 : Access privileges for coprocessor 7.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : CP7_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP7_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP7_3
Full access.
End of enumeration elements list.
CP10 : Access privileges for coprocessor 10.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : CP10_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP10_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP10_3
Full access.
End of enumeration elements list.
CP11 : Access privileges for coprocessor 11.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : CP11_0
Access denied. Any attempted access generates a NOCP UsageFault.
0x1 : CP11_1
Privileged access only. An unprivileged access generates a NOCP UsageFault.
0x3 : CP11_3
Full access.
End of enumeration elements list.
Instruction cache invalidate all to Point of Unification (PoU)
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTID : Indicates the interrupt to be triggered
bits : 0 - 8 (9 bit)
access : write-only
Instruction cache invalidate all to Point of Unification (PoU)
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ICIALLU : I-cache invalidate all to PoU
bits : 0 - 31 (32 bit)
access : write-only
Instruction cache invalidate by address to PoU
address_offset : 0xF58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ICIMVAU : I-cache invalidate by MVA to PoU
bits : 0 - 31 (32 bit)
access : write-only
Data cache invalidate by address to Point of Coherency (PoC)
address_offset : 0xF5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCIMVAC : D-cache invalidate by MVA to PoC
bits : 0 - 31 (32 bit)
access : write-only
Data cache invalidate by set/way
address_offset : 0xF60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCISW : D-cache invalidate by set-way
bits : 0 - 31 (32 bit)
access : write-only
Data cache by address to PoU
address_offset : 0xF64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCCMVAU : D-cache clean by MVA to PoU
bits : 0 - 31 (32 bit)
access : write-only
Data cache clean by address to PoC
address_offset : 0xF68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCCMVAC : D-cache clean by MVA to PoC
bits : 0 - 31 (32 bit)
access : write-only
Data cache clean by set/way
address_offset : 0xF6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCCSW : D-cache clean by set-way
bits : 0 - 31 (32 bit)
access : write-only
Data cache clean and invalidate by address to PoC
address_offset : 0xF70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCCIMVAC : D-cache clean and invalidate by MVA to PoC
bits : 0 - 31 (32 bit)
access : write-only
Data cache clean and invalidate by set/way
address_offset : 0xF74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCCISW : D-cache clean and invalidate by set-way
bits : 0 - 31 (32 bit)
access : write-only
Instruction Tightly-Coupled Memory Control Register
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : TCM enable. When a TCM is disabled all accesses are made to the AXIM interface.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_0
TCM disabled.
0x1 : EN_1
TCM enabled.
End of enumeration elements list.
RMW : Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RMW_0
RMW disabled.
0x1 : RMW_1
RMW enabled.
End of enumeration elements list.
RETEN : Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RETEN_0
Retry phase disabled.
0x1 : RETEN_1
Retry phase enabled.
End of enumeration elements list.
SZ : TCM size. Indicates the size of the relevant TCM.
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : SZ_0
No TCM implemented.
0x3 : SZ_3
4KB.
0x4 : SZ_4
8KB.
0x5 : SZ_5
16KB.
0x6 : SZ_6
32KB.
0x7 : SZ_7
64KB.
0x8 : SZ_8
128KB.
0x9 : SZ_9
256KB.
0xA : SZ_10
512KB.
0xB : SZ_11
1MB.
0xC : SZ_12
2MB.
0xD : SZ_13
4MB.
0xE : SZ_14
8MB.
0xF : SZ_15
16MB.
End of enumeration elements list.
Data Tightly-Coupled Memory Control Register
address_offset : 0xF94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : TCM enable. When a TCM is disabled all accesses are made to the AXIM interface.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_0
TCM disabled.
0x1 : EN_1
TCM enabled.
End of enumeration elements list.
RMW : Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RMW_0
RMW disabled.
0x1 : RMW_1
RMW enabled.
End of enumeration elements list.
RETEN : Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RETEN_0
Retry phase disabled.
0x1 : RETEN_1
Retry phase enabled.
End of enumeration elements list.
SZ : TCM size. Indicates the size of the relevant TCM.
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
0 : SZ_0
No TCM implemented.
0x3 : SZ_3
4KB.
0x4 : SZ_4
8KB.
0x5 : SZ_5
16KB.
0x6 : SZ_6
32KB.
0x7 : SZ_7
64KB.
0x8 : SZ_8
128KB.
0x9 : SZ_9
256KB.
0xA : SZ_10
512KB.
0xB : SZ_11
1MB.
0xC : SZ_12
2MB.
0xD : SZ_13
4MB.
0xE : SZ_14
8MB.
0xF : SZ_15
16MB.
End of enumeration elements list.
AHBP Control Register
address_offset : 0xF98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : AHBP enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_0
AHBP disabled. When disabled all accesses are made to the AXIM interface.
0x1 : EN_1
AHBP enabled.
End of enumeration elements list.
SZ : AHBP size.
bits : 1 - 3 (3 bit)
access : read-only
Enumeration:
0 : SZ_0
0MB. AHBP disabled.
0x1 : SZ_1
64MB.
0x2 : SZ_2
128MB.
0x3 : SZ_3
256MB.
0x4 : SZ_4
512MB.
End of enumeration elements list.
L1 Cache Control Register
address_offset : 0xF9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIWT : Shared cacheable-is-WT for data cache. Enables limited cache coherency usage.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SIWT_0
Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory.
0x1 : SIWT_1
Normal Cacheable shared locations are treated as Write-Through.
End of enumeration elements list.
ECCDIS : Enables ECC in the instruction and data cache.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ECCDIS_0
Enables ECC in the instruction and data cache.
0x1 : ECCDIS_1
Disables ECC in the instruction and data cache.
End of enumeration elements list.
FORCEWT : Enables Force Write-Through in the data cache.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FORCEWT_0
Disables Force Write-Through.
0x1 : FORCEWT_1
Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through.
End of enumeration elements list.
AHB Slave Control Register
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTL : AHBS prioritization control.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : CTL_0
AHBS access priority demoted. This is the reset value.
0x1 : CTL_1
Software access priority demoted.
0x2 : CTL_2
AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR[INITCOUNT] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR[TPRI].
0x3 : CTL_3
AHBSPRI signal has control of access priority.
End of enumeration elements list.
TPRI : Threshold execution priority for AHBS traffic demotion.
bits : 2 - 10 (9 bit)
access : read-write
INITCOUNT : Fairness counter initialization value.
bits : 11 - 15 (5 bit)
access : read-write
Auxiliary Bus Fault Status Register
address_offset : 0xFA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITCM : Asynchronous fault on ITCM interface.
bits : 0 - 0 (1 bit)
access : read-write
DTCM : Asynchronous fault on DTCM interface.
bits : 1 - 1 (1 bit)
access : read-write
AHBP : Asynchronous fault on AHBP interface.
bits : 2 - 2 (1 bit)
access : read-write
AXIM : Asynchronous fault on AXIM interface.
bits : 3 - 3 (1 bit)
access : read-write
EPPB : Asynchronous fault on EPPB interface.
bits : 4 - 4 (1 bit)
access : read-write
AXIMTYPE : Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : AXIMTYPE_0
OKAY.
0x1 : AXIMTYPE_1
EXOKAY.
0x2 : AXIMTYPE_2
SLVERR.
0x3 : AXIMTYPE_3
DECERR.
End of enumeration elements list.
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