Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x628 byte (0x0)
mem_usage : registers
protection : not protected
Receive Descriptor Active Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAR : Receive Descriptor Active
bits : 24 - 24 (1 bit)
access : read-write
Receive Interrupt Coalescing Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICTT : Interrupt coalescing timer threshold
bits : 0 - 15 (16 bit)
access : read-write
ICFT : Interrupt coalescing frame count threshold
bits : 20 - 27 (8 bit)
access : read-write
ICCS : Interrupt Coalescing Timer Clock Source Select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ICCS_0
Use MII/GMII TX clocks.
0x1 : ICCS_1
Use ENET system clock.
End of enumeration elements list.
ICEN : Interrupt Coalescing Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ICEN_0
Disable Interrupt coalescing.
0x1 : ICEN_1
Enable Interrupt coalescing.
End of enumeration elements list.
Descriptor Individual Upper Address Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IADDR1 : Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Individual Lower Address Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IADDR2 : Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Group Upper Address Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GADDR1 : Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address
bits : 0 - 31 (32 bit)
access : read-write
Timer Control Status Register
address_offset : 0x1220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRE : Timer DMA Request Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDRE_0
DMA request is disabled
0x1 : TDRE_1
DMA request is enabled
End of enumeration elements list.
TMODE : Timer Mode
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : TMODE_0
Timer Channel is disabled.
0x1 : TMODE_1
Timer Channel is configured for Input Capture on rising edge.
0x2 : TMODE_2
Timer Channel is configured for Input Capture on falling edge.
0x3 : TMODE_3
Timer Channel is configured for Input Capture on both edges.
0x4 : TMODE_4
Timer Channel is configured for Output Compare - software only.
0x5 : TMODE_5
Timer Channel is configured for Output Compare - toggle output on compare.
0x6 : TMODE_6
Timer Channel is configured for Output Compare - clear output on compare.
0x7 : TMODE_7
Timer Channel is configured for Output Compare - set output on compare.
#10x1 : TMODE_9
Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
0xA : TMODE_10
Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
0xE : TMODE_14
Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
0xF : TMODE_15
Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
End of enumeration elements list.
TIE : Timer Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TIE_0
Interrupt is disabled
0x1 : TIE_1
Interrupt is enabled
End of enumeration elements list.
TF : Timer Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TF_0
Input Capture or Output Compare has not occurred.
0x1 : TF_1
Input Capture or Output Compare has occurred.
End of enumeration elements list.
TPWC : Timer PulseWidth Control
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : TPWC_0
Pulse width is one 1588-clock cycle.
0x1 : TPWC_1
Pulse width is two 1588-clock cycles.
0x2 : TPWC_2
Pulse width is three 1588-clock cycles.
0x3 : TPWC_3
Pulse width is four 1588-clock cycles.
0x1F : TPWC_31
Pulse width is 32 1588-clock cycles.
End of enumeration elements list.
Timer Compare Capture Register
address_offset : 0x122C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCC : Timer Capture Compare
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Group Lower Address Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GADDR2 : Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address
bits : 0 - 31 (32 bit)
access : read-write
Transmit Descriptor Active Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDAR : Transmit Descriptor Active
bits : 24 - 24 (1 bit)
access : read-write
Transmit FIFO Watermark Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFWR : Transmit FIFO Write
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : TFWR_0
64 bytes written.
0x1 : TFWR_1
64 bytes written.
0x2 : TFWR_2
128 bytes written.
0x3 : TFWR_3
192 bytes written.
0x1F : TFWR_31
1984 bytes written.
End of enumeration elements list.
STRFWD : Store And Forward Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : STRFWD_0
Reset. The transmission start threshold is programmed in TFWR[TFWR].
0x1 : STRFWD_1
Enabled.
End of enumeration elements list.
Receive Descriptor Ring Start Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R_DES_START : Pointer to the beginning of the receive buffer descriptor queue.
bits : 3 - 31 (29 bit)
access : read-write
Timer Control Status Register
address_offset : 0x1838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRE : Timer DMA Request Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDRE_0
DMA request is disabled
0x1 : TDRE_1
DMA request is enabled
End of enumeration elements list.
TMODE : Timer Mode
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : TMODE_0
Timer Channel is disabled.
0x1 : TMODE_1
Timer Channel is configured for Input Capture on rising edge.
0x2 : TMODE_2
Timer Channel is configured for Input Capture on falling edge.
0x3 : TMODE_3
Timer Channel is configured for Input Capture on both edges.
0x4 : TMODE_4
Timer Channel is configured for Output Compare - software only.
0x5 : TMODE_5
Timer Channel is configured for Output Compare - toggle output on compare.
0x6 : TMODE_6
Timer Channel is configured for Output Compare - clear output on compare.
0x7 : TMODE_7
Timer Channel is configured for Output Compare - set output on compare.
#10x1 : TMODE_9
Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
0xA : TMODE_10
Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
0xE : TMODE_14
Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
0xF : TMODE_15
Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
End of enumeration elements list.
TIE : Timer Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TIE_0
Interrupt is disabled
0x1 : TIE_1
Interrupt is enabled
End of enumeration elements list.
TF : Timer Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TF_0
Input Capture or Output Compare has not occurred.
0x1 : TF_1
Input Capture or Output Compare has occurred.
End of enumeration elements list.
TPWC : Timer PulseWidth Control
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : TPWC_0
Pulse width is one 1588-clock cycle.
0x1 : TPWC_1
Pulse width is two 1588-clock cycles.
0x2 : TPWC_2
Pulse width is three 1588-clock cycles.
0x3 : TPWC_3
Pulse width is four 1588-clock cycles.
0x1F : TPWC_31
Pulse width is 32 1588-clock cycles.
End of enumeration elements list.
Transmit Buffer Descriptor Ring Start Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_DES_START : Pointer to the beginning of the transmit buffer descriptor queue.
bits : 3 - 31 (29 bit)
access : read-write
Timer Compare Capture Register
address_offset : 0x1848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCC : Timer Capture Compare
bits : 0 - 31 (32 bit)
access : read-write
Maximum Receive Buffer Size Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R_BUF_SIZE : Receive buffer size in bytes
bits : 4 - 13 (10 bit)
access : read-write
Receive FIFO Section Full Threshold
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_SECTION_FULL : Value Of Receive FIFO Section Full Threshold
bits : 0 - 7 (8 bit)
access : read-write
Receive FIFO Section Empty Threshold
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_SECTION_EMPTY : Value Of The Receive FIFO Section Empty Threshold
bits : 0 - 7 (8 bit)
access : read-write
STAT_SECTION_EMPTY : RX Status FIFO Section Empty Threshold
bits : 16 - 20 (5 bit)
access : read-write
Receive FIFO Almost Empty Threshold
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_ALMOST_EMPTY : Value Of The Receive FIFO Almost Empty Threshold
bits : 0 - 7 (8 bit)
access : read-write
Receive FIFO Almost Full Threshold
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_ALMOST_FULL : Value Of The Receive FIFO Almost Full Threshold
bits : 0 - 7 (8 bit)
access : read-write
Transmit FIFO Section Empty Threshold
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_SECTION_EMPTY : Value Of The Transmit FIFO Section Empty Threshold
bits : 0 - 7 (8 bit)
access : read-write
Transmit FIFO Almost Empty Threshold
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_ALMOST_EMPTY : Value of Transmit FIFO Almost Empty Threshold
bits : 0 - 7 (8 bit)
access : read-write
Transmit FIFO Almost Full Threshold
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_ALMOST_FULL : Value Of The Transmit FIFO Almost Full Threshold
bits : 0 - 7 (8 bit)
access : read-write
Transmit Inter-Packet Gap
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPG : Transmit Inter-Packet Gap
bits : 0 - 4 (5 bit)
access : read-write
Frame Truncation Length
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRUNC_FL : Frame Truncation Length
bits : 0 - 13 (14 bit)
access : read-write
Transmit Accelerator Function Configuration
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFT16 : TX FIFO Shift-16
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SHIFT16_0
Disabled.
0x1 : SHIFT16_1
Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
End of enumeration elements list.
IPCHK : Enables insertion of IP header checksum.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : IPCHK_0
Checksum is not inserted.
0x1 : IPCHK_1
If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
End of enumeration elements list.
PROCHK : Enables insertion of protocol checksum.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PROCHK_0
Checksum not inserted.
0x1 : PROCHK_1
If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
End of enumeration elements list.
Receive Accelerator Function Configuration
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADREM : Enable Padding Removal For Short IP Frames
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PADREM_0
Padding not removed.
0x1 : PADREM_1
Any bytes following the IP payload section of the frame are removed from the frame.
End of enumeration elements list.
IPDIS : Enable Discard Of Frames With Wrong IPv4 Header Checksum
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : IPDIS_0
Frames with wrong IPv4 header checksum are not discarded.
0x1 : IPDIS_1
If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
End of enumeration elements list.
PRODIS : Enable Discard Of Frames With Wrong Protocol Checksum
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PRODIS_0
Frames with wrong checksum are not discarded.
0x1 : PRODIS_1
If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
End of enumeration elements list.
LINEDIS : Enable Discard Of Frames With MAC Layer Errors
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : LINEDIS_0
Frames with errors are not discarded.
0x1 : LINEDIS_1
Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
End of enumeration elements list.
SHIFT16 : RX FIFO Shift-16
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SHIFT16_0
Disabled.
0x1 : SHIFT16_1
Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
End of enumeration elements list.
Timer Control Status Register
address_offset : 0x1E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRE : Timer DMA Request Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDRE_0
DMA request is disabled
0x1 : TDRE_1
DMA request is enabled
End of enumeration elements list.
TMODE : Timer Mode
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : TMODE_0
Timer Channel is disabled.
0x1 : TMODE_1
Timer Channel is configured for Input Capture on rising edge.
0x2 : TMODE_2
Timer Channel is configured for Input Capture on falling edge.
0x3 : TMODE_3
Timer Channel is configured for Input Capture on both edges.
0x4 : TMODE_4
Timer Channel is configured for Output Compare - software only.
0x5 : TMODE_5
Timer Channel is configured for Output Compare - toggle output on compare.
0x6 : TMODE_6
Timer Channel is configured for Output Compare - clear output on compare.
0x7 : TMODE_7
Timer Channel is configured for Output Compare - set output on compare.
#10x1 : TMODE_9
Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
0xA : TMODE_10
Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
0xE : TMODE_14
Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
0xF : TMODE_15
Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
End of enumeration elements list.
TIE : Timer Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TIE_0
Interrupt is disabled
0x1 : TIE_1
Interrupt is enabled
End of enumeration elements list.
TF : Timer Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TF_0
Input Capture or Output Compare has not occurred.
0x1 : TF_1
Input Capture or Output Compare has occurred.
End of enumeration elements list.
TPWC : Timer PulseWidth Control
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : TPWC_0
Pulse width is one 1588-clock cycle.
0x1 : TPWC_1
Pulse width is two 1588-clock cycles.
0x2 : TPWC_2
Pulse width is three 1588-clock cycles.
0x3 : TPWC_3
Pulse width is four 1588-clock cycles.
0x1F : TPWC_31
Pulse width is 32 1588-clock cycles.
End of enumeration elements list.
Timer Compare Capture Register
address_offset : 0x1E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCC : Timer Capture Compare
bits : 0 - 31 (32 bit)
access : read-write
Reserved Statistic Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Tx Packet Count Statistic Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Packet count
bits : 0 - 15 (16 bit)
access : read-only
Tx Broadcast Packets Statistic Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Broadcast packets
bits : 0 - 15 (16 bit)
access : read-only
Tx Multicast Packets Statistic Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Multicast packets
bits : 0 - 15 (16 bit)
access : read-only
Tx Packets with CRC/Align Error Statistic Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Packets with CRC/align error
bits : 0 - 15 (16 bit)
access : read-only
Tx Packets Less Than Bytes and Good CRC Statistic Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of transmit packets less than 64 bytes with good CRC
bits : 0 - 15 (16 bit)
access : read-only
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of transmit packets greater than MAX_FL bytes with good CRC
bits : 0 - 15 (16 bit)
access : read-only
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of packets less than 64 bytes with bad CRC
bits : 0 - 15 (16 bit)
access : read-only
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of transmit packets greater than MAX_FL bytes and bad CRC
bits : 0 - 15 (16 bit)
access : read-only
Tx Collision Count Statistic Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of transmit collisions
bits : 0 - 15 (16 bit)
access : read-only
Tx 64-Byte Packets Statistic Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of 64-byte transmit packets
bits : 0 - 15 (16 bit)
access : read-only
Tx 65- to 127-byte Packets Statistic Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of 65- to 127-byte transmit packets
bits : 0 - 15 (16 bit)
access : read-only
Tx 128- to 255-byte Packets Statistic Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of 128- to 255-byte transmit packets
bits : 0 - 15 (16 bit)
access : read-only
Tx 256- to 511-byte Packets Statistic Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of 256- to 511-byte transmit packets
bits : 0 - 15 (16 bit)
access : read-only
Tx 512- to 1023-byte Packets Statistic Register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of 512- to 1023-byte transmit packets
bits : 0 - 15 (16 bit)
access : read-only
Tx 1024- to 2047-byte Packets Statistic Register
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of 1024- to 2047-byte transmit packets
bits : 0 - 15 (16 bit)
access : read-only
Ethernet Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET : Ethernet MAC Reset
bits : 0 - 0 (1 bit)
access : read-write
ETHEREN : Ethernet Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ETHEREN_0
Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
0x1 : ETHEREN_1
MAC is enabled, and reception and transmission are possible.
End of enumeration elements list.
MAGICEN : Magic Packet Detection Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MAGICEN_0
Magic detection logic disabled.
0x1 : MAGICEN_1
The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
End of enumeration elements list.
SLEEP : Sleep Mode Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SLEEP_0
Normal operating mode.
0x1 : SLEEP_1
Sleep mode.
End of enumeration elements list.
EN1588 : EN1588 Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EN1588_0
Legacy FEC buffer descriptors and functions enabled.
0x1 : EN1588_1
Enhanced frame time-stamping functions enabled.
End of enumeration elements list.
DBGEN : Debug Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DBGEN_0
MAC continues operation in debug mode.
0x1 : DBGEN_1
MAC enters hardware freeze mode when the processor is in debug mode.
End of enumeration elements list.
DBSWP : Descriptor Byte Swapping Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DBSWP_0
The buffer descriptor bytes are not swapped to support big-endian devices.
0x1 : DBSWP_1
The buffer descriptor bytes are swapped to support little-endian devices.
End of enumeration elements list.
Tx Packets Greater Than 2048 Bytes Statistic Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTS : Number of transmit packets greater than 2048 bytes
bits : 0 - 15 (16 bit)
access : read-only
Tx Octets Statistic Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXOCTS : Number of transmit octets
bits : 0 - 31 (32 bit)
access : read-only
Reserved Statistic Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Frames Transmitted OK Statistic Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames transmitted OK
bits : 0 - 15 (16 bit)
access : read-only
Frames Transmitted with Single Collision Statistic Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames transmitted with one collision
bits : 0 - 15 (16 bit)
access : read-only
Frames Transmitted with Multiple Collisions Statistic Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames transmitted with multiple collisions
bits : 0 - 15 (16 bit)
access : read-only
Frames Transmitted after Deferral Delay Statistic Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames transmitted with deferral delay
bits : 0 - 15 (16 bit)
access : read-only
Frames Transmitted with Late Collision Statistic Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames transmitted with late collision
bits : 0 - 15 (16 bit)
access : read-only
Frames Transmitted with Excessive Collisions Statistic Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames transmitted with excessive collisions
bits : 0 - 15 (16 bit)
access : read-only
Frames Transmitted with Tx FIFO Underrun Statistic Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames transmitted with transmit FIFO underrun
bits : 0 - 15 (16 bit)
access : read-only
Frames Transmitted with Carrier Sense Error Statistic Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames transmitted with carrier sense error
bits : 0 - 15 (16 bit)
access : read-only
Reserved Statistic Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : This read-only field is reserved and always has the value 0
bits : 0 - 15 (16 bit)
access : read-only
Flow Control Pause Frames Transmitted Statistic Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of flow-control pause frames transmitted
bits : 0 - 15 (16 bit)
access : read-only
Octet Count for Frames Transmitted w/o Error Statistic Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).
bits : 0 - 31 (32 bit)
access : read-only
Rx Packet Count Statistic Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of packets received
bits : 0 - 15 (16 bit)
access : read-only
Rx Broadcast Packets Statistic Register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of receive broadcast packets
bits : 0 - 15 (16 bit)
access : read-only
Rx Multicast Packets Statistic Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of receive multicast packets
bits : 0 - 15 (16 bit)
access : read-only
Rx Packets with CRC/Align Error Statistic Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of receive packets with CRC or align error
bits : 0 - 15 (16 bit)
access : read-only
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of receive packets with less than 64 bytes and good CRC
bits : 0 - 15 (16 bit)
access : read-only
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of receive packets greater than MAX_FL and good CRC
bits : 0 - 15 (16 bit)
access : read-only
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of receive packets with less than 64 bytes and bad CRC
bits : 0 - 15 (16 bit)
access : read-only
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of receive packets greater than MAX_FL and bad CRC
bits : 0 - 15 (16 bit)
access : read-only
Reserved Statistic Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Rx 64-Byte Packets Statistic Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of 64-byte receive packets
bits : 0 - 15 (16 bit)
access : read-only
Rx 65- to 127-Byte Packets Statistic Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of 65- to 127-byte recieve packets
bits : 0 - 15 (16 bit)
access : read-only
Rx 128- to 255-Byte Packets Statistic Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of 128- to 255-byte recieve packets
bits : 0 - 15 (16 bit)
access : read-only
Rx 256- to 511-Byte Packets Statistic Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of 256- to 511-byte recieve packets
bits : 0 - 15 (16 bit)
access : read-only
Rx 512- to 1023-Byte Packets Statistic Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of 512- to 1023-byte recieve packets
bits : 0 - 15 (16 bit)
access : read-only
Rx 1024- to 2047-Byte Packets Statistic Register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of 1024- to 2047-byte recieve packets
bits : 0 - 15 (16 bit)
access : read-only
Rx Packets Greater than 2048 Bytes Statistic Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of greater-than-2048-byte recieve packets
bits : 0 - 15 (16 bit)
access : read-only
Rx Octets Statistic Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of receive octets
bits : 0 - 31 (32 bit)
access : read-only
Frames not Counted Correctly Statistic Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Frame count
bits : 0 - 15 (16 bit)
access : read-only
Frames Received OK Statistic Register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames received OK
bits : 0 - 15 (16 bit)
access : read-only
Frames Received with CRC Error Statistic Register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames received with CRC error
bits : 0 - 15 (16 bit)
access : read-only
Frames Received with Alignment Error Statistic Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of frames received with alignment error
bits : 0 - 15 (16 bit)
access : read-only
Receive FIFO Overflow Count Statistic Register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Receive FIFO overflow count
bits : 0 - 15 (16 bit)
access : read-only
Flow Control Pause Frames Received Statistic Register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of flow-control pause frames received
bits : 0 - 15 (16 bit)
access : read-only
Octet Count for Frames Received without Error Statistic Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Number of octets for frames received without error
bits : 0 - 31 (32 bit)
access : read-only
Interrupt Event Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS_TIMER : Timestamp Timer
bits : 15 - 15 (1 bit)
access : read-write
TS_AVAIL : Transmit Timestamp Available
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP : Node Wakeup Request Indication
bits : 17 - 17 (1 bit)
access : read-write
PLR : Payload Receive Error
bits : 18 - 18 (1 bit)
access : read-write
UN : Transmit FIFO Underrun
bits : 19 - 19 (1 bit)
access : read-write
RL : Collision Retry Limit
bits : 20 - 20 (1 bit)
access : read-write
LC : Late Collision
bits : 21 - 21 (1 bit)
access : read-write
EBERR : Ethernet Bus Error
bits : 22 - 22 (1 bit)
access : read-write
MII : MII Interrupt.
bits : 23 - 23 (1 bit)
access : read-write
RXB : Receive Buffer Interrupt
bits : 24 - 24 (1 bit)
access : read-write
RXF : Receive Frame Interrupt
bits : 25 - 25 (1 bit)
access : read-write
TXB : Transmit Buffer Interrupt
bits : 26 - 26 (1 bit)
access : read-write
TXF : Transmit Frame Interrupt
bits : 27 - 27 (1 bit)
access : read-write
GRA : Graceful Stop Complete
bits : 28 - 28 (1 bit)
access : read-write
BABT : Babbling Transmit Error
bits : 29 - 29 (1 bit)
access : read-write
BABR : Babbling Receive Error
bits : 30 - 30 (1 bit)
access : read-write
MII Management Frame Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Management Frame Data
bits : 0 - 15 (16 bit)
access : read-write
TA : Turn Around
bits : 16 - 17 (2 bit)
access : read-write
RA : Register Address
bits : 18 - 22 (5 bit)
access : read-write
PA : PHY Address
bits : 23 - 27 (5 bit)
access : read-write
OP : Operation Code
bits : 28 - 29 (2 bit)
access : read-write
ST : Start Of Frame Delimiter
bits : 30 - 31 (2 bit)
access : read-write
Adjustable Timer Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable Timer
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_0
The timer stops at the current value.
0x1 : EN_1
The timer starts incrementing.
End of enumeration elements list.
OFFEN : Enable One-Shot Offset Event
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : OFFEN_0
Disable.
0x1 : OFFEN_1
The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
End of enumeration elements list.
OFFRST : Reset Timer On Offset Event
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : OFFRST_0
The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
0x1 : OFFRST_1
If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
End of enumeration elements list.
PEREN : Enable Periodical Event
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PEREN_0
Disable.
0x1 : PEREN_1
A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
End of enumeration elements list.
PINPER : Enables event signal output assertion on period event
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPER_0
Disable.
0x1 : PINPER_1
Enable.
End of enumeration elements list.
RESTART : Reset Timer
bits : 9 - 9 (1 bit)
access : read-write
CAPTURE : Capture Timer Value
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : CAPTURE_0
No effect.
0x1 : CAPTURE_1
The current time is captured and can be read from the ATVR register.
End of enumeration elements list.
SLAVE : Enable Timer Slave Mode
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SLAVE_0
The timer is active and all configuration fields in this register are relevant.
0x1 : SLAVE_1
The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
End of enumeration elements list.
Timer Value Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATIME : A write sets the timer
bits : 0 - 31 (32 bit)
access : read-write
Timer Offset Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Offset value for one-shot event generation
bits : 0 - 31 (32 bit)
access : read-write
Timer Period Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Value for generating periodic events
bits : 0 - 31 (32 bit)
access : read-write
Timer Correction Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COR : Correction Counter Wrap-Around Value
bits : 0 - 30 (31 bit)
access : read-write
Time-Stamping Clock Period Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INC : Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
bits : 0 - 6 (7 bit)
access : read-write
INC_CORR : Correction Increment Value
bits : 8 - 14 (7 bit)
access : read-write
Timestamp of Last Transmitted Frame
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMESTAMP : Timestamp of the last frame transmitted by the core that had TxBD[TS] set
bits : 0 - 31 (32 bit)
access : read-only
MII Speed Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MII_SPEED : MII Speed
bits : 1 - 6 (6 bit)
access : read-write
DIS_PRE : Disable Preamble
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DIS_PRE_0
Preamble enabled.
0x1 : DIS_PRE_1
Preamble (32 ones) is not prepended to the MII management frame.
End of enumeration elements list.
HOLDTIME : Hold time On MDIO Output
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : HOLDTIME_0
1 internal module clock cycle
0x1 : HOLDTIME_1
2 internal module clock cycles
0x2 : HOLDTIME_2
3 internal module clock cycles
0x7 : HOLDTIME_7
8 internal module clock cycles
End of enumeration elements list.
Timer Global Status Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF0 : Copy Of Timer Flag For Channel 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TF0_0
Timer Flag for Channel 0 is clear
0x1 : TF0_1
Timer Flag for Channel 0 is set
End of enumeration elements list.
TF1 : Copy Of Timer Flag For Channel 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TF1_0
Timer Flag for Channel 1 is clear
0x1 : TF1_1
Timer Flag for Channel 1 is set
End of enumeration elements list.
TF2 : Copy Of Timer Flag For Channel 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TF2_0
Timer Flag for Channel 2 is clear
0x1 : TF2_1
Timer Flag for Channel 2 is set
End of enumeration elements list.
TF3 : Copy Of Timer Flag For Channel 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TF3_0
Timer Flag for Channel 3 is clear
0x1 : TF3_1
Timer Flag for Channel 3 is set
End of enumeration elements list.
MIB Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIB_CLEAR : MIB Clear
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : MIB_CLEAR_0
See note above.
0x1 : MIB_CLEAR_1
All statistics counters are reset to 0.
End of enumeration elements list.
MIB_IDLE : MIB Idle
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : MIB_IDLE_0
The MIB block is updating MIB counters.
0x1 : MIB_IDLE_1
The MIB block is not currently updating any MIB counters.
End of enumeration elements list.
MIB_DIS : Disable MIB Logic
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : MIB_DIS_0
MIB logic is enabled.
0x1 : MIB_DIS_1
MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
End of enumeration elements list.
Interrupt Mask Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS_TIMER : TS_TIMER Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-write
TS_AVAIL : TS_AVAIL Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP : WAKEUP Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-write
PLR : PLR Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-write
UN : UN Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-write
RL : RL Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-write
LC : LC Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-write
EBERR : EBERR Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-write
MII : MII Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-write
RXB : RXB Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-write
RXF : RXF Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-write
TXB : TXB Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TXB_0
The corresponding interrupt source is masked.
0x1 : TXB_1
The corresponding interrupt source is not masked.
End of enumeration elements list.
TXF : TXF Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : TXF_0
The corresponding interrupt source is masked.
0x1 : TXF_1
The corresponding interrupt source is not masked.
End of enumeration elements list.
GRA : GRA Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : GRA_0
The corresponding interrupt source is masked.
0x1 : GRA_1
The corresponding interrupt source is not masked.
End of enumeration elements list.
BABT : BABT Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : BABT_0
The corresponding interrupt source is masked.
0x1 : BABT_1
The corresponding interrupt source is not masked.
End of enumeration elements list.
BABR : BABR Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : BABR_0
The corresponding interrupt source is masked.
0x1 : BABR_1
The corresponding interrupt source is not masked.
End of enumeration elements list.
Receive Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOP : Internal Loopback
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOOP_0
Loopback disabled.
0x1 : LOOP_1
Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
End of enumeration elements list.
DRT : Disable Receive On Transmit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DRT_0
Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
0x1 : DRT_1
Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
End of enumeration elements list.
MII_MODE : Media Independent Interface Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x1 : MII_MODE_1
MII or RMII mode, as indicated by the RMII_MODE field.
End of enumeration elements list.
PROM : Promiscuous Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PROM_0
Disabled.
0x1 : PROM_1
Enabled.
End of enumeration elements list.
BC_REJ : Broadcast Frame Reject
bits : 4 - 4 (1 bit)
access : read-write
FCE : Flow Control Enable
bits : 5 - 5 (1 bit)
access : read-write
RMII_MODE : RMII Mode Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RMII_MODE_0
MAC configured for MII mode.
0x1 : RMII_MODE_1
MAC configured for RMII operation.
End of enumeration elements list.
RMII_10T : Enables 10-Mbit/s mode of the RMII .
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RMII_10T_0
100-Mbit/s operation.
0x1 : RMII_10T_1
10-Mbit/s operation.
End of enumeration elements list.
PADEN : Enable Frame Padding Remove On Receive
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : PADEN_0
No padding is removed on receive by the MAC.
0x1 : PADEN_1
Padding is removed from received frames.
End of enumeration elements list.
PAUFWD : Terminate/Forward Pause Frames
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PAUFWD_0
Pause frames are terminated and discarded in the MAC.
0x1 : PAUFWD_1
Pause frames are forwarded to the user application.
End of enumeration elements list.
CRCFWD : Terminate/Forward Received CRC
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : CRCFWD_0
The CRC field of received frames is transmitted to the user application.
0x1 : CRCFWD_1
The CRC field is stripped from the frame.
End of enumeration elements list.
CFEN : MAC Control Frame Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CFEN_0
MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
0x1 : CFEN_1
MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
End of enumeration elements list.
MAX_FL : Maximum Frame Length
bits : 16 - 29 (14 bit)
access : read-write
NLC : Payload Length Check Disable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NLC_0
The payload length check is disabled.
0x1 : NLC_1
The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
End of enumeration elements list.
GRS : Graceful Receive Stopped
bits : 31 - 31 (1 bit)
access : read-only
Timer Control Status Register
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRE : Timer DMA Request Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDRE_0
DMA request is disabled
0x1 : TDRE_1
DMA request is enabled
End of enumeration elements list.
TMODE : Timer Mode
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : TMODE_0
Timer Channel is disabled.
0x1 : TMODE_1
Timer Channel is configured for Input Capture on rising edge.
0x2 : TMODE_2
Timer Channel is configured for Input Capture on falling edge.
0x3 : TMODE_3
Timer Channel is configured for Input Capture on both edges.
0x4 : TMODE_4
Timer Channel is configured for Output Compare - software only.
0x5 : TMODE_5
Timer Channel is configured for Output Compare - toggle output on compare.
0x6 : TMODE_6
Timer Channel is configured for Output Compare - clear output on compare.
0x7 : TMODE_7
Timer Channel is configured for Output Compare - set output on compare.
#10x1 : TMODE_9
Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
0xA : TMODE_10
Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
0xE : TMODE_14
Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
0xF : TMODE_15
Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
End of enumeration elements list.
TIE : Timer Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TIE_0
Interrupt is disabled
0x1 : TIE_1
Interrupt is enabled
End of enumeration elements list.
TF : Timer Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TF_0
Input Capture or Output Compare has not occurred.
0x1 : TF_1
Input Capture or Output Compare has occurred.
End of enumeration elements list.
TPWC : Timer PulseWidth Control
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
0 : TPWC_0
Pulse width is one 1588-clock cycle.
0x1 : TPWC_1
Pulse width is two 1588-clock cycles.
0x2 : TPWC_2
Pulse width is three 1588-clock cycles.
0x3 : TPWC_3
Pulse width is four 1588-clock cycles.
0x1F : TPWC_31
Pulse width is 32 1588-clock cycles.
End of enumeration elements list.
Timer Compare Capture Register
address_offset : 0xC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCC : Timer Capture Compare
bits : 0 - 31 (32 bit)
access : read-write
Transmit Control Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTS : Graceful Transmit Stop
bits : 0 - 0 (1 bit)
access : read-write
FDEN : Full-Duplex Enable
bits : 2 - 2 (1 bit)
access : read-write
TFC_PAUSE : Transmit Frame Control Pause
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TFC_PAUSE_0
No PAUSE frame transmitted.
0x1 : TFC_PAUSE_1
The MAC stops transmission of data frames after the current transmission is complete.
End of enumeration elements list.
RFC_PAUSE : Receive Frame Control Pause
bits : 4 - 4 (1 bit)
access : read-only
ADDSEL : Source MAC Address Select On Transmit
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : ADDSEL_0
Node MAC address programmed on PADDR1/2 registers.
End of enumeration elements list.
ADDINS : Set MAC Address On Transmit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : ADDINS_0
The source MAC address is not modified by the MAC.
0x1 : ADDINS_1
The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
End of enumeration elements list.
CRCFWD : Forward Frame From Application With CRC
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : CRCFWD_0
TxBD[TC] controls whether the frame has a CRC from the application.
0x1 : CRCFWD_1
The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
End of enumeration elements list.
Physical Address Lower Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR1 : Pause Address
bits : 0 - 31 (32 bit)
access : read-write
Physical Address Upper Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Type Field In PAUSE Frames
bits : 0 - 15 (16 bit)
access : read-only
PADDR2 : Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames
bits : 16 - 31 (16 bit)
access : read-write
Opcode/Pause Duration Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAUSE_DUR : Pause Duration
bits : 0 - 15 (16 bit)
access : read-write
OPCODE : Opcode Field In PAUSE Frames
bits : 16 - 31 (16 bit)
access : read-only
Transmit Interrupt Coalescing Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICTT : Interrupt coalescing timer threshold
bits : 0 - 15 (16 bit)
access : read-write
ICFT : Interrupt coalescing frame count threshold
bits : 20 - 27 (8 bit)
access : read-write
ICCS : Interrupt Coalescing Timer Clock Source Select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ICCS_0
Use MII/GMII TX clocks.
0x1 : ICCS_1
Use ENET system clock.
End of enumeration elements list.
ICEN : Interrupt Coalescing Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ICEN_0
Disable Interrupt coalescing.
0x1 : ICEN_1
Enable Interrupt coalescing.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.