Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTENA : Master enable
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : MASTER_OFF
MASTER_OFF: Master is off (is not enabled). If MASTER_OFF is enabled, then the I3C module can only use slave mode.
0x1 : MASTER_ON
MASTER_ON: Master is on (is enabled). When used from start-up, this I3C module is master by default (the main master). The module will control the bus unless the master is handed off. If the master is handed off, then MSTENA must move to 2 after that happens. The handoff means emitting GETACCMST and if accepted, the module will emit a STOP and set the MSTENA bit to 2 (or 0).
0x2 : MASTER_CAPABLE
MASTER_CAPABLE: The I3C module is master-capable; however the module is operating as a slave now. When used from the start, the I3C module will start as a slave, but will be prepared to switch to master mode. To switch to master mode, the slave emits an Master Request (MR), or gets a GETACCMST CCC command and accepts it (to switch on the STOP).
End of enumeration elements list.
DISTO : Disable Timeout
bits : 3 - 3 (1 bit)
access : read-write
HKEEP : High-Keeper
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : NONE
NONE: Use PUR (Pull-Up Resistor). Hold SCL High.
0x1 : WIRED_IN
WIRED_IN: Wired-in High Keeper controls; use pin_HK (High Keeper) controls.
0x2 : PASSIVE_SDA
PASSIVE_SDA: Passive on SDA; can Hi-Z (high impedance) for Bus Free (IDLE) and hold.
0x3 : PASSIVE_ON_SDA_SCL
PASSIVE_ON_SDA_SCL: Passive on SDA and SCL; can Hi-Z (high impedance) both for Bus Free (IDLE), and can Hi-Z SDA for hold.
End of enumeration elements list.
ODSTOP : Open drain stop
bits : 6 - 6 (1 bit)
access : read-write
PPBAUD : Push-pull baud rate
bits : 8 - 11 (4 bit)
access : read-write
PPLOW : Push-Pull low
bits : 12 - 15 (4 bit)
access : read-write
ODBAUD : Open drain baud rate
bits : 16 - 23 (8 bit)
access : read-write
ODHPP : Open drain high push-pull
bits : 24 - 24 (1 bit)
access : read-write
SKEW : Skew
bits : 25 - 27 (3 bit)
access : read-write
I2CBAUD : I2C baud rate
bits : 28 - 31 (4 bit)
access : read-write
Slave Interrupt Set Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
MATCHED : Match interrupt enable
bits : 9 - 9 (1 bit)
access : read-write
STOP : Stop interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
RXPEND : Receive interrupt enable
bits : 11 - 11 (1 bit)
access : read-write
TXSEND : Transmit interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
DACHG : Dynamic address change interrupt enable
bits : 13 - 13 (1 bit)
access : read-write
CCC : Common Command Code (CCC) (that was not handled by I3C module) interrupt enable
bits : 14 - 14 (1 bit)
access : read-write
ERRWARN : Error/warning interrupt enable
bits : 15 - 15 (1 bit)
access : read-write
DDRMATCHED : Double Data Rate (DDR) interrupt enable
bits : 16 - 16 (1 bit)
access : read-write
CHANDLED : Common Command Code (CCC) (that was handled by I3C module) interrupt enable
bits : 17 - 17 (1 bit)
access : read-write
EVENT : Event interrupt enable
bits : 18 - 18 (1 bit)
access : read-write
Slave Interrupt Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : START interrupt enable clear
bits : 8 - 8 (1 bit)
access : read-write
MATCHED : MATCHED interrupt enable clear
bits : 9 - 9 (1 bit)
access : read-write
STOP : STOP interrupt enable clear
bits : 10 - 10 (1 bit)
access : read-write
RXPEND : RXPEND interrupt enable clear
bits : 11 - 11 (1 bit)
access : read-write
TXSEND : TXSEND interrupt enable clear
bits : 12 - 12 (1 bit)
access : read-write
DACHG : DACHG interrupt enable clear
bits : 13 - 13 (1 bit)
access : read-write
CCC : CCC interrupt enable clear
bits : 14 - 14 (1 bit)
access : read-write
ERRWARN : ERRWARN interrupt enable clear
bits : 15 - 15 (1 bit)
access : read-write
DDRMATCHED : DDRMATCHED interrupt enable clear
bits : 16 - 16 (1 bit)
access : read-write
CHANDLED : CHANDLED interrupt enable clear
bits : 17 - 17 (1 bit)
access : read-write
EVENT : EVENT interrupt enable clear
bits : 18 - 18 (1 bit)
access : read-write
Slave Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
START : START interrupt mask
bits : 8 - 8 (1 bit)
access : read-only
MATCHED : MATCHED interrupt mask
bits : 9 - 9 (1 bit)
access : read-only
STOP : STOP interrupt mask
bits : 10 - 10 (1 bit)
access : read-only
RXPEND : RXPEND interrupt mask
bits : 11 - 11 (1 bit)
access : read-only
TXSEND : TXSEND interrupt mask
bits : 12 - 12 (1 bit)
access : read-only
DACHG : DACHG interrupt mask
bits : 13 - 13 (1 bit)
access : read-only
CCC : CCC interrupt mask
bits : 14 - 14 (1 bit)
access : read-only
ERRWARN : ERRWARN interrupt mask
bits : 15 - 15 (1 bit)
access : read-only
DDRMATCHED : DDRMATCHED interrupt mask
bits : 16 - 16 (1 bit)
access : read-only
CHANDLED : CHANDLED interrupt mask
bits : 17 - 17 (1 bit)
access : read-only
EVENT : EVENT interrupt mask
bits : 18 - 18 (1 bit)
access : read-only
Slave Errors and Warnings Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ORUN : Overrun error
bits : 0 - 0 (1 bit)
access : read-write
URUN : Underrun error
bits : 1 - 1 (1 bit)
access : read-write
URUNNACK : Underrun and Not Acknowledged (NACKed) error
bits : 2 - 2 (1 bit)
access : read-write
TERM : Terminated error
bits : 3 - 3 (1 bit)
access : read-write
INVSTART : Invalid start error
bits : 4 - 4 (1 bit)
access : read-write
SPAR : SDR parity error
bits : 8 - 8 (1 bit)
access : read-write
HPAR : HDR parity error
bits : 9 - 9 (1 bit)
access : read-write
HCRC : HDR-DDR CRC error
bits : 10 - 10 (1 bit)
access : read-write
S0S1 : S0 or S1 error
bits : 11 - 11 (1 bit)
access : read-write
OREAD : Over-read error
bits : 16 - 16 (1 bit)
access : read-write
OWRITE : Over-write error
bits : 17 - 17 (1 bit)
access : read-write
Slave DMA Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAFB : DMA Read (From-bus) trigger
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NOT_USED
DMA not used
0x1 : ENABLE_ONE_FRAME
DMA is enabled for 1 frame
0x2 : ENABLE
DMA enable
End of enumeration elements list.
DMATB : DMA Write (To-bus) trigger
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : NOT_USED
NOT_USED: DMA is not used
0x1 : ENABLE_ONE_FRAME
ENABLE_ONE_FRAME: DMA is enabled for 1 Frame (ended by DMA or terminated). DMATB auto-clears on a STOP or START (see the Match START or STOP bit (SCONFIG.MATCHSS).
0x2 : ENABLE
ENABLE: DMA is enabled until turned off. Normally, ENABLE should only be used with Master Message mode.
End of enumeration elements list.
DMAWIDTH : Width of DMA operations
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : BYTE
BYTE
0x1 : BYTE_AGAIN
BYTE_AGAIN
0x2 : HALF_WORD
HALF_WORD: Half word (16 bits). This will make sure that 2 bytes are free/available in the FIFO.
End of enumeration elements list.
Slave Data Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLUSHTB : Flush the to-bus buffer/FIFO
bits : 0 - 0 (1 bit)
access : write-only
FLUSHFB : Flushes the from-bus buffer/FIFO
bits : 1 - 1 (1 bit)
access : write-only
UNLOCK : Unlock
bits : 3 - 3 (1 bit)
access : write-only
TXTRIG : Trigger level for TX FIFO emptiness
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TRIGGREMPTY
Trigger on empty
0x1 : TRIGGRONEFOURTH
Trigger on full or less
0x2 : TRIGGRONEHALF
Trigger on .5 full or less
0x3 : TRIGGRONELESS
Trigger on 1 less than full or less (Default)
End of enumeration elements list.
RXTRIG : Trigger level for RX FIFO fullness
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : TRIGGRNOTEMPTY
Trigger on not empty
0x1 : TRIGGRONEFOURTH
Trigger on or more full
0x2 : TRIGGRONEHALF
Trigger on .5 or more full
0x3 : TRIGGRTHREEFOURTHS
Trigger on 3/4 or more full
End of enumeration elements list.
TXCOUNT : Count of bytes in TX
bits : 16 - 20 (5 bit)
access : read-only
RXCOUNT : Count of bytes in RX
bits : 24 - 28 (5 bit)
access : read-only
TXFULL : TX is full
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : TXISNOTFULL
TX is not full
0x1 : TXISFULL
TX is full
End of enumeration elements list.
RXEMPTY : RX is empty
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : RXISNOTEMPTY
RX is not empty
0x1 : RXISEMPTY
RX is empty
End of enumeration elements list.
Slave Write Data Byte Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : The data byte to send to the master
bits : 0 - 7 (8 bit)
access : write-only
END : End
bits : 8 - 8 (1 bit)
access : write-only
END_ALSO : End also
bits : 16 - 16 (1 bit)
access : write-only
Slave Write Data Byte End
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : The data byte to send to the master
bits : 0 - 7 (8 bit)
access : write-only
Slave Write Data Half-word Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : The 1st byte to send to the master
bits : 0 - 7 (8 bit)
access : write-only
DATA1 : The 2nd byte to send to the master
bits : 8 - 15 (8 bit)
access : write-only
END : End of message
bits : 16 - 16 (1 bit)
access : write-only
Slave Write Data Half-word End Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : The 1st byte to send to the master
bits : 0 - 7 (8 bit)
access : write-only
DATA1 : The 2nd byte to send to the master
bits : 8 - 15 (8 bit)
access : write-only
Slave Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLVENA : Slave enable
bits : 0 - 0 (1 bit)
access : read-write
NACK : Not acknowledge
bits : 1 - 1 (1 bit)
access : read-write
MATCHSS : Match START or STOP
bits : 2 - 2 (1 bit)
access : read-write
S0IGNORE : S0/S1 errors ignore
bits : 3 - 3 (1 bit)
access : read-write
DDROK : Double Data Rate OK
bits : 4 - 4 (1 bit)
access : read-write
IDRAND : ID random
bits : 8 - 8 (1 bit)
access : read-write
OFFLINE : Offline
bits : 9 - 9 (1 bit)
access : read-write
BAMATCH : Bus available match
bits : 16 - 23 (8 bit)
access : read-write
SADDR : Static address
bits : 25 - 31 (7 bit)
access : read-write
Slave Read Data Byte Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Byte read from the master
bits : 0 - 7 (8 bit)
access : read-only
Slave Read Data Half-word Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LSB : The 1st byte read from the slave
bits : 0 - 7 (8 bit)
access : read-only
MSB : The 2nd byte read from the slave
bits : 8 - 15 (8 bit)
access : read-only
Slave Capabilities Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDENA : ID 48b handler
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : APPLICATION
APPLICATION: Application handles ID 48b
0x1 : HW
HW: Hardware handles ID 48b
0x2 : HW_BUT
HW_BUT: in hardware but the I3C module instance handles ID 48b.
0x3 : PARTNO
PARTNO: a part number register (PARTNO) handles ID 48b
End of enumeration elements list.
IDREG : ID register
bits : 2 - 5 (4 bit)
access : read-only
HDRSUPP : HDR support
bits : 6 - 8 (3 bit)
access : read-only
MASTER : Master
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : MASTERNOTSUPPORTED
MASTERNOTSUPPORTED: master capability is not supported.
0x1 : MASTERSUPPORTED
MASTERSUPPORTED: master capability is supported.
End of enumeration elements list.
SADDR : Static address
bits : 10 - 11 (2 bit)
access : read-only
Enumeration:
0 : NO_STATIC
NO_STATIC: No static address
0x1 : STATIC
STATIC: Static address is fixed in hardware
0x2 : HW_CONTROL
HW_CONTROL: Hardware controls the static address dynamically (for example, from the pin strap)
0x3 : CONFIG
CONFIG: SCONFIG register supplies the static address
End of enumeration elements list.
CCCHANDLE : Common Command Codes (CCC) handling
bits : 12 - 15 (4 bit)
access : read-only
IBI_MR_HJ : In-Band Interrupts, Master Requests, Hot Join events
bits : 16 - 20 (5 bit)
access : read-only
TIMECTRL : Time control
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : NO_TIME_CONTROL_TYPE
NO_TIME_CONTROL_TYPE: No time control is enabled
0x1 : ATLEAST1_TIME_CONTROL
ATLEAST1_TIME_CONTROL: at least one time-control type is supported
End of enumeration elements list.
EXTFIFO : External FIFO
bits : 23 - 25 (3 bit)
access : read-only
Enumeration:
0x1 : STD_EXT_FIFO
STD_EXT_FIFO: standard available/free external FIFO
End of enumeration elements list.
FIFOTX : FIFO transmit
bits : 26 - 27 (2 bit)
access : read-only
Enumeration:
0 : FIFO_2BYTE
FIFO_2BYTE: 2-byte TX FIFO, the default FIFO transmit value (FIFOTX)
0x1 : FIFO_4BYTE
FIFO_4BYTE: 4-byte TX FIFO
0x2 : FIFO_8BYTE
FIFO_8BYTE: 8-byte TX FIFO
0x3 : FIFO_16BYTE
FIFO_16BYTE: 16-byte TX FIFO
End of enumeration elements list.
FIFORX : FIFO receive
bits : 28 - 29 (2 bit)
access : read-only
Enumeration:
0 : FIFO_2BYTE
FIFO_2BYTE: 2 (or 3)-byte RX FIFO, the default FIFO receive value (FIFORX)
0x1 : FIFO_4BYTE
FIFO_4BYTE: 4-byte RX FIFO
0x2 : FIFO_8BYTE
FIFO_8BYTE: 8-byte RX FIFO
0x3 : FIFO_16BYTE
FIFO_16BYTE: 16-byte RX FIFO
End of enumeration elements list.
INT : INT
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : INTERRUPTSNO
Interrupts are not supported
0x1 : INTERRUPTSYES
Interrupts are supported
End of enumeration elements list.
DMA : DMA
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : DMANO
DMA is not supported
0x1 : DMAYES
DMA is supported
End of enumeration elements list.
Slave Dynamic Address Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAVALID : DAVALID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DANOTASSIGNED
DANOTASSIGNED: a Dynamic Address is not assigned
0x1 : DAASSIGNED
DAASSIGNED: a Dynamic Address is assigned
End of enumeration elements list.
DADDR : Dynamic address
bits : 1 - 7 (7 bit)
access : read-write
MAPIDX : Mapped Dynamic Address
bits : 8 - 11 (4 bit)
access : write-only
MAPSA : Map a Static Address
bits : 12 - 12 (1 bit)
access : write-only
KEY : Key
bits : 16 - 31 (16 bit)
access : read-write
Slave Maximum Limits Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXRD : Maximum read length
bits : 0 - 11 (12 bit)
access : read-write
MAXWR : Maximum write length
bits : 16 - 27 (12 bit)
access : read-write
Slave ID Part Number Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARTNO : Part number
bits : 0 - 31 (32 bit)
access : read-write
Slave ID Extension Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCR : Device Characteristic Register
bits : 8 - 15 (8 bit)
access : read-write
BCR : Bus Characteristics Register
bits : 16 - 23 (8 bit)
access : read-write
Slave Vendor ID Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VID : Vendor ID
bits : 0 - 14 (15 bit)
access : read-write
Slave Time Control Clock Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCURACY : Clock accuracy
bits : 0 - 7 (8 bit)
access : read-write
FREQ : Clock frequency
bits : 8 - 15 (8 bit)
access : read-write
Slave Message-Mapped Address Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAPLAST : Matched address index
bits : 0 - 3 (4 bit)
access : read-only
MAPLASTM1 : Previous match index 1
bits : 8 - 11 (4 bit)
access : read-only
MAPLASTM2 : Previous match index 2
bits : 16 - 19 (4 bit)
access : read-only
Slave Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STNOTSTOP : Status not stop
bits : 0 - 0 (1 bit)
access : read-only
STMSG : Status message
bits : 1 - 1 (1 bit)
access : read-only
STCCCH : Status Common Command Code Handler
bits : 2 - 2 (1 bit)
access : read-only
STREQRD : Status required
bits : 3 - 3 (1 bit)
access : read-only
STREQWR : Status request write
bits : 4 - 4 (1 bit)
access : read-only
STDAA : Status Dynamic Address Assignment
bits : 5 - 5 (1 bit)
access : read-only
STHDR : Status High Data Rate
bits : 6 - 6 (1 bit)
access : read-only
START : Start
bits : 8 - 8 (1 bit)
access : read-write
MATCHED : Matched
bits : 9 - 9 (1 bit)
access : read-write
STOP : Stop
bits : 10 - 10 (1 bit)
access : read-write
RX_PEND : Received message pending
bits : 11 - 11 (1 bit)
access : read-only
TXNOTFULL : Transmit buffer is not full
bits : 12 - 12 (1 bit)
access : read-only
DACHG : DACHG
bits : 13 - 13 (1 bit)
access : read-write
CCC : Common Command Code
bits : 14 - 14 (1 bit)
access : read-write
ERRWARN : Error warning
bits : 15 - 15 (1 bit)
access : read-only
HDRMATCH : High Data Rate command match
bits : 16 - 16 (1 bit)
access : read-write
CHANDLED : Common-Command-Code handled
bits : 17 - 17 (1 bit)
access : read-write
EVENT : Event
bits : 18 - 18 (1 bit)
access : read-write
EVDET : Event details
bits : 20 - 21 (2 bit)
access : read-only
Enumeration:
0 : NONE
NONE: no event or no pending event
0x1 : NO_REQUEST
NO_REQUEST: Request not sent yet. Either there was no START yet, or is waiting for Bus-Available or Bus-Idle (HJ).
0x2 : NACKED
NACKED: Not acknowledged(Request sent and NACKed); the module will try again.
0x3 : ACKED
ACKED: Acknowledged (Request sent and ACKed), so Done (unless the time control data is still being sent).
End of enumeration elements list.
IBIDIS : In-Band Interrupts are disabled
bits : 24 - 24 (1 bit)
access : read-only
MRDIS : Master requests are disabled
bits : 25 - 25 (1 bit)
access : read-only
HJDIS : Hot-Join is disabled
bits : 27 - 27 (1 bit)
access : read-only
ACTSTATE : Activity state from Common Command Codes (CCC)
bits : 28 - 29 (2 bit)
access : read-only
Enumeration:
0 : NO_LATENCY
NO_LATENCY: normal bus operations
0x1 : LATENCY_1MS
LATENCY_1MS: 1 ms of latency
0x2 : LATENCY_100MS
LATENCY_100MS: 100 ms of latency
0x3 : LATENCY_10S
LATENCY_10S: 10 seconds of latency
End of enumeration elements list.
TIMECTRL : Time control
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0 : NO_TIME_CONTROL
NO_TIME_CONTROL: No time control is enabled
0x2 : ASYNC_MODE
ASYNC_MODE: Asynchronous standard mode (0) is enabled
End of enumeration elements list.
Master Main Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQUEST : Request
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
NONE: Returns to this when finished with any request. The MSTATUS register indicates the master's state. See also AutoIBI mode. NONE is only written as 0: when setting RDTERM to 1 (to stop a read in progress) or when setting IBI reponse field (IBIRESP) for MSG use
0x1 : EMITSTARTADDR
EMITSTARTADDR: Emit START with address and direction from a stopped state or in the middle of a Single Data Rate (SDR) message. If from a stopped state (IDLE), then emit start may be prevented by an event (like IBI, MR, HJ), in which case the appropriate interrupt is signaled; note that Emit START can be resubmitted.
0x2 : EMITSTOP
EMITSTOP: Emit a STOP on bus. Must be in Single Data Rate (SDR) mode. If in Dynamic Address Assignment (DAA) mode, Emit stop will exit DAA mode.
0x3 : IBIACKNACK
IBIACKNACK: Manual In-Band Interrupt (IBI) Acknowledge (ACK) or Not Acknowledge (NACK). When IBIRESP has indicated a hold on an In-Band Interrupt to allow a manual decision, this request completes it. Uses IBIRESP to provide the information.
0x4 : PROCESSDAA
PROCESSDAA: If not in Dynamic Address Assignment (DAA) mode now, will issue START, 7E, ENTDAA, and then will emit 7E/R to process each slave. Will stop just before the new Dynamic Address (DA) is to be emitted. The next Process DAA request will use the Addr field as the new DA to assign. If NACKed on the 7E/R, then the interrupt will indicate this situation, and a STOP will be emitted.
0x6 : FORCEEXIT
FORCEEXIT and IBHR: Emit an Exit Pattern from any state, but end Double Data Rate (DDR) (including MSGDDR), if in DDR mode now. Includes a STOP afterward. If TYPE != 0, then it will perform an IBHR (In-Band Hardware Reset). If TYPE=2, then it does a normal reset (DEFRST can prevent the reset). If TYPE=3, it does a forced reset (will always reset).
0x7 : AUTOIBI
AUTOIBI: Hold in a stopped state, but auto-emit START,7E when the slave is holding down SDA to get an In-Band Interrupt (IBI). Actual In-Band Interrupt handling is defined by IBIRESP.
End of enumeration elements list.
TYPE : Bus type with START
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : I3C
I3C: Normally the SDR mode of I3C. For ForceExit, the Exit pattern.
0x1 : I2C
I2C: Normally the Standard I2C protocol.
0x2 : DDR
DDR: (Double Data Rate): Normally the HDR-DDR mode of I3C. Enter DDR mode (7E and then ENTHDR0), if the module is not already in DDR mode. The 1st byte written to the TX FIFO should be a command, and should already be in the FIFO. To end DDR mode, use ForceExit. For ForceExit, the normal IBHR (In-Band Hardware Reset).
0x3 : FORCEDIBHR
For ForcedExit, this is forced IBHR.
End of enumeration elements list.
IBIRESP : In-Band Interrupt (IBI) response
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : ACK
ACK: Acknowledge. A mandatory byte (or not) is decided by the Master In-band Interrupt Registry and Rules Register (MIBIRULES). To limit the maximum number of IBI bytes, configure the Read Termination field (MCTRL.RDTERM).
0x1 : NACK
NACK: Not acknowledge
0x2 : ACK_WITH_MANDATORY
ACK_WITH_MANDATORY: Acknowledge with mandatory byte (ignores the MIBIRULES register). Acknowledge with mandatory byte should not be used, unless only slaves with a mandatory byte can cause an In-Band Interrupt.
0x3 : MANUAL
MANUAL: stop and wait for a decision using the IBIAckNack request
End of enumeration elements list.
DIR : DIR
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DIRWRITE
DIRWRITE: Write
0x1 : DIRREAD
DIRREAD: Read
End of enumeration elements list.
ADDR : ADDR
bits : 9 - 15 (7 bit)
access : read-write
RDTERM : Read terminate
bits : 16 - 23 (8 bit)
access : read-write
Master Status Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE : State of the master
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : IDLE
IDLE: the bus has STOPped.
0x1 : SLVREQ
SLVREQ: (Slave Request state) the bus has STOPped but a slave is holding SDA low. If using auto-emit IBI (MCTRL.AutoIBI), then the master will not stay in the Slave Request state.
0x2 : MSGSDR
MSGSDR: in Single Data Rate (SDR) Message state (from using MWMSG_SDR)
0x3 : NORMACT
NORMACT: normal active Single Data Rate (SDR) state (from using MCTRL and MWDATAn and MRDATAn registers). The master will stay in the NORMACT state until a STOP is issued.
0x4 : DDR
MSGDDR: in Double Data Rate (DDR) Message mode (from using MWMSG_DDR or using the normal method with DDR). The master will stay in the DDR state, until the master exits using EXIT (emits the Exit pattern).
0x5 : DAA
DAA: in Enter Dynamic Address Assignment (ENTDAA) mode
0x6 : IBIACK
IBIACK: waiting for an In-Band Interrupt (IBI) ACK/NACK decision
0x7 : IBIRCV
IBIRCV: Receiving an In-Band Interrupt (IBI); this IBIRCV state is used after IBI/MR/HJ has won the arbitration, and IBIRCV state is also used for IBI mandatory byte (if any) and any bytes that follow.
End of enumeration elements list.
BETWEEN : Between messages or Dynamic Address Assignments (DAA)
bits : 4 - 4 (1 bit)
access : read-only
NACKED : Not acknowledged
bits : 5 - 5 (1 bit)
access : read-only
IBITYPE : In-Band Interrupt (IBI) type
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0 : NONE
NONE: cleared when IBI Won bit (MSTATUS.IBIWON) is cleared
0x1 : IBI
IBI: In-Band Interrupt
0x2 : MR
MR: Master Request
0x3 : HJ
HJ: Hot-Join
End of enumeration elements list.
SLVSTART : Slave start
bits : 8 - 8 (1 bit)
access : read-write
MCTRLDONE : Master control done
bits : 9 - 9 (1 bit)
access : read-write
COMPLETE : COMPLETE
bits : 10 - 10 (1 bit)
access : read-write
RXPEND : RXPEND
bits : 11 - 11 (1 bit)
access : read-only
TXNOTFULL : TX buffer/FIFO not yet full
bits : 12 - 12 (1 bit)
access : read-only
IBIWON : In-Band Interrupt (IBI) won
bits : 13 - 13 (1 bit)
access : read-write
ERRWARN : Error or warning
bits : 15 - 15 (1 bit)
access : read-only
NOWMASTER : Now master (now this module is a master)
bits : 19 - 19 (1 bit)
access : read-write
IBIADDR : IBI address
bits : 24 - 30 (7 bit)
access : read-only
Master In-band Interrupt Registry and Rules Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR0 : ADDR0
bits : 0 - 5 (6 bit)
access : read-write
ADDR1 : ADDR1
bits : 6 - 11 (6 bit)
access : read-write
ADDR2 : ADDR2
bits : 12 - 17 (6 bit)
access : read-write
ADDR3 : ADDR3
bits : 18 - 23 (6 bit)
access : read-write
ADDR4 : ADDR4
bits : 24 - 29 (6 bit)
access : read-write
MSB0 : Set Most Significant address Bit to 0
bits : 30 - 30 (1 bit)
access : read-write
NOBYTE : No IBI byte
bits : 31 - 31 (1 bit)
access : read-write
Master Interrupt Set Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLVSTART : Slave start interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
MCTRLDONE : Master control done interrupt enable
bits : 9 - 9 (1 bit)
access : read-write
COMPLETE : Completed message interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
RXPEND : RX pending interrupt enable
bits : 11 - 11 (1 bit)
access : read-write
TXNOTFULL : TX buffer/FIFO is not full interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
IBIWON : In-Band Interrupt (IBI) won interrupt enable
bits : 13 - 13 (1 bit)
access : read-write
ERRWARN : Error or warning (ERRWARN) interrupt enable
bits : 15 - 15 (1 bit)
access : read-write
NOWMASTER : Now master (now this I3C module is a master) interrupt enable
bits : 19 - 19 (1 bit)
access : read-write
Master Interrupt Clear Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLVSTART : SLVSTART interrupt enable clear
bits : 8 - 8 (1 bit)
access : write-only
MCTRLDONE : MCTRLDONE interrupt enable clear
bits : 9 - 9 (1 bit)
access : write-only
COMPLETE : COMPLETE interrupt enable clear
bits : 10 - 10 (1 bit)
access : write-only
RXPEND : RXPEND interrupt enable clear
bits : 11 - 11 (1 bit)
access : write-only
TXNOTFULL : TXNOTFULL interrupt enable clear
bits : 12 - 12 (1 bit)
access : write-only
IBIWON : IBIWON interrupt enable clear
bits : 13 - 13 (1 bit)
access : write-only
ERRWARN : ERRWARN interrupt enable clear
bits : 15 - 15 (1 bit)
access : write-only
NOWMASTER : NOWMASTER interrupt enable clear
bits : 19 - 19 (1 bit)
access : write-only
Master Interrupt Mask Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLVSTART : SLVSTART interrupt mask
bits : 8 - 8 (1 bit)
access : read-only
MCTRLDONE : MCTRLDONE interrupt mask
bits : 9 - 9 (1 bit)
access : read-only
COMPLETE : COMPLETE interrupt mask
bits : 10 - 10 (1 bit)
access : read-only
RXPEND : RXPEND interrupt mask
bits : 11 - 11 (1 bit)
access : read-only
TXNOTFULL : TXNOTFULL interrupt mask
bits : 12 - 12 (1 bit)
access : read-only
IBIWON : IBIWON interrupt mask
bits : 13 - 13 (1 bit)
access : read-only
ERRWARN : ERRWARN interrupt mask
bits : 15 - 15 (1 bit)
access : read-only
NOWMASTER : NOWMASTER interrupt mask
bits : 19 - 19 (1 bit)
access : read-only
Master Errors and Warnings Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NACK : Not acknowledge (NACK) error
bits : 2 - 2 (1 bit)
access : read-write
WRABT : WRABT (Write abort) error
bits : 3 - 3 (1 bit)
access : read-write
TERM : Terminate error
bits : 4 - 4 (1 bit)
access : read-write
HPAR : High data rate parity
bits : 9 - 9 (1 bit)
access : read-write
HCRC : High data rate CRC error
bits : 10 - 10 (1 bit)
access : read-write
OREAD : Over-read error
bits : 16 - 16 (1 bit)
access : read-write
OWRITE : Over-write error
bits : 17 - 17 (1 bit)
access : read-write
MSGERR : Message error
bits : 18 - 18 (1 bit)
access : read-write
INVREQ : Invalid request error
bits : 19 - 19 (1 bit)
access : read-write
TIMEOUT : TIMEOUT error
bits : 20 - 20 (1 bit)
access : read-write
Master DMA Control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAFB : DMA from bus
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NOT_USED
NOT_USED: DMA is not used
0x1 : ENABLE_ONE_FRAME
ENABLE_ONE_FRAME: DMA is enabled for 1 frame. DMAFB auto-clears on STOP or repeated START. See MCONFIG.MATCHSS.
0x2 : ENABLE
ENABLE: DMA is enabled until the DMA is turned off.
End of enumeration elements list.
DMATB : DMA to bus
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : NOT_USED
NOT_USED: DMA is not used
0x1 : ENABLE_ONE_FRAME
ENABLE_ONE_FRAME: DMA is enabled for 1 frame (ended by DMA or Terminated). DMATB auto-clears on STOP or START. See MCONFIG.MATCHSS.
0x2 : ENABLE
ENABLE: DMA is enabled until DMA is turned off. Normally DMA ENABLE should only be used in Master Message mode.
End of enumeration elements list.
DMAWIDTH : DMA width
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : BYTE
BYTE
0x1 : BYTE_AGAIN
BYTE_AGAIN
0x2 : HALF_WORD
HALF_WORD: Half-word (16 bits). This will make sure that 2 bytes are free/available in FIFO.
End of enumeration elements list.
Master Data Control Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLUSHTB : Flush to-bus buffer/FIFO
bits : 0 - 0 (1 bit)
access : write-only
FLUSHFB : Flush from-bus buffer/FIFO
bits : 1 - 1 (1 bit)
access : write-only
UNLOCK : Unlock
bits : 2 - 2 (1 bit)
access : write-only
TXTRIG : TX trigger level
bits : 4 - 5 (2 bit)
access : read-write
RXTRIG : RX trigger level
bits : 6 - 7 (2 bit)
access : read-write
TXCOUNT : TX byte count
bits : 16 - 20 (5 bit)
access : read-only
RXCOUNT : RX byte count
bits : 24 - 28 (5 bit)
access : read-only
TXFULL : TX is full
bits : 30 - 30 (1 bit)
access : read-only
RXEMPTY : RX is empty
bits : 31 - 31 (1 bit)
access : read-only
Master Write Data Byte Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data byte
bits : 0 - 7 (8 bit)
access : write-only
END : End of message
bits : 8 - 8 (1 bit)
access : write-only
END_ALSO : End of message also
bits : 16 - 16 (1 bit)
access : write-only
Master Write Data Byte End Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 7 (8 bit)
access : write-only
Master Write Data Half-word Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Data byte 0
bits : 0 - 7 (8 bit)
access : write-only
DATA1 : Data byte 1
bits : 8 - 15 (8 bit)
access : write-only
END : End of message
bits : 16 - 16 (1 bit)
access : write-only
Master Write Data Byte End Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : DATA 0
bits : 0 - 7 (8 bit)
access : write-only
DATA1 : DATA 1
bits : 8 - 15 (8 bit)
access : write-only
Slave Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENT : EVENT
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
NORMAL_MODE: If EVENT is set to 0 after was a non-0 value, event processing will cancel if the event processing has not yet started; if event processing has already been started, then event processing will not be be cancelled.
0x1 : IBI
IBI: Start an In-Band Interrupt. This will try to push an IBI interrupt onto the I3C bus. If data is associated with the IBI, then the data will be read from the SCTRL.IBIDATA field. If time control is enabled, then this data will also include any time control-related bytes; additionally, the IBIDATA byte will have bit 7 set to 1 automatically (as is required for time control). The IBI interrupt will occur after the 1st (mandatory) IBIDATA, if any.
0x2 : MASTER_REQUEST
MASTER_REQUEST: Start a Master-Request.
0x3 : HOT_JOIN_REQUEST
HOT_JOIN_REQUEST: Start a Hot-Join request. A Hot-Join Request should only be used when the device is powered on after the I3C bus is already powered up, or when the device is connected using hot insertion methods (the device is powered up when it is physically inserted onto the powered-up I3C bus). The hot join will wait for Bus Idle, and SCTRL.EVENT=HOT_JOIN_REQUEST must be set before the slave enable (SCONFIG.SLVENA).
End of enumeration elements list.
IBIDATA : In-Band Interrupt data
bits : 8 - 15 (8 bit)
access : read-write
PENDINT : Pending interrupt
bits : 16 - 19 (4 bit)
access : read-write
ACTSTATE : Activity state (of slave)
bits : 20 - 21 (2 bit)
access : read-write
VENDINFO : Vendor information
bits : 24 - 31 (8 bit)
access : read-write
Master Read Data Byte Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : VALUE
bits : 0 - 7 (8 bit)
access : read-only
Master Read Data Half-word Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LSB : LSB
bits : 0 - 7 (8 bit)
access : read-only
MSB : MSB
bits : 8 - 15 (8 bit)
access : read-only
Master Write Message in SDR mode
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : MWMSG_SDR
reset_Mask : 0x0
DIR : Direction
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : WRITE
Write
0x1 : READ
Read
End of enumeration elements list.
ADDR : Address to be written to
bits : 1 - 7 (7 bit)
access : write-only
END : End of SDR message
bits : 8 - 8 (1 bit)
access : write-only
I2C : I2C
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
0 : I3CMESSAGE
I3C message
0x1 : I2CMESSAGE
I2C message
End of enumeration elements list.
LEN : Length
bits : 11 - 15 (5 bit)
access : write-only
Master Write Message Data in SDR mode
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : MWMSG_SDR
reset_Mask : 0x0
DATA16B : Data
bits : 0 - 15 (16 bit)
access : write-only
END : End of message
bits : 16 - 16 (1 bit)
access : write-only
Master Read Message in SDR mode
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 15 (16 bit)
access : read-only
Master Write Message in DDR mode
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : MWMSG_DDR
reset_Mask : 0x0
LEN : Length of message
bits : 0 - 9 (10 bit)
access : write-only
END : End of message
bits : 14 - 14 (1 bit)
access : write-only
Master Write Message Data in DDR mode
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : MWMSG_DDR
reset_Mask : 0x0
DATA16B : Data
bits : 0 - 15 (16 bit)
access : write-only
END : End of message
bits : 16 - 16 (1 bit)
access : write-only
Master Read Message in DDR mode
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 15 (16 bit)
access : read-write
CLEN : Current length
bits : 16 - 25 (10 bit)
access : read-write
Master Dynamic Address Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAVALID : Dynamic address valid
bits : 0 - 0 (1 bit)
access : read-write
DADDR : Dynamic address
bits : 1 - 7 (7 bit)
access : read-write
Slave Module ID Register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
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