Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xF9C byte (0x0)
mem_usage : registers
protection : not protected
CHANNEL[1]-CHANNEL[0]-DIVHFCLK
CHANNEL[1]-CHANNEL[0]-PREAC2FSCOEF
CHANNEL[1]-CHANNEL[0]-PREAC4FSCOEF
CHANNEL[1]-CHANNEL[0]-GAINSHIFT
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-OSR
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DIVHFCLK
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC2FSCOEF
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC4FSCOEF
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-GAINSHIFT
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_CTRL
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_STATUS
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_DATA
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PHY_CTRL
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DC_CTRL
CHANNEL[1]-CHANNEL[0]-FIFO_CTRL
CHANNEL[1]-CHANNEL[0]-FIFO_STATUS
CHANNEL[1]-CHANNEL[0]-FIFO_DATA
CHANNEL[1]-CHANNEL[0]-PHY_CTRL
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-OSR
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DIVHFCLK
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC2FSCOEF
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC4FSCOEF
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-GAINSHIFT
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_CTRL
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_STATUS
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_DATA
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PHY_CTRL
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DC_CTRL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-OSR
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DIVHFCLK
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC2FSCOEF
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC4FSCOEF
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-GAINSHIFT
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_CTRL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_STATUS
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_DATA
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PHY_CTRL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DC_CTRL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-OSR
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DIVHFCLK
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC2FSCOEF
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC4FSCOEF
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-GAINSHIFT
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_CTRL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_STATUS
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_DATA
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PHY_CTRL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DC_CTRL
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-OSR
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DIVHFCLK
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC2FSCOEF
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC4FSCOEF
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-GAINSHIFT
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_CTRL
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_STATUS
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_DATA
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PHY_CTRL
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DC_CTRL
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-OSR
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DIVHFCLK
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC2FSCOEF
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PREAC4FSCOEF
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-GAINSHIFT
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_CTRL
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_STATUS
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-FIFO_DATA
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-PHY_CTRL
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-DC_CTRL
CIC Filter decimation rate
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Selects the oversample rate for the related input channel.
bits : 0 - 7 (8 bit)
access : read-write
Decimator output gain adjustment
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Gain shift for decimator output (can be positive or negative number)
bits : 0 - 5 (6 bit)
access : read-write
CIC Filter decimation rate
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Selects the oversample rate for the related input channel.
bits : 0 - 7 (8 bit)
access : read-write
Divider for generating PDM clock from DMIC clock input
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMDIV : Divide by factor to create PDM Clock (enumerated type)
bits : 0 - 3 (4 bit)
access : read-write
Compensation filter for 2FS
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Compensation filter for 4FS
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Decimator output gain adjustment
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Gain shift for decimator output (can be positive or negative number)
bits : 0 - 5 (6 bit)
access : read-write
CIC Filter decimation rate
address_offset : 0x1500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Selects the oversample rate for the related input channel.
bits : 0 - 7 (8 bit)
access : read-write
Divider for generating PDM clock from DMIC clock input
address_offset : 0x1504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMDIV : Divide by factor to create PDM Clock (enumerated type)
bits : 0 - 3 (4 bit)
access : read-write
Compensation filter for 2FS
address_offset : 0x1508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Compensation filter for 4FS
address_offset : 0x150C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Decimator output gain adjustment
address_offset : 0x1510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Gain shift for decimator output (can be positive or negative number)
bits : 0 - 5 (6 bit)
access : read-write
FIFO Control
address_offset : 0x1580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : FIFO enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1 : ENABLED
FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
End of enumeration elements list.
RESETN : FIFO reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset the FIFO.
0x1 : NORMAL
Normal operation
End of enumeration elements list.
INTEN : Interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO level interrupts are not enabled.
0x1 : ENABLED
FIFO level interrupts are enabled.
End of enumeration elements list.
DMAEN : DMA enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA requests are not enabled.
0x1 : ENABLED
DMA requests based on FIFO level are enabled.
End of enumeration elements list.
TRIGLVL : Trigger level for interrupt
bits : 16 - 20 (5 bit)
access : read-write
FIFO Status
address_offset : 0x1584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Status of Interrupt (write 1 to clear)
bits : 0 - 0 (1 bit)
access : read-write
OVERRUN : Overrun Detected (write 1 to clear)
bits : 1 - 1 (1 bit)
access : read-write
UNDERRUN : Underrun Detected (write 1 to clear)
bits : 2 - 2 (1 bit)
access : read-write
FIFO Data
address_offset : 0x1588 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PCM Data
bits : 0 - 23 (24 bit)
access : read-only
Phy Ctrl
address_offset : 0x158C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_FALL : Capture DMIC on Falling edge (0 means on rising)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Capture PDM_DATA on the rising edge of PDM_CLK.
0x1 : FALLING_EDGE
Capture PDM_DATA on the falling edge of PDM_CLK.
End of enumeration elements list.
PHY_HALF : Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
0x1 : HALF_RATE
Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
End of enumeration elements list.
DC Filter Control
address_offset : 0x1590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPOLE : DC block filter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLAT_RESPONSE
Flat response, no filter.
0x1 : HZ_155
155 Hz.
0x2 : HZ_78
78 Hz.
0x3 : HZ_39
39 Hz
End of enumeration elements list.
DCGAIN : Fine gain adjustment in the form of a number of bits to downshift.
bits : 4 - 7 (4 bit)
access : read-write
SATURATEAT16BIT : Selects 16-bit saturation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SATURATE
Results roll over if out range and do not saturate.
0x1 : SATURATE
If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
End of enumeration elements list.
SIGNEXTEND : Sign extend.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SIGNEXTEND
The top byte of the FIFODATA register is always 0.
0x1 : SIGNEXTEND
The top byte of the FIFODATA register is sign extended. This allows processing of 24-bit audio data on 32-bit machines.
End of enumeration elements list.
FIFO Control
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : FIFO enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1 : ENABLED
FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
End of enumeration elements list.
RESETN : FIFO reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset the FIFO.
0x1 : NORMAL
Normal operation
End of enumeration elements list.
INTEN : Interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO level interrupts are not enabled.
0x1 : ENABLED
FIFO level interrupts are enabled.
End of enumeration elements list.
DMAEN : DMA enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA requests are not enabled.
0x1 : ENABLED
DMA requests based on FIFO level are enabled.
End of enumeration elements list.
TRIGLVL : Trigger level for interrupt
bits : 16 - 20 (5 bit)
access : read-write
FIFO Status
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Status of Interrupt (write 1 to clear)
bits : 0 - 0 (1 bit)
access : read-write
OVERRUN : Overrun Detected (write 1 to clear)
bits : 1 - 1 (1 bit)
access : read-write
UNDERRUN : Underrun Detected (write 1 to clear)
bits : 2 - 2 (1 bit)
access : read-write
FIFO Data
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PCM Data
bits : 0 - 23 (24 bit)
access : read-only
Phy Ctrl
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_FALL : Capture DMIC on Falling edge (0 means on rising)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Capture PDM_DATA on the rising edge of PDM_CLK.
0x1 : FALLING_EDGE
Capture PDM_DATA on the falling edge of PDM_CLK.
End of enumeration elements list.
PHY_HALF : Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
0x1 : HALF_RATE
Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
End of enumeration elements list.
DC Filter Control
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPOLE : DC block filter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLAT_RESPONSE
Flat response, no filter.
0x1 : HZ_155
155 Hz.
0x2 : HZ_78
78 Hz.
0x3 : HZ_39
39 Hz
End of enumeration elements list.
DCGAIN : Fine gain adjustment in the form of a number of bits to downshift.
bits : 4 - 7 (4 bit)
access : read-write
SATURATEAT16BIT : Selects 16-bit saturation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SATURATE
Results roll over if out range and do not saturate.
0x1 : SATURATE
If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
End of enumeration elements list.
SIGNEXTEND : Sign extend.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SIGNEXTEND
The top byte of the FIFODATA register is always 0.
0x1 : SIGNEXTEND
The top byte of the FIFODATA register is sign extended. This allows processing of 24-bit audio data on 32-bit machines.
End of enumeration elements list.
CIC Filter decimation rate
address_offset : 0x1C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Selects the oversample rate for the related input channel.
bits : 0 - 7 (8 bit)
access : read-write
Divider for generating PDM clock from DMIC clock input
address_offset : 0x1C04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMDIV : Divide by factor to create PDM Clock (enumerated type)
bits : 0 - 3 (4 bit)
access : read-write
Compensation filter for 2FS
address_offset : 0x1C08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Compensation filter for 4FS
address_offset : 0x1C0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Decimator output gain adjustment
address_offset : 0x1C10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Gain shift for decimator output (can be positive or negative number)
bits : 0 - 5 (6 bit)
access : read-write
FIFO Control
address_offset : 0x1C80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : FIFO enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1 : ENABLED
FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
End of enumeration elements list.
RESETN : FIFO reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset the FIFO.
0x1 : NORMAL
Normal operation
End of enumeration elements list.
INTEN : Interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO level interrupts are not enabled.
0x1 : ENABLED
FIFO level interrupts are enabled.
End of enumeration elements list.
DMAEN : DMA enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA requests are not enabled.
0x1 : ENABLED
DMA requests based on FIFO level are enabled.
End of enumeration elements list.
TRIGLVL : Trigger level for interrupt
bits : 16 - 20 (5 bit)
access : read-write
FIFO Status
address_offset : 0x1C84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Status of Interrupt (write 1 to clear)
bits : 0 - 0 (1 bit)
access : read-write
OVERRUN : Overrun Detected (write 1 to clear)
bits : 1 - 1 (1 bit)
access : read-write
UNDERRUN : Underrun Detected (write 1 to clear)
bits : 2 - 2 (1 bit)
access : read-write
FIFO Data
address_offset : 0x1C88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PCM Data
bits : 0 - 23 (24 bit)
access : read-only
Phy Ctrl
address_offset : 0x1C8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_FALL : Capture DMIC on Falling edge (0 means on rising)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Capture PDM_DATA on the rising edge of PDM_CLK.
0x1 : FALLING_EDGE
Capture PDM_DATA on the falling edge of PDM_CLK.
End of enumeration elements list.
PHY_HALF : Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
0x1 : HALF_RATE
Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
End of enumeration elements list.
DC Filter Control
address_offset : 0x1C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPOLE : DC block filter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLAT_RESPONSE
Flat response, no filter.
0x1 : HZ_155
155 Hz.
0x2 : HZ_78
78 Hz.
0x3 : HZ_39
39 Hz
End of enumeration elements list.
DCGAIN : Fine gain adjustment in the form of a number of bits to downshift.
bits : 4 - 7 (4 bit)
access : read-write
SATURATEAT16BIT : Selects 16-bit saturation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SATURATE
Results roll over if out range and do not saturate.
0x1 : SATURATE
If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
End of enumeration elements list.
SIGNEXTEND : Sign extend.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SIGNEXTEND
The top byte of the FIFODATA register is always 0.
0x1 : SIGNEXTEND
The top byte of the FIFODATA register is sign extended. This allows processing of 24-bit audio data on 32-bit machines.
End of enumeration elements list.
CIC Filter decimation rate
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Selects the oversample rate for the related input channel.
bits : 0 - 7 (8 bit)
access : read-write
Divider for generating PDM clock from DMIC clock input
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMDIV : Divide by factor to create PDM Clock (enumerated type)
bits : 0 - 3 (4 bit)
access : read-write
Compensation filter for 2FS
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Compensation filter for 4FS
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Decimator output gain adjustment
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Gain shift for decimator output (can be positive or negative number)
bits : 0 - 5 (6 bit)
access : read-write
FIFO Control
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : FIFO enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1 : ENABLED
FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
End of enumeration elements list.
RESETN : FIFO reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset the FIFO.
0x1 : NORMAL
Normal operation
End of enumeration elements list.
INTEN : Interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO level interrupts are not enabled.
0x1 : ENABLED
FIFO level interrupts are enabled.
End of enumeration elements list.
DMAEN : DMA enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA requests are not enabled.
0x1 : ENABLED
DMA requests based on FIFO level are enabled.
End of enumeration elements list.
TRIGLVL : Trigger level for interrupt
bits : 16 - 20 (5 bit)
access : read-write
FIFO Status
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Status of Interrupt (write 1 to clear)
bits : 0 - 0 (1 bit)
access : read-write
OVERRUN : Overrun Detected (write 1 to clear)
bits : 1 - 1 (1 bit)
access : read-write
UNDERRUN : Underrun Detected (write 1 to clear)
bits : 2 - 2 (1 bit)
access : read-write
FIFO Data
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PCM Data
bits : 0 - 23 (24 bit)
access : read-only
Phy Ctrl
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_FALL : Capture DMIC on Falling edge (0 means on rising)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Capture PDM_DATA on the rising edge of PDM_CLK.
0x1 : FALLING_EDGE
Capture PDM_DATA on the falling edge of PDM_CLK.
End of enumeration elements list.
PHY_HALF : Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
0x1 : HALF_RATE
Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
End of enumeration elements list.
DC Filter Control
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPOLE : DC block filter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLAT_RESPONSE
Flat response, no filter.
0x1 : HZ_155
155 Hz.
0x2 : HZ_78
78 Hz.
0x3 : HZ_39
39 Hz
End of enumeration elements list.
DCGAIN : Fine gain adjustment in the form of a number of bits to downshift.
bits : 4 - 7 (4 bit)
access : read-write
SATURATEAT16BIT : Selects 16-bit saturation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SATURATE
Results roll over if out range and do not saturate.
0x1 : SATURATE
If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
End of enumeration elements list.
SIGNEXTEND : Sign extend.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SIGNEXTEND
The top byte of the FIFODATA register is always 0.
0x1 : SIGNEXTEND
The top byte of the FIFODATA register is sign extended. This allows processing of 24-bit audio data on 32-bit machines.
End of enumeration elements list.
Divider for generating PDM clock from DMIC clock input
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMDIV : Divide by factor to create PDM Clock (enumerated type)
bits : 0 - 3 (4 bit)
access : read-write
CIC Filter decimation rate
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Selects the oversample rate for the related input channel.
bits : 0 - 7 (8 bit)
access : read-write
Divider for generating PDM clock from DMIC clock input
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMDIV : Divide by factor to create PDM Clock (enumerated type)
bits : 0 - 3 (4 bit)
access : read-write
Compensation filter for 2FS
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Compensation filter for 4FS
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Decimator output gain adjustment
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Gain shift for decimator output (can be positive or negative number)
bits : 0 - 5 (6 bit)
access : read-write
FIFO Control
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : FIFO enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1 : ENABLED
FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
End of enumeration elements list.
RESETN : FIFO reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset the FIFO.
0x1 : NORMAL
Normal operation
End of enumeration elements list.
INTEN : Interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO level interrupts are not enabled.
0x1 : ENABLED
FIFO level interrupts are enabled.
End of enumeration elements list.
DMAEN : DMA enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA requests are not enabled.
0x1 : ENABLED
DMA requests based on FIFO level are enabled.
End of enumeration elements list.
TRIGLVL : Trigger level for interrupt
bits : 16 - 20 (5 bit)
access : read-write
FIFO Status
address_offset : 0x684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Status of Interrupt (write 1 to clear)
bits : 0 - 0 (1 bit)
access : read-write
OVERRUN : Overrun Detected (write 1 to clear)
bits : 1 - 1 (1 bit)
access : read-write
UNDERRUN : Underrun Detected (write 1 to clear)
bits : 2 - 2 (1 bit)
access : read-write
FIFO Data
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PCM Data
bits : 0 - 23 (24 bit)
access : read-only
Phy Ctrl
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_FALL : Capture DMIC on Falling edge (0 means on rising)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Capture PDM_DATA on the rising edge of PDM_CLK.
0x1 : FALLING_EDGE
Capture PDM_DATA on the falling edge of PDM_CLK.
End of enumeration elements list.
PHY_HALF : Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
0x1 : HALF_RATE
Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
End of enumeration elements list.
DC Filter Control
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPOLE : DC block filter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLAT_RESPONSE
Flat response, no filter.
0x1 : HZ_155
155 Hz.
0x2 : HZ_78
78 Hz.
0x3 : HZ_39
39 Hz
End of enumeration elements list.
DCGAIN : Fine gain adjustment in the form of a number of bits to downshift.
bits : 4 - 7 (4 bit)
access : read-write
SATURATEAT16BIT : Selects 16-bit saturation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SATURATE
Results roll over if out range and do not saturate.
0x1 : SATURATE
If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
End of enumeration elements list.
SIGNEXTEND : Sign extend.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SIGNEXTEND
The top byte of the FIFODATA register is always 0.
0x1 : SIGNEXTEND
The top byte of the FIFODATA register is sign extended. This allows processing of 24-bit audio data on 32-bit machines.
End of enumeration elements list.
Compensation filter for 2FS
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
FIFO Control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : FIFO enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1 : ENABLED
FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
End of enumeration elements list.
RESETN : FIFO reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset the FIFO.
0x1 : NORMAL
Normal operation
End of enumeration elements list.
INTEN : Interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO level interrupts are not enabled.
0x1 : ENABLED
FIFO level interrupts are enabled.
End of enumeration elements list.
DMAEN : DMA enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA requests are not enabled.
0x1 : ENABLED
DMA requests based on FIFO level are enabled.
End of enumeration elements list.
TRIGLVL : Trigger level for interrupt
bits : 16 - 20 (5 bit)
access : read-write
FIFO Status
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Status of Interrupt (write 1 to clear)
bits : 0 - 0 (1 bit)
access : read-write
OVERRUN : Overrun Detected (write 1 to clear)
bits : 1 - 1 (1 bit)
access : read-write
UNDERRUN : Underrun Detected (write 1 to clear)
bits : 2 - 2 (1 bit)
access : read-write
FIFO Data
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PCM Data
bits : 0 - 23 (24 bit)
access : read-only
Phy Ctrl
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_FALL : Capture DMIC on Falling edge (0 means on rising)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Capture PDM_DATA on the rising edge of PDM_CLK.
0x1 : FALLING_EDGE
Capture PDM_DATA on the falling edge of PDM_CLK.
End of enumeration elements list.
PHY_HALF : Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
0x1 : HALF_RATE
Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
End of enumeration elements list.
DC Filter Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPOLE : DC block filter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLAT_RESPONSE
Flat response, no filter.
0x1 : HZ_155
155 Hz.
0x2 : HZ_78
78 Hz.
0x3 : HZ_39
39 Hz
End of enumeration elements list.
DCGAIN : Fine gain adjustment in the form of a number of bits to downshift.
bits : 4 - 7 (4 bit)
access : read-write
SATURATEAT16BIT : Selects 16-bit saturation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SATURATE
Results roll over if out range and do not saturate.
0x1 : SATURATE
If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
End of enumeration elements list.
SIGNEXTEND : Sign extend.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SIGNEXTEND
The top byte of the FIFODATA register is always 0.
0x1 : SIGNEXTEND
The top byte of the FIFODATA register is sign extended. This allows processing of 24-bit audio data on 32-bit machines.
End of enumeration elements list.
CIC Filter decimation rate
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Selects the oversample rate for the related input channel.
bits : 0 - 7 (8 bit)
access : read-write
Divider for generating PDM clock from DMIC clock input
address_offset : 0xA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMDIV : Divide by factor to create PDM Clock (enumerated type)
bits : 0 - 3 (4 bit)
access : read-write
Compensation filter for 2FS
address_offset : 0xA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Compensation filter for 4FS
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Decimator output gain adjustment
address_offset : 0xA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Gain shift for decimator output (can be positive or negative number)
bits : 0 - 5 (6 bit)
access : read-write
FIFO Control
address_offset : 0xA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : FIFO enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1 : ENABLED
FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
End of enumeration elements list.
RESETN : FIFO reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset the FIFO.
0x1 : NORMAL
Normal operation
End of enumeration elements list.
INTEN : Interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO level interrupts are not enabled.
0x1 : ENABLED
FIFO level interrupts are enabled.
End of enumeration elements list.
DMAEN : DMA enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA requests are not enabled.
0x1 : ENABLED
DMA requests based on FIFO level are enabled.
End of enumeration elements list.
TRIGLVL : Trigger level for interrupt
bits : 16 - 20 (5 bit)
access : read-write
FIFO Status
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Status of Interrupt (write 1 to clear)
bits : 0 - 0 (1 bit)
access : read-write
OVERRUN : Overrun Detected (write 1 to clear)
bits : 1 - 1 (1 bit)
access : read-write
UNDERRUN : Underrun Detected (write 1 to clear)
bits : 2 - 2 (1 bit)
access : read-write
FIFO Data
address_offset : 0xA88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PCM Data
bits : 0 - 23 (24 bit)
access : read-only
Phy Ctrl
address_offset : 0xA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_FALL : Capture DMIC on Falling edge (0 means on rising)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Capture PDM_DATA on the rising edge of PDM_CLK.
0x1 : FALLING_EDGE
Capture PDM_DATA on the falling edge of PDM_CLK.
End of enumeration elements list.
PHY_HALF : Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
0x1 : HALF_RATE
Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
End of enumeration elements list.
DC Filter Control
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPOLE : DC block filter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLAT_RESPONSE
Flat response, no filter.
0x1 : HZ_155
155 Hz.
0x2 : HZ_78
78 Hz.
0x3 : HZ_39
39 Hz
End of enumeration elements list.
DCGAIN : Fine gain adjustment in the form of a number of bits to downshift.
bits : 4 - 7 (4 bit)
access : read-write
SATURATEAT16BIT : Selects 16-bit saturation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SATURATE
Results roll over if out range and do not saturate.
0x1 : SATURATE
If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
End of enumeration elements list.
SIGNEXTEND : Sign extend.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SIGNEXTEND
The top byte of the FIFODATA register is always 0.
0x1 : SIGNEXTEND
The top byte of the FIFODATA register is sign extended. This allows processing of 24-bit audio data on 32-bit machines.
End of enumeration elements list.
Compensation filter for 4FS
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
CIC Filter decimation rate
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Selects the oversample rate for the related input channel.
bits : 0 - 7 (8 bit)
access : read-write
Channel Enable register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN_CH0 : Enable channel 0. When 1, PDM channel 0 is enabled.
bits : 0 - 0 (1 bit)
access : read-write
EN_CH1 : Enable channel 1. When 1, PDM channel 1 is enabled.
bits : 1 - 1 (1 bit)
access : read-write
EN_CH2 : Enable channel 2. When 1, PDM channel 2 is enabled.
bits : 2 - 2 (1 bit)
access : read-write
EN_CH3 : Enable channel 3. When 1, PDM channel 3 is enabled.
bits : 3 - 3 (1 bit)
access : read-write
EN_CH4 : Enable channel 4. When 1, PDM channel 4 is enabled.
bits : 4 - 4 (1 bit)
access : read-write
EN_CH5 : Enable channel 5. When 1, PDM channel 5 is enabled.
bits : 5 - 5 (1 bit)
access : read-write
EN_CH6 : Enable channel 6. When 1, PDM channel 6 is enabled.
bits : 6 - 6 (1 bit)
access : read-write
EN_CH7 : Enable channel 7. When 1, PDM channel 7 is enabled.
bits : 7 - 7 (1 bit)
access : read-write
Divider for generating PDM clock from DMIC clock input
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMDIV : Divide by factor to create PDM Clock (enumerated type)
bits : 0 - 3 (4 bit)
access : read-write
Compensation filter for 2FS
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Compensation filter for 4FS
address_offset : 0xF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : Co-efficient choice for CIC droop compensation droop filter
bits : 0 - 1 (2 bit)
access : read-write
Decimator output gain adjustment
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Gain shift for decimator output (can be positive or negative number)
bits : 0 - 5 (6 bit)
access : read-write
Use 2FS register
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USE2FS : Use 2FS register
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : USE_1FS
Use 1FS output for PCM data.
0x1 : USE_2FS
Use 2FS output for PCM data.
End of enumeration elements list.
global sync enable
address_offset : 0xF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_SYNC_EN : Choose which channels to sync to global sync (7:0) corresponds to the 8 channels
bits : 0 - 7 (8 bit)
access : read-write
no description available
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCOUNTVAL : 32bit value, global sync counter will trigger a pulse whenever count reaches GCOUNTVAL
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DECRESET : no description available
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : RELEASE_RESET
release reset to decimator
0x1 : ASSERT_RESET
assert reset to decimator Note : resets are applied in pairs. So bit 0 corresponds to channels 0/1, bit1 corresponds to channels 2/3, bit2 to channel 4/5 and bit3 to channel 6/7
End of enumeration elements list.
FIFO Control
address_offset : 0xF80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : FIFO enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a period when the data was not needed.
0x1 : ENABLED
FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
End of enumeration elements list.
RESETN : FIFO reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset the FIFO.
0x1 : NORMAL
Normal operation
End of enumeration elements list.
INTEN : Interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
FIFO level interrupts are not enabled.
0x1 : ENABLED
FIFO level interrupts are enabled.
End of enumeration elements list.
DMAEN : DMA enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA requests are not enabled.
0x1 : ENABLED
DMA requests based on FIFO level are enabled.
End of enumeration elements list.
TRIGLVL : Trigger level for interrupt
bits : 16 - 20 (5 bit)
access : read-write
HWVAD input gain register
address_offset : 0xF80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUTGAIN : Gain factor for input signal into HWVAD
bits : 0 - 3 (4 bit)
access : read-write
FIFO Status
address_offset : 0xF84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Status of Interrupt (write 1 to clear)
bits : 0 - 0 (1 bit)
access : read-write
OVERRUN : Overrun Detected (write 1 to clear)
bits : 1 - 1 (1 bit)
access : read-write
UNDERRUN : Underrun Detected (write 1 to clear)
bits : 2 - 2 (1 bit)
access : read-write
HWVAD filter control register
address_offset : 0xF84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPFS : This field chooses the High Pass filter in first part of HWVAD
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : BYPASS
First filter by-pass.
0x1 : HIGH_PASS_1750HZ
High pass filter with -3dB cut-off at 1750Hz.
0x2 : HIGH_PASS_215HZ
High pass filter with -3dB cut-off at 215Hz.
End of enumeration elements list.
FIFO Data
address_offset : 0xF88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PCM Data
bits : 0 - 23 (24 bit)
access : read-only
HWVAD control register
address_offset : 0xF88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST10 : 1' means enter stage 1 of VAD, ie a sound change has been detected and the HWVAD is being allowed to settle. Use 0 when changing back to detection mode. Allow several milliseconds in stage 1 for settling.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Normal operation, waiting for HWVAD trigger event (stage 0).
0x1 : RESET
Reset internal interrupt flag by writing a '1' pulse.
End of enumeration elements list.
Phy Ctrl
address_offset : 0xF8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_FALL : Capture DMIC on Falling edge (0 means on rising)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Capture PDM_DATA on the rising edge of PDM_CLK.
0x1 : FALLING_EDGE
Capture PDM_DATA on the falling edge of PDM_CLK.
End of enumeration elements list.
PHY_HALF : Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
0x1 : HALF_RATE
Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
End of enumeration elements list.
HWVAD filter reset register
address_offset : 0xF8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTT : Reset HWVAD. Write back to 0 to release reset.
bits : 0 - 0 (1 bit)
access : read-write
DC Filter Control
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPOLE : DC block filter
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLAT_RESPONSE
Flat response, no filter.
0x1 : HZ_155
155 Hz.
0x2 : HZ_78
78 Hz.
0x3 : HZ_39
39 Hz
End of enumeration elements list.
DCGAIN : Fine gain adjustment in the form of a number of bits to downshift.
bits : 4 - 7 (4 bit)
access : read-write
SATURATEAT16BIT : Selects 16-bit saturation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SATURATE
Results roll over if out range and do not saturate.
0x1 : SATURATE
If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
End of enumeration elements list.
SIGNEXTEND : Sign extend.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DO_NOT_SIGNEXTEND
The top byte of the FIFODATA register is always 0.
0x1 : SIGNEXTEND
The top byte of the FIFODATA register is sign extended. This allows processing of 24-bit audio data on 32-bit machines.
End of enumeration elements list.
HWVAD noise estimator gain register
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THGN : Gain Factor for Noise-floor - use a positive number to make average less sensitive to sudden changes
bits : 0 - 3 (4 bit)
access : read-write
HWVAD signal estimator gain register
address_offset : 0xF94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THGS : Signal Gain factor - use a postive number to make current signal stand out more over longer term average
bits : 0 - 3 (4 bit)
access : read-write
HWVAD noise envelope estimator register
address_offset : 0xF98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOWZ : Average noise-floor value
bits : 0 - 15 (16 bit)
access : read-only
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